KR20000003627A - Method of fabricating capacitor of semiconductor device - Google Patents
Method of fabricating capacitor of semiconductor device Download PDFInfo
- Publication number
- KR20000003627A KR20000003627A KR1019980024887A KR19980024887A KR20000003627A KR 20000003627 A KR20000003627 A KR 20000003627A KR 1019980024887 A KR1019980024887 A KR 1019980024887A KR 19980024887 A KR19980024887 A KR 19980024887A KR 20000003627 A KR20000003627 A KR 20000003627A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- film
- bst film
- gas
- etching
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000003990 capacitor Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000003860 storage Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000004140 cleaning Methods 0.000 claims abstract description 3
- 230000009977 dual effect Effects 0.000 claims description 2
- 229920000642 polymer Polymers 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- UCKMPCXJQFINFW-UHFFFAOYSA-N Sulphide Chemical compound [S-2] UCKMPCXJQFINFW-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 고유전율을 갖는 유전막인 BST((Ba1-xSrx)TiO3)막을 모디파이드 알.아이.이.(modified Reactive Ion Etch) 장비를 이용하여 Ar/Cl2/HBr 혼합가스로 식각하여 소자동작에 충분한 정전용량을 확보하고, 그에 따른 반도체소자의 고집적화를 가능하게 하는 기술에 관한 것이다.The present invention relates to a capacitor manufacturing method of a semiconductor device, especially an Al sulfide in the dielectric film having a high dielectric BST ((Ba 1-x Sr x) TiO 3) film-modify GI this. (Modified Reactive Ion Etch) Equipment The present invention relates to a technology for securing a sufficient capacitance for device operation by etching with an Ar / Cl 2 / HBr mixed gas, thereby enabling high integration of semiconductor devices.
반도체소자가 고집적화됨에 따라 소자의 동작에 필요한 최소한의 저장전극의 용량은 줄어드는데 한계가 있다. 이에 작은 면적에 최소한의 저장전극 용량(C)을 확보하기 위하여 많은 노력을 기울이고 있다. 저장전극 용량은 유전율(ε)과 저장전극 표면적(A)에 비례하고 유전막 두께(d)에 반비례하므로 저장전극의 용량을 증가시키는 방법으로는 여러가지가 있을 수 있지만, 그 중에서 유전율이 큰 물질인 BST((Ba1-xSrx)TiO3), PZT(Pb(ZrTi1-x)O3), Ta2O5등을 이용하여 저장전극 용량을 증가시키는 방법이 현재 많이 연구되고 있다.As semiconductor devices are highly integrated, the capacity of the minimum storage electrode required for the operation of the device is limited. In order to secure a minimum storage electrode capacity (C) in a small area has been put a lot of effort. Since the storage electrode capacity is proportional to the dielectric constant (ε) and the storage electrode surface area (A) and inversely proportional to the dielectric film thickness (d), there are various ways to increase the capacity of the storage electrode. A method of increasing the storage electrode capacity using ((Ba 1-x Sr x ) TiO 3 ), PZT (Pb (ZrTi 1-x ) O 3 ), Ta 2 O 5 , and the like has been studied.
상기와 같이 유전상수가 높은 물질을 사용하려는 시도가 이루어지고 있으며, 상기 강유전체는 상온에서 유전상수가 수백에서 수천에 이르며 두개의 안정한 잔류분극(remainent polarization)상태를 갖고, 박막화하여 전원이 꺼진 상태에서도 데이타를 기억하는 비휘발성(nonvolatile) 메모리인 FeRAM 소자 개발에 적용되고 있다.Attempts have been made to use materials with high dielectric constants as described above, and the ferroelectrics have hundreds to thousands of dielectric constants at room temperature and have two stable residual polarization states, even when the power is turned off by thinning. It is applied to the development of FeRAM device, which is a nonvolatile memory for storing data.
그러나, 상기와 같은 종래기술에 따른 반도체소자의 캐패시터 제조방법은, 여러물질로 구성된 BST를 식각하기 어렵고, 식각공정에 의해 발생되는 폴리머(polymer)의 재증착 때문에 원하는 프로파일(profile)을 얻기 어려운 문제점이 있다.However, the method of manufacturing a capacitor of a semiconductor device according to the prior art as described above is difficult to etch a BST composed of various materials, and it is difficult to obtain a desired profile due to redeposition of a polymer generated by an etching process. There is this.
본 발명은 상기한 문제점을 해결하기 위하여, 유전막인 BST막을 모디파이드 RIE 장비를 사용하여 Ar/Cl2/HBr 혼합가스로 식각함으로써 유전막의 식각공정을 용이하게 함으로써 캐패시터의 정전용량을 향상시켜 소자의 전기적 특성을 향상시키는 반도체소자의 캐패시터 제조방법을 제공하는 데 그 목적이 있다.In order to solve the above problems, the dielectric film is etched with Ar / Cl 2 / HBr mixed gas using a modified RIE device to facilitate the etching process of the dielectric film, thereby improving the capacitance of the capacitor to improve the capacitance of the device. It is an object of the present invention to provide a method for manufacturing a capacitor of a semiconductor device to improve electrical characteristics.
도 1 은 본 발명에 따른 반도체소자의 캐패시터 제조방법에 의해 형성된 BST막의 식각상태도.1 is an etching state diagram of a BST film formed by a method of manufacturing a capacitor of a semiconductor device according to the present invention.
상기 목적을 달성하기 위해 본 발명에 따른 반도체소자의 캐패시터 제조방법은,Capacitor manufacturing method of a semiconductor device according to the present invention to achieve the above object,
반도체기판 상부에 형성된 하부전극 상부에 유전막으로 BST 막을 형성하는 공정과,Forming a BST film with a dielectric film on the lower electrode formed on the semiconductor substrate;
상기 BST 막을 전하저장전극용 마스크를 이용하여 모디파이드 RIE 장비에서 Ar/Cl2/HBr 혼합가스로 식각하는 공정과,Etching the BST film with an Ar / Cl 2 / HBr mixed gas in a modified RIE device using a mask for a charge storage electrode;
상기 BST 막을 세정하는 공정을 포함하는 것을 특징으로 한다.And cleaning the BST film.
이하, 첨부된 도면을 참조하여 본 발명에 따른 반도체 소자의 캐패시터 제조방법에 대하여 상세히 설명을 하기로 한다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1 은 본 발명에 따른 반도체소자의 캐패시터 제조방법에 의해 형성된 BST 막의 식각상태도이다.1 is an etching state diagram of a BST film formed by a method of manufacturing a capacitor of a semiconductor device according to the present invention.
먼저, 반도체기판에 소자분리 절연막, 게이트산화막을 형성하고, 게이트 전극 및 소오스/드레인영역을 구비하는 모스 트랜지스터를 형성한 다음, 비트라인 등의 하부구조물을 형성한다.First, a device isolation insulating film and a gate oxide film are formed on a semiconductor substrate, and a MOS transistor having a gate electrode and a source / drain region is formed, and a substructure such as a bit line is formed.
다음, Pt 또는 Ir/IrO2적층구조 또는 RuO2막을 사용하여 상기 모스 트랜지스터의 소오스/드레인영역에서 전하저장전극 콘택으로 예정되는 부분과 접속되는 하부전극을 형성한다.Next, a Pt or Ir / IrO 2 stacked structure or a RuO 2 film is used to form a lower electrode connected to a portion intended as a charge storage electrode contact in the source / drain region of the MOS transistor.
그 다음, 상기 구조 상부에 BST막으로 유전막을 형성한다.Next, a dielectric film is formed on the structure as a BST film.
다음, 상기 BST막을 전하저장전극용 마스크를 이용하여 식각한다.Next, the BST layer is etched by using a charge storage electrode mask.
상기 식각공정은 모디파이드 RIE 장비에서 Ar/Cl2/HBr 혼합가스를 사용하여 식각한다. 이때, 상기 Ar/Cl2/HBr 혼합가스에서 상기 Ar가스는 10 ∼ 50 sccm, 상기 Cl2가스는 5 ∼ 20 sccm 그리고 상기 HBr 가스는 5 ∼ 30 sccm의 유량으로 혼합되고, 상기 식각공정에서는 상기 Ar 가스는 스퍼터링 효과를 나타내고, 상기 Cl2/HBr 혼합가스는 화학적인 반응을 도와주는 역할을 한다. 특히, 상기 HBr가스는 상기 전하저장전극용 마스크로 사용되는 감광막에 대한 식각선택비를 높여주는 역할을 한다.The etching process is etched using Ar / Cl 2 / HBr mixed gas in the Modified RIE equipment. In the Ar / Cl 2 / HBr mixed gas, the Ar gas is mixed at a flow rate of 10 to 50 sccm, the Cl 2 gas is 5 to 20 sccm and the HBr gas is at a flow rate of 5 to 30 sccm. Ar gas has a sputtering effect, and the Cl 2 / HBr mixed gas serves to help chemical reaction. In particular, the HBr gas serves to increase the etching selectivity for the photoresist used as the mask for the charge storage electrode.
상기 스퍼터링식각공정은 압력이 2 ∼ 9mTorr이고, 500 ∼ 1000W의 MHz 파워와 100 ∼ 300 W의 kHz파워의 듀얼 주파수(dual frequency)를 사용하는 조건에서 300 ∼ 1000 Å/분의 속도로 식각하는 것을 식각조건으로 한다. 상기 식각공정시 상기 전하저장전극용 마스크로 사용되는 감광막 패턴을 인 시튜(in-situ)방법으로 제거하거나, 후속 공정으로 제거한다.In the sputtering etching process, the pressure is 2 to 9 mTorr, and the etching is performed at a speed of 300 to 1000 mW / min under conditions using a dual frequency of 500 to 1000 W MHz power and 100 to 300 W kHz power. It is set as an etching condition. During the etching process, the photoresist pattern used as the mask for the charge storage electrode is removed by an in-situ method or by a subsequent process.
그 다음, 상기 식각공정으로 발생된 식각잔류물 및 폴리머를 EKC, ACT 등의 용액을 사용하여 제거하여 상기 BST막이 80 ∼ 90。의 프로파일로 형성되게 한다. (도 1참조)Then, the etching residue and the polymer generated by the etching process are removed using a solution such as EKC, ACT, so that the BST film is formed in a profile of 80 to 90 °. (See Fig. 1)
상기한 바와 같이 본 발명에 따른 반도체 소자의 캐패시터 제조방법은, 유전막으로 BST((Ba1-xSrx)TiO3)막을 사용하는 경우에 모디파이드 알.아이.이.(modified reactive ion etch, RIE)장비에서 Ar/Cl2/HBr 혼합가스를 이용한 스퍼터링식각방법으로 패터닝함으로써 공정을 용이하게 하고 적은 양의 폴리머가 발생하여 우수한 프로파일을 갖게 하는 이점이 있다.As described above, in the method of manufacturing a capacitor of a semiconductor device according to the present invention, a modified R.I. (modified reactive ion etch) method is used when a BST ((Ba 1-x Sr x ) TiO 3 ) film is used as a dielectric film. Patterning by sputtering etching method using Ar / Cl 2 / HBr mixed gas in RIE) equipment facilitates the process and has the advantage that a small amount of polymer is generated to have an excellent profile.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024887A KR100329612B1 (en) | 1998-06-29 | 1998-06-29 | Capacitor Manufacturing Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024887A KR100329612B1 (en) | 1998-06-29 | 1998-06-29 | Capacitor Manufacturing Method of Semiconductor Device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000003627A true KR20000003627A (en) | 2000-01-15 |
| KR100329612B1 KR100329612B1 (en) | 2002-05-09 |
Family
ID=19541407
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980024887A KR100329612B1 (en) | 1998-06-29 | 1998-06-29 | Capacitor Manufacturing Method of Semiconductor Device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100329612B1 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102498557B1 (en) | 2022-07-15 | 2023-02-10 | (주)태연금속 | Collector for Aluminum ingot manufacturing |
| EP4127796A4 (en) * | 2020-03-31 | 2023-10-11 | Psiquantum Corp. | Patterning method for photonic devices |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3088178B2 (en) * | 1991-04-22 | 2000-09-18 | 日本電気株式会社 | Polysilicon film etching method |
| KR950010874B1 (en) * | 1993-03-19 | 1995-09-25 | 금성일렉트론주식회사 | Process for manufacturing a capacitor of semiconductor device |
| JP3683972B2 (en) * | 1995-03-22 | 2005-08-17 | 三菱電機株式会社 | Semiconductor device |
-
1998
- 1998-06-29 KR KR1019980024887A patent/KR100329612B1/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP4127796A4 (en) * | 2020-03-31 | 2023-10-11 | Psiquantum Corp. | Patterning method for photonic devices |
| KR102498557B1 (en) | 2022-07-15 | 2023-02-10 | (주)태연금속 | Collector for Aluminum ingot manufacturing |
Also Published As
| Publication number | Publication date |
|---|---|
| KR100329612B1 (en) | 2002-05-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20070221974A1 (en) | Method for Forming Ferroelectric Memory Capacitor | |
| KR100329612B1 (en) | Capacitor Manufacturing Method of Semiconductor Device | |
| US6764896B2 (en) | Semiconductor manufacturing method including patterning a capacitor lower electrode by chemical etching | |
| US7015049B2 (en) | Fence-free etching of iridium barrier having a steep taper angle | |
| KR100334528B1 (en) | Capacitor Manufacturing Method of Ferroelectric Ram | |
| KR100337926B1 (en) | Method of forming storage electrode of semiconductor device | |
| KR100353805B1 (en) | A method for forming capacitor in semiconductor device | |
| KR20020003067A (en) | Method for forming semiconductor memory device capable of preventing loss of glue layer during wet cleaning process | |
| KR100677775B1 (en) | Ferroelectric capacitor and Method for forming the same in semiconductor device | |
| KR20030054028A (en) | Method for fabricating semiconductor device | |
| KR100275337B1 (en) | Manufacturing method for capacitor of fedram | |
| KR100772530B1 (en) | Method for forming concave capacitor in semiconductor device | |
| KR20030054310A (en) | Method for fabricating capacitor in semiconductor device | |
| KR20010004293A (en) | Method for forming ferroelectric capacitor capable of preventing short between top and bottom electrode | |
| KR20000042479A (en) | Method for fabricating capacitor of semiconductor device | |
| KR19990055794A (en) | Manufacturing method of semiconductor device | |
| KR20020014229A (en) | Method for forming capacitor having Pt electrode | |
| KR20000042490A (en) | Method for fabricating storage electrode of semiconductor device | |
| KR20040091322A (en) | A method for forming a capacitor of a semiconductor device | |
| KR20000045366A (en) | Method for fabricating storage electrode | |
| KR20030002878A (en) | Method of forming bottom electrode of capacitor | |
| KR20000042387A (en) | Method for manufacturing ferroelectric capacitor of semiconductor device | |
| KR20030042874A (en) | Method of forming memory device | |
| KR19990055811A (en) | Method for forming charge storage electrode of semiconductor device | |
| KR20020002548A (en) | Semiconductor memory device capable of preventing bottom electrode peeling and method for forming the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20100224 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |