KR19990055811A - Method for forming charge storage electrode of semiconductor device - Google Patents
Method for forming charge storage electrode of semiconductor device Download PDFInfo
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- KR19990055811A KR19990055811A KR1019970075766A KR19970075766A KR19990055811A KR 19990055811 A KR19990055811 A KR 19990055811A KR 1019970075766 A KR1019970075766 A KR 1019970075766A KR 19970075766 A KR19970075766 A KR 19970075766A KR 19990055811 A KR19990055811 A KR 19990055811A
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000003860 storage Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 19
- 229920000642 polymer Polymers 0.000 claims abstract description 12
- 150000001412 amines Chemical class 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims abstract description 4
- 239000002904 solvent Substances 0.000 claims abstract description 4
- 239000010408 film Substances 0.000 claims description 51
- 239000002184 metal Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 8
- 239000011229 interlayer Substances 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 2
- 238000000295 emission spectrum Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 claims description 2
- 230000001052 transient effect Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000003786 synthesis reaction Methods 0.000 claims 1
- 239000007772 electrode material Substances 0.000 abstract description 7
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 230000003467 diminishing effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Drying Of Semiconductors (AREA)
Abstract
본 발명은 반도체소자의 전하저장전극 형성방법에 관한 것으로, FeRAM(ferroelectric RAM) 소자의 제조공정에서 전극 재료로 Ir과 IrO2막을 사용하고, HBr, O2및 Ar 혼합 플라즈마로 상기 전극 재료를 건식 방향성 식각한 다음, 식각공정으로 발생한 폴리머를 아민계 용매를 사용하여 제거함으로써 전하저장전극의 전기적 특성을 우수하게 하고, 반도체소자의 특성 및 신뢰성을 향상시키는 기술에 관한 것이다.The present invention relates to a method for forming a charge storage electrode of the semiconductor element, FeRAM (ferroelectric RAM) used in the manufacturing process of the device as an electrode material Ir and IrO 2 film, and dry the electrode material with HBr, O 2 and Ar mixed plasma The present invention relates to a technique for enhancing the electrical characteristics of a charge storage electrode and improving the characteristics and reliability of a semiconductor device by removing the polymer generated by the etching process using an amine-based solvent.
Description
본 발명은 반도체소자의 전하저장전극 형성방법에 관한 것으로서, 특히 Ir 또는 IrO2막을 전극재료로 사용하고, 상기 전극재료를 브롬계 플라즈마로 건식 방향성 식각함으로써 소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a charge storage electrode of a semiconductor device and more particularly to a technique capable of improving characteristics and reliability of a device by using an Ir or IrO 2 film as an electrode material and dry etching the electrode material with a bromine- .
일반적으로, 반도체소자의 고집적화가 증가됨에 따라 캐패시터의 고정전용량이 요구되고 있다. 이를 해결하기 위해 캐패시터의 유전상수가 높은 물질을 사용하거나 유전체막의 두께를 얇게 하거나 전하저장전극의 표면적을 증대시키는 방법 등이 대두되고 있다. 이를 해결하기 위한 방안 중의 하나로서 높은 유전상수를 갖는 물질을 적용하려는 시도가 이루어지고 있다.In general, as the degree of integration of semiconductor devices increases, a fixed amount of capacitors is required. In order to solve this problem, a method of using a material having a high dielectric constant of the capacitor, a method of reducing the thickness of the dielectric film or increasing the surface area of the charge storage electrode has been emerged. An attempt has been made to apply a material having a high dielectric constant as one of the measures to solve this problem.
상기와 같이 유전상수가 높은 물질인 강유전체막은 상온에서 유전상 수가 수백에서 수천에 이르며 두 개의 안정한 잔류분극(remainent polarization) 상태를 갖는 강유전체로 박막화하여 전원이 꺼진 상태에서도 데이타를 기억하는 비휘발성(nonvolatile)메모리인 FeRAM 소자 개발에 적용되고 있다.As described above, the ferroelectric film having a high dielectric constant has a dielectric constant of several hundreds to several thousands at a room temperature, and has two stable remnant polarization states. The nonvolatile (nonvolatile) ) Memory FeRAM devices.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 전극재료로서 Ir과 IrO2를 사용하고, 브롬계 혼합플라즈마로 건식 방향성 식각한 다음, 아민계 용매를 사용하여 식각공정으로 생성된 폴리머를 제거하여 소자의 특성 및 신뢰성을 향상시키는 반도체소자의 전하저장전극 형성방법을 제공하는데 그 목적이 있다.In order to solve the problems of the prior art described above, the present invention has been made to solve the above-mentioned problems in the prior art by using Ir and IrO 2 as the electrode materials, dry-directional etching with a bromine mixed plasma and then removing the polymer produced by the etching process using an amine- And a method of forming a charge storage electrode of a semiconductor device which improves the characteristics and reliability of the device.
도 1 내지 도 3 은 본 발명에 따른 반도체소자의 전하저장전극 형성방법을 도시한 단면도.1 to 3 are sectional views showing a method of forming a charge storage electrode of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호 설명>Description of the Related Art [0002]
11 : 층간절연막 13 : Ir 금속박막11: interlayer insulating film 13: Ir metal thin film
15 : IrO2막17 : 반사방지막15: IrO 2 film 17: antireflection film
19 : 감광막 패턴 21 : 폴리머19: photosensitive film pattern 21: polymer
이상의 목적을 달성하기 위하여 본 발명에 따른 반도체소자의 전하저장전극 형성방법은,According to an aspect of the present invention, there is provided a method of forming a charge storage electrode of a semiconductor device,
FeRAM 소자의 제조공정에 있어서,In the FeRAM device manufacturing process,
반도체기판 상부에 층간절연막을 형성하는 공정과,A step of forming an interlayer insulating film on the semiconductor substrate,
상기 층간절연막 상부에 Ir금속박막/IrO2막의 적층구조로 된 전극용 도전체를 형성하는 공정과,Forming an electrode conductor having a laminated structure of Ir metal thin film / IrO 2 film on the interlayer insulating film;
상기 전극용 도전체 상부에 반사방지막을 형성하는 공정과,Forming an antireflection film on the conductor for the electrode,
전하저장전극용 마스크를 사용하여 상기 반사방지막 및 전극용 도전체를 식각하는 공정과,Etching the conductor for the antireflection film and the electrode using a mask for a charge storage electrode,
상기 식각공정으로 생성된 폴리머를 세정하는 공정을 포함하는 것을 특징으로 한다.And a step of cleaning the polymer produced by the etching process.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1 내지 도 3 은 본 발명에 따른 반도체소자의 전하저장전극 형성방법을 도시한 단면도이다.1 to 3 are cross-sectional views illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention.
먼저, 반도체기판(도시안됨) 상에 소자분리 산화막(도시안됨)과 게이트산화막(도시안됨)을 형성하고, 게이트전극(도시안됨)과 소오스/드레인전극(도시안됨)으로 구성되는 모스 전계효과 트랜지스터를 형성하고 전체표면을 평탄화시킨 후, 상기 구조의 전표면에 SiO2으로 층간절연막(11)을 형성한다.First, a device isolation oxide film (not shown) and a gate oxide film (not shown) are formed on a semiconductor substrate (not shown) and a MOS field effect transistor (not shown) composed of a gate electrode (not shown) and a source / drain electrode And the entire surface is planarized, and then an interlayer insulating film 11 is formed of SiO 2 on the entire surface of the structure.
다음, 상기 층간절연막(11) 상부에 하부전극용 도전층으로 Ir 금속박막(13)과 IrO2막(15)을 각각 500 ∼ 2000 Å두께로 형성한다.Next, an Ir metal thin film 13 and an IrO 2 film 15 are formed as a conductive layer for the lower electrode on the interlayer insulating film 11 to have a thickness of 500 to 2000 Å, respectively.
그 다음, 상기 IrO2막(15) 상부에 반사방지막(17)으로 TiN막을 200 ∼ 400 Å두께로 형성한다.Next, a TiN film is formed to a thickness of 200 to 400 Å by using the antireflection film 17 on the IrO 2 film 15.
그리고, 상기 반사방지막(17) 상부에 전하저장전극으로 예정되는 부분을 보호하는 감광막 패턴(19)을 형성한다. (도 1참조)A photoresist pattern 19 is formed on the antireflection film 17 to protect a portion to be a charge storage electrode. (See Fig. 1)
다음, 상기 감광막 패턴(19)을 식각마스크로 사용하여 상기 반사방지막(17), IrO2막(15) 및 Ir금속박막(13)을 패터닝한다.Next, the antireflection film 17, the IrO 2 film 15, and the Ir metal film 13 are patterned using the photoresist pattern 19 as an etching mask.
먼저, 상기 반사방지막(17) TiN 층은 Cl2/BCl3혼합 플라즈마로 2∼10 mtorr 의 압력에서 30 ∼ 100 w의 바이어스 파워(bias power)를 사용하여 실시하되, 10 ∼ 50%로 과도식각률을 조절함으로써 식각공정시 상기 Cl2/BCl3혼합 플라즈마가 IrO2막(15)과 반응하여 IrClx가 발생하는 것을 최소화한다.First, the TiN layer of the antireflection film 17 is subjected to a bias power of 30 to 100 W at a pressure of 2 to 10 mtorr with a Cl 2 / BCl 3 mixed plasma, and a transient etching rate of 10 to 50% So that the Cl 2 / BCl 3 mixed plasma reacts with the IrO 2 film 15 during the etching process to minimize the generation of IrCl x .
다음, 상기 IrO2막(15) 및 Ir 금속박막(13)은 50 ∼ 200sccm의 HBr 가스에 50 ∼ 100sccm 의 O2가스 및 50 ∼ 200 sccm 의 Ar 가스를 혼합한 플라즈마를 사용하여 상기 반사방지막(17), IrO2막(15) 및 Ir 금속박막(13)의 양측면에 IrBrx계 폴리머를 형성시키면서 방향성 식각을 실시한다.Next, the IrO 2 film 15 and the Ir metal thin film 13 are etched using the plasma obtained by mixing 50-200 sccm of HBr gas with 50-100 sccm of O 2 gas and 50-200 sccm of Ar gas, Directional etching is performed while forming IrBr x based polymer on both sides of the IrO 2 film 17, the IrO 2 film 15 and the Ir metal film 13.
그 다음, 상기 IrO2막(15)은 HBr, Ar 및 O2를 혼합한 플라즈마를 1 ∼ 10mtorr의 압력에서 100 ∼ 500 w의 바이어스 파워를 인가하여 식각함으로써 입사이온에너지를 극대화시킨다.Next, the IrO 2 film 15 is etched by applying a bias power of 100 to 500 W at a pressure of 1 to 10 mtorr to a plasma mixed with HBr, Ar, and O 2 to maximize incident ion energy.
또한, 상기 IrO2막(15)의 정확한 식각시간을 환산하기 위하여 상기 IrO2막(15)의 식각종말점을 O 라디칼(radical)의 광학 발광 스펙트럼으로 측정하여 O 라디칼의 감소점으로 잡는다.Further, in order to convert the exact etching time of the IrO 2 film 15 by measuring the etching end point of the IrO 2 film 15 in the optical emission spectrum of the O radical (radical) takes a point of diminishing the O radical.
그 다음, 상기 Ir 금속박막(13)의 식각공정은 상기 IrO2막(15)과 동일한 플라즈마를 사용하여 1000 ∼ 3000 w의 소오스 파워(souce power)를 인가함으로써 식각속도를 증대시키고, 하부 층간절연막(11)의 손실을 최소화한다.Next, the Ir metal thin film 13 is etched using the same plasma as the IrO 2 film 15 to increase the etch rate by applying a source power of 1000 to 3000 W, (11).
다음, 상기 감광막 패턴(19)은 O2가스와 CF4가스를 혼합한 플라즈마를 사용하여 제거하고, 상기 식각공정시 반사방지막(17), IrO2막(15) 및 Ir금속박막(13)의 측면에 생성된 IrBrx폴리머(21)를 부분적으로 제거한다. (도 2참조)Next, the photoresist pattern 19 is removed using a plasma in which an O 2 gas and a CF 4 gas are mixed, and the antireflection film 17, the IrO 2 film 15, and the Ir metal thin film 13 The IrBr x polymer 21 generated on the side surface is partially removed. (See Fig. 2)
그 다음, 아민(amine)계 용매인 ACT935 또는 EKC265 등을 사용하여 50 ∼ 80 ℃의 온도에서 15 ∼ 25 분 동안 처리하여 상기 IrBrx폴리머(21)를 완전하게 제거한다. (도 3참조)Then, the IrBr x polymer 21 is completely removed by treating it at a temperature of 50 to 80 ° C for 15 to 25 minutes by using an amine type solvent ACT935 or EKC265 or the like. (See Fig. 3)
이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 전하저장전극 형성방법은, FeRAM 소자의 제조공정에서 전극 재료로 Ir과 IrO2막을 사용하고, HBr, O2및 Ar 혼합 플라즈마로 상기 전극 재료를 건식 방향성 식각한 다음, 식각공정으로 발생한 폴리머를 아민계 용매를 사용하여 제거함으로써 전하저장전극의 전기적 특성을 우수하게 하고, 반도체소자의 특성 및 신뢰성을 향상시키는 이점이 있다.A charge storage electrode forming method of a semiconductor device according to the present invention as described above, Ir and IrO 2 film is used, and dry the electrode material with HBr, O 2 and Ar mixed plasma in the manufacturing process of the FeRAM device as an electrode material The polymer generated by the etching process is removed by using an amine-based solvent to improve the electrical characteristics of the charge storage electrode and improve the characteristics and reliability of the semiconductor device.
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| KR1019970075766A KR100457747B1 (en) | 1997-12-27 | 1997-12-27 | Method for forming storage node of semiconductor device to improve electrical characteristic of storage node |
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| KR1019970075766A KR100457747B1 (en) | 1997-12-27 | 1997-12-27 | Method for forming storage node of semiconductor device to improve electrical characteristic of storage node |
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| KR100457747B1 KR100457747B1 (en) | 2005-02-23 |
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| KR100513363B1 (en) * | 1998-06-30 | 2005-11-03 | 주식회사 하이닉스반도체 | Method for manufacturing charge storage electrode of semiconductor device |
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| KR0155866B1 (en) * | 1995-08-10 | 1998-10-15 | 김광호 | Ferroelectric memory device and its manufacturing method |
| KR970018061A (en) * | 1995-09-29 | 1997-04-30 | 김광호 | Metal electrode manufacturing method to prevent the diffusion of oxygen |
| KR100215905B1 (en) * | 1996-01-10 | 1999-08-16 | 구본준 | Method of forming capacitor of semiconductor device |
| KR100359299B1 (en) * | 2001-03-26 | 2002-11-07 | Samsung Electronics Co Ltd | Semiconductor memory device having resist pattern and method for forming metal contact thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100513363B1 (en) * | 1998-06-30 | 2005-11-03 | 주식회사 하이닉스반도체 | Method for manufacturing charge storage electrode of semiconductor device |
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| KR100457747B1 (en) | 2005-02-23 |
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