KR20000003380A - Method for driving a plasma display panel - Google Patents

Abstract

PURPOSE: A plasma display panel driving method is provided to perform different address discharges according to the existence and non-existence of sub-field discharge without a reset period. CONSTITUTION: The plasma display panel driving method comprises the steps of: comparing the existence and non-existence of a previous sub-field discharge with that of a present sub-field discharge; and supplying different address drive voltages from each other according to a comparison result. By the method, different address discharges are performed according to the existence and non-existence of the previous sub-field discharge, power consumption is reduced, and the rate of light and shade is improved.

Description

Method of Driving of Plasma Display Panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device (hereinafter referred to as a PDP), which is one of flat panel display devices. In particular, the present invention relates to a PDP drive capable of performing different address discharges depending on whether a previous subfield is discharged without a reset period. It is about a method.

Recently, as a large flat panel display device is required, research on a plasma display panel (hereinafter referred to as PDP) has been actively conducted. PDP is a display device that displays an image using a gas discharge phenomenon, and is largely classified into a direct current (DC) method and an alternating current (AC) method according to a discharge method.

Referring to FIG. 1, a cell structure of a PDP of a three-electrode alternating current (AC) type which is commonly used is illustrated. Here, FIG. 1A shows a cross-sectional view of the PDP cell cut along the horizontal axis, and FIG. 1B shows a cross-sectional view of the cell cut along the vertical axis.

The cell of the PDP shown in FIG. 1 includes an upper substrate 10 which is a display surface of an image, and a lower substrate 12 arranged in parallel with the upper substrate 10 by the partition 14. The barrier rib 14 isolates cells from each other to provide a discharge space 30 inside the cell. On the upper substrate 10, a pair of sustain electrodes, that is, a scan and sustain electrode (hereinafter referred to as Y sustain electrode) 16 and a sustain electrode (hereinafter referred to as Z sustain electrode) 18 are arranged side by side. The Y and Z sustain electrodes 16 and 18 and the address electrode 20 for causing discharge are disposed on the lower substrate 12. The Y and Z sustain electrodes 16 and 18 and the address electrode 20 are supplied with an alternating current (AC) voltage whose polarity is continuously reversed to maintain the discharge. The upper dielectric layer 22 for charge accumulation is formed flat on the upper substrate 10 on which the Y and Z sustain electrodes 16 and 18 are disposed, and a protective film 24 is formed on the upper dielectric layer 22 surface. Formed. The protective layer 24 protects the upper dielectric layer 22 from the sputtering of plasma particles to extend its lifespan, improve the emission efficiency of secondary electrons, and reduce the change of discharge characteristics due to oxide contamination of the refractory metal. Magnesium oxide (MgO) membrane is mainly used. The lower dielectric layer 26 for charge accumulation is also formed flat on the lower substrate 12 on which the address electrode 20 is disposed, and the intrinsic color visible rays R, G, and B are generated on the lower dielectric layer 26. Phosphor layer 28 is applied so as to capture partition 14. The phosphor layer 28 is excited by a short ultraviolet (Vacuum Ultraviolet (VUV)) generated during gas discharge to generate visible light of red, green, and blue (R, G, B). The discharge space 30 provided inside the cell is mainly filled with a mixed gas of neon (Ne) and xenon (Xe) in order to increase ultraviolet emission efficiency. The cell 32 of the PDP having such a configuration is discharged due to a voltage applied between the address electrode 20 and the Y sustain electrode 16 to form an on state, and a wall charge is formed inside the cell 32. do. Then, when a voltage is applied between the Y and Z sustain electrodes 16 and 18, the discharge continues to occur only in the cell in which the wall charge is formed to emit vacuum ultraviolet rays. This vacuum ultraviolet light excites the phosphor 28 to generate visible light.

FIG. 2 shows a gray scale implementation method of the PDP, and shows a driving sequence of one frame when driven in the subfield method.

In general, when the PDP is driven in a subfield method, one frame corresponding to one screen includes a plurality of temporally separated, for example, eight subfields. In this case, the gradation of one frame is realized by a combination of brightness, that is, luminance values determined by the length of the light emission period in each subfield. In FIG. 2, gray levels from 0 to 255 are implemented by a combination of luminance values 1, 2, 4, 8,..., 128 determined in each subfield. To this end, wall charges are selectively formed in each cell so that a discharge occurs in a cell in which wall charges are formed, and a discharge does not occur in a cell in which wall charges are not formed. Optionally, a section in which wall charges are formed in each cell is called an address period, and a section in which discharge occurs and emits light is called a sustain period. Here, the address period is allocated the same time for each subfield, while the sustain period for which the luminance value is determined is allocated differently for each subfield.

Referring to FIG. 3, a driving waveform of one subfield divided into a reset period, an address period, and a sustain period is shown. Fig. 3A shows the voltage waveform supplied to the address electrode X, (B) shows the voltage waveform supplied to the Y sustain electrode Y, and (C) supplies the Z sustain electrode Z. Shows the voltage waveform.

In Fig. 3, the reset period is a period of initializing so as not to be affected by the previous field in the next address operation. In other words, the sustain discharge occurs in the previous subfield so that the cell with the wall charge and the cell without the wall charge due to the sustain discharge have different results even when the same address discharge is performed. Accordingly, it is necessary to initialize all the cells in the panel under the same conditions so that they can be addressed regardless of the discharge in the previous subfield. To this end, in the reset period, regardless of the previous discharge or not, a large discharge is generated between the Y sustain electrode and the Z sustain electrode by about 2 to 3 so that the wall charge values due to the previous discharge are initialized so that the cells have little meaning. In detail, in the reset period, first, a high voltage is applied between the Y sustain electrode Y and the Z sustain electrode Z to form wall charges in all cells. Then, a sustain pulse is applied to the Y sustain electrode Y to maintain wall charges, and then an erase pulse is applied to neutralize most of the wall charges, thereby maintaining uniform wall charges inside the entire cell. The addressing section is a section for accumulating wall charges such that the next sustain discharge is possible for the pixels to be lit in accordance with the address discharge. The address discharge is generated by the image data pulse applied to the address electrode X and the scanning pulse supplied in series to the Y sustain electrode Y, so that wall charges are formed inside the cell to be lit. The sustain period is a section in which the sustain pulse is raised to the wall charge so that the sustain discharge occurs only for the cells in which the address discharge has occurred. The sustain discharge maintains the discharge in accordance with the sustain pulse applied between the Y sustain electrode Y and the Z sustain electrode Z inside the cell that is lit in the addressing section.

In the PDP driving method, the reset period plays an important role in preventing cell malfunctions, but it is a factor of increasing power consumption by discharging a large discharge even though the screen is not displayed. In addition, despite the non-display period, the minimum luminance value is relatively increased as the light is emitted, and the contrast ratio of the ratio between the minimum and maximum luminance values is lowered.

Accordingly, an object of the present invention is to provide a PDP driving method capable of reducing power consumption by performing address discharge according to the presence or absence of discharge of a previous subfield without requiring a reset period.

Another object of the present invention is to provide a PDP driving method capable of increasing the contrast ratio by discharging an address in accordance with the presence or absence of a discharge of a previous subfield without requiring a reset period.

It is still another object of the present invention to provide a PDP driving method capable of shortening an address period by discharging an address according to whether a previous subfield is discharged without requiring a reset period.

1 is a cross-sectional view showing the structure of a conventional AC PDP cell.

2 is a diagram showing a gray scale implementation method in a conventional PDP.

3 is a waveform diagram of voltage supplied to each electrode of FIG. 1 during one subfield;

4 is a voltage waveform diagram for address discharge in a PDP driving method according to an embodiment of the present invention.

FIG. 5 is a diagram showing stepwise an address discharge phenomenon due to the voltage waveform shown in FIG.

FIG. 6 is a diagram showing stepwise an address discharge phenomenon due to the voltage waveform shown in FIG.

FIG. 7 is a diagram showing stepwise an address discharge phenomenon due to the voltage waveform shown in FIG.

Fig. 8 is a view showing the electrodes disposed on a conventional PDP as a whole.

<Brief description of symbols for the main parts of the drawings>

10: upper substrate 12: lower substrate

14: partition 16: Y sustain electrode

18: Z sustain electrode 20: address electrode

22: upper dielectric layer 24: protective film

26 lower dielectric layer 28 phosphor

30: discharge space 32: cell

34: PDP

In order to achieve the above object, the PDP driving method according to the present invention is characterized in that different address driving voltages are supplied in each case by comparing discharge of the previous subfield with discharge of the current subfield.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 8.

Prior to the description of the embodiment of the present invention, the present invention addresses the previous discharge state so that no reset discharge is necessary. Considering the discharge of the previous subfield and the discharge of the current subfield, the following four cases can be seen.

Case A Case B Case C Case D Previous subfield On On off off Current subfield On off On off

As shown in Table 1, it can be seen that four address modes are generated in the current subfield with respect to the previous state. In detail, when the cell that was turned on by the previous sustain discharge should be turned on in the next sustain discharge, when the cell that has been sustained discharged is turned off, when the cell that is turned off is turned on, and the state of the cell that is turned off is maintained. It is eggplant. Accordingly, the PDP driving method according to the present invention satisfies the above four cases by adjusting the voltage waveforms supplied to the two sustain electrodes and the address electrodes in the address period.

For example, when the PDP has 640 × 480 pixel cells, 1920 address electrodes exist for two sustain electrodes. In other words, each cell includes two sustain electrodes and one address electrode. When the address operation is performed on one scan line, the sustain electrode works the same for all 1920 cells, and thus it is not easy to create a waveform satisfying the above four modes. Therefore, in the present invention, the erase pulse is applied between the two sustain electrodes during the address discharge. In this case, when the erase pulse is applied, B and D can be easily realized by supplying an appropriate voltage to the address electrode. The discharge between the address electrode and the sustain electrode can satisfy A and C.

4 is a voltage waveform diagram illustrating the address discharge in the four modes in the PDP driving method according to an embodiment of the present invention. In FIG. 4, (A) and (B) show voltage waveforms supplied to the Y and Z sustain electrodes, and (C) to (F) show voltage waveforms supplied to the address electrodes respectively corresponding to the address modes.

First, in the case of A, it is necessary to be able to form wall charges so that the cells can be discharged again to the cells where the wall charges are formed by the previous discharge. In this case, when Vf is the discharge start voltage, Vs is the minimum discharge holding voltage, Vz is the supply voltage of the Z sustain electrode, Vy is the supply voltage of the Y sustain electrode, and Va is the address electrode supply voltage of the A mode. The range of voltage is shown in Equation 1 below.

Vf> Vz1 + Vy> Vs, Vz1 = Va, Vs> Vz2 + Va

Here, Vz1 and Vz2 are voltages supplied to the Z sustain electrode in the t1 and t2 sections. First, in the t1 section, a voltage of -Vy is applied to the Y sustain electrode, Vz1 is applied to the Z sustain electrode, and a voltage of Va is applied to the address electrode. Supplied. In this case, a voltage equal to or lower than the discharge start voltage Vf of the voltage between the Y and Z sustain electrodes is applied, but the voltage applied to the discharge space is greater than or equal to the discharge start voltage due to the influence of the wall charge formed by the previous discharge. Discharge will be initiated as shown in (A) of FIG. At the instant of discharge, a voltage below the discharge start voltage is applied between the address electrode and the Y sustain electrode, so that no discharge occurs. However, when the charged particles are filled in the discharge space by the discharge between the Y and Z sustain electrodes, the discharge is also started between the address electrode and the Y sustain electrode which are subjected to a voltage below the discharge start voltage. In this case, as shown in FIG. 5B, the wall charge is not yet formed in the cell. Then, in the period t2, the voltage of -Vz2 is applied to the Z sustain electrode, which is a voltage that does not cause a discharge between the remaining two electrodes, so that a discharge occurs between the address electrode and the Y sustain electrode, so that only the address electrode and the Y sustain electrode are wall discharged. Accumulate. As shown in FIG. 5C, when the wall charges are accumulated on the two electrodes, the voltage applied to the space is applied below the discharge holding voltage and the discharge is extinguished. As described above, in the case of A, erase discharge occurs between the Y and Z sustain electrodes, and address discharge is caused by the space charge generated at this time to form wall charges.

Case B is a case where a wall charge has not been formed by erasing and discharging a cell previously discharged. In this case, the voltage range of each electrode may be represented by Equation 2 below.

Vf> Vz1 + Vy> Vs, 0 <Vb <Vz2, Vz2 <Vy

In the t1 section, the discharge occurs even at a voltage lower than the discharge start voltage Vf between the Y and Z sustain electrodes in the wall charge formed by the previous discharge. At this time, if the address electrode has a voltage applied between the two sustain electrodes, as shown in FIG. Next, when a voltage having a similar magnitude is applied to the Z sustain electrode and the address electrode in the t2 section, the discharge disappears with little voltage difference between the electrodes and there is almost no wall charge as shown in FIG. do. As described above, in case B, the erase cell is turned off by applying a small pulse width to prevent the wall charges from being formed on the Z sustain electrode.

Case C is a case where the wall charge is formed by causing an address discharge when there is no wall charge because there is no discharge before. In this case, the voltage supplied to the address electrode can be expressed by Equation 3 below.

Vc + Vy> Vf

A large voltage equal to or greater than the discharge start voltage Vf is applied between the Y sustain electrode and the address electrode to cause a writing discharge as shown in FIG. 7B to turn on the corresponding cell. At this time, the wall charge is formed inside the cell as shown in FIG.

In the case of D, the discharge does not occur, and a voltage in the range as shown in Equation 4 below is applied to the address electrode.

Vy> Vd> Vz2

In this case, since there is no wall charge, there is no effect on the cell even if an erase pulse is applied between the Y and Z sustain electrodes.

8 shows an electrode structure arranged in a conventional PDP.

When the total pixel size is 640x480, the number of address electrodes becomes 1920 corresponding to three phosphors of red, green, and blue. First, a voltage as shown in FIGS. 4A and 4B is applied between the Y and Z sustain electrodes, and a voltage is applied to the address electrode according to the four modes described above. At this time, since the voltage applied to the address electrode should cause different address discharge according to the result of the previous sustain discharge, the voltage is determined by combining the previous discharge pattern with the current discharge pattern.

Address discharge is performed in a linear order. In other words, an address discharge is first performed between the first Y and Z sustain electrodes Y1 and Z1 and the address electrodes X1 to X1920 of the first scan line, and then the address discharge is transferred to the second scan line. As described above, when the address discharge is continuously performed up to 480 scan lines, the address discharge is completed, and then the sustain voltage is supplied between the Y and Z sustain electrodes so that the discharge is maintained only in the cell in which wall charge is formed by the address discharge.

As described above, according to the PDP driving method according to the present invention, power consumption can be reduced by performing different address discharges depending on the presence or absence of a previous discharge without the need for a reset period. In addition, according to the PDP driving method according to the present invention, as the reset period is not necessary, the minimum luminance value decreases and the contrast ratio increases, thereby making the screen clearly visible. In addition, according to the PDP driving method according to the present invention, as the reset period is not necessary, the address period is shortened and the sustain period is increased, thereby increasing luminance and facilitating high resolution.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A driving method of a plasma display panel in which pixel cells including first and second sustain electrodes and an address electrode are arranged in a matrix form, And comparing the discharge of the previous subfield with the discharge of the current subfield and supplying different address driving voltages to the pixel cells in each case. The method of claim 1, And a driving voltage pulse for each of the above cases is applied to the address electrode. The method of claim 1, First and second scan pulses synchronized with the driving voltage pulses are simultaneously supplied to the first and second sustain electrodes, and the first and second scan pulses are supplied for each scan line. . The method of claim 3, wherein And a second scan pulse supplied to the second sustain electrode having voltages of first and second states. The method of claim 1, And when a pixel cell is turned on in a previous subfield and also needs to be turned on in a current subfield, a voltage is added to the address electrode to cause writing discharge. The method of claim 5, Vf is the discharge start voltage, Vs is the minimum discharge holding voltage, Vz1 and Vz2 are the first and second voltages supplied to the Z sustain electrode in the periods t1 and t2, Vy is the supply voltage of the Y sustain electrode, and Va is the address. In terms of electrode supply voltage, the range of voltage supplied to each electrode is Vf> Vz1 + Vy> Vs, Vz1 = Va, Vs> Vz2 + Va Plasma display panel driving method characterized in that. The method of claim 1, When an arbitrary pixel cell is turned on in the previous subfield and should be turned off in the current subfield, an erase discharge is caused by the scan pulse supplied to the first sustain electrode and the first voltage of the scan pulse supplied to the second sustain electrode. A plasma display panel driving method. The method of claim 7, wherein Vf is the discharge start voltage, Vs is the minimum discharge holding voltage, Vz1 and Vz2 are the voltages supplied to the second sustain electrode in the periods t1 and t2, Vy is the supply voltage of the second sustain electrode, and Vb is the address electrode supply voltage. In this case, the range of the voltage supplied to each electrode is Vf> Vz1 + Vy> Vs, 0 <Vb <Vz2, Vz2 <Vy Plasma display panel driving method characterized in that. The method of claim 1, When a pixel cell is turned off in the previous subfield and turned on in the current subfield, a relatively high voltage is applied to the address electrode so as to cause a scanning pulse and a writing discharge supplied to the first sustain electrode. Plasma Display Panel Driving Method. The method of claim 1, When any pixel cell is to be turned off in the previous subfield and also to be turned off in the current subfield, the address electrode includes a first scan pulse supplied to the first sustain electrode and a second scan pulse supplied to the second sustain electrode. A plasma display panel driving method, wherein a voltage between voltages is applied.