KR20000003359A - Metal wire forming method for semiconductor device - Google Patents

Metal wire forming method for semiconductor device Download PDF

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Publication number
KR20000003359A
KR20000003359A KR1019980024589A KR19980024589A KR20000003359A KR 20000003359 A KR20000003359 A KR 20000003359A KR 1019980024589 A KR1019980024589 A KR 1019980024589A KR 19980024589 A KR19980024589 A KR 19980024589A KR 20000003359 A KR20000003359 A KR 20000003359A
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South Korea
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layer
forming
film
semiconductor device
silicon layer
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KR1019980024589A
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Korean (ko)
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이상협
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김영환
현대전자산업 주식회사
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Priority to KR1019980024589A priority Critical patent/KR20000003359A/en
Publication of KR20000003359A publication Critical patent/KR20000003359A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855—After-treatment introducing at least one additional element into the layer
    • H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A metal wire forming method is provided to produce a metal wire preventing the loss of Si according to the reaction of a silicon substrate to an adhesion layer. CONSTITUTION: A metal wire is formed by the steps of: evaporating an interlayer insulating film(3) onto a silicon substrate(1) and forming a bit line contact hole to expose a contact layer(2) by etching the interlayer insulating film; evaporating polycrystalline silicon film(4) onto the exposed contact layer; and evaporating Ti film(5) onto the whole structure, Ti film(6) thereunto and tungsten film(7) thereunto.

Description

반도체 장치의 금속배선 형성방법Metal wiring formation method of semiconductor device

본 발명은 반도체 기술분야에 관한 것으로, 특히 반도체 장치 제조공정 중 비트라인 등의 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor technology, and more particularly, to a method for forming metal wiring such as bit lines in a semiconductor device manufacturing process.

일반적으로, 반도체 장치에서 금속배선을 형성하는데 있어서, 녹는점이 높고 비저항이 낮은 텅스텐(W)을 많이 사용하고 있다. 텅스텐은 10∼20μΩ㎝의 매우 낮은 비저항을 가지며, 모서리 도포성이 우수한 장점이 있다. 따라서, 반도체 장치의 신호전달 속도를 향상시키고, 비트라인 등의 금속배선의 길이를 길게 가져갈 수 있게 되어 반도체 장치 설계시의 마진을 개선하고 칩 크기를 줄일 수 있는 장점이 있다.In general, in forming a metal wiring in a semiconductor device, tungsten (W) having a high melting point and low specific resistance is often used. Tungsten has a very low resistivity of 10 to 20 µΩcm, and has an advantage of excellent edge coatability. Therefore, the signal transmission speed of the semiconductor device can be improved, and the length of the metal wiring such as the bit line can be long, thereby improving the margin when designing the semiconductor device and reducing the chip size.

텅스텐을 금속배선에 적용하기 위해서는 접착층으로서 TiN막을 필요로 하며, 접합층과의 접촉저항을 낮추기 위하여 Ti막을 사용하는 것이 통상적이다. 즉, 콘택홀 형성후, Ti/TiN/W 적층 구조의 금속배선을 형성하는 것이다.In order to apply tungsten to the metal wiring, a TiN film is required as the adhesive layer, and a Ti film is usually used to lower the contact resistance with the bonding layer. That is, after forming the contact hole, the metal wiring of the Ti / TiN / W laminated structure is formed.

그러나, 이러한 종래의 Ti/TiN/W 적층 구조의 금속배선에서 Ti가 접합층의 단결정실리콘과 접하게 되어 후속 고온 열공정시 티타늄실리사이드(TiSi2)로 변환되는데, 티타늄실리사이드는 750℃ 이상의 온도에서 상변이와 함께 응집되는 특성을 나타내어 접합층의 깊이를 크게 감소시키는 문제점이 유발된다. 또한 접합층에 도핑된 도펀트까지 흡수하기도 하여 반도체 장치의 동작 특성을 크게 열화시키는 문제점이 있었다.However, in the metal wiring of the conventional Ti / TiN / W laminated structure, Ti comes into contact with single crystal silicon of the bonding layer and is converted into titanium silicide (TiSi 2 ) during a subsequent high temperature thermal process, and the titanium silicide is phase-transformed at a temperature of 750 ° C. or higher. It exhibits the property of coagulation with causes a problem of greatly reducing the depth of the bonding layer. In addition, the dopant doped to the bonding layer is also absorbed, which greatly deteriorates the operating characteristics of the semiconductor device.

이러한 문제점은 비단 Ti/TiN/W 적층 구조의 금속배선 공정시에만 유발되는 것이 아니라, 거의 모든 금속배선에서 유발되고 있어 이에 대한 해결 방안이 요구되고 있다.This problem is not only caused during the metallization process of the Ti / TiN / W laminated structure, but is caused in almost all metallizations, and thus a solution for this problem is required.

본 발명은 실리콘 기판(접합층)과 접착층(또는 장벽금속)의 반응에 따른 Si 손실을 방지하는 반도체 장치의 금속배선 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming metal wiring in a semiconductor device which prevents Si loss due to the reaction of a silicon substrate (bonding layer) and an adhesive layer (or barrier metal).

도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 금속 비트라인 형성 공정도.1A through 1D are diagrams illustrating a metal bit line forming process according to an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

1 : 실리콘 기판 2 : 접합층1 silicon substrate 2 bonding layer

3 : 층간절연막 4 : 다결정실리콘막3: interlayer insulating film 4: polysilicon film

5 : Ti막 6 : TiN막5: Ti film 6: TiN film

7 : 텅스텐막 8 : 티타늄실리사이드막7: tungsten film 8: titanium silicide film

상기 목적을 달성하기 위하여 본 발명의 반도체 장치의 금속배선 형성방법은 층간절연막을 관통하여 실리콘 기판상의 접합층을 노출시키는 콘택홀을 형성하는 제1 단계; 상기 제1 단계 수행후, 상기 콘택홀 저면에 실리콘층을 제공하는 제2 단계; 상기 제2 단계 수행후, 전체구조 상부에 접착층을 형성하는 제3 단계; 및 상기 접착층과 상기 실리콘층의 상호반응을 유도하여 실리사이드층을 형성하는 제4 단계를 포함한다.In order to achieve the above object, the method for forming a metal wiring of the semiconductor device of the present invention comprises: a first step of forming a contact hole through the interlayer insulating film to expose a bonding layer on a silicon substrate; A second step of providing a silicon layer on a bottom surface of the contact hole after performing the first step; A third step of forming an adhesive layer on the entire structure after performing the second step; And a fourth step of inducing a mutual reaction between the adhesive layer and the silicon layer to form a silicide layer.

즉, 본 발명은 접합층(실리콘 기판)과 접착층의 반응을 최대한 억제하기 위하여 접합층과 접착층 사이에 실리콘층을 삽입하는 것이다. 즉, 실리콘층을 접착층에 Si를 제공하는 희생막으로 사용하여 접합층에서의 Si 손실을 최소화한다. 여기서, 실리콘층의 두께는 이후 접착층과 반응하여 모두 실리사이드막으로 변환될 수 있도록 얇게 형성한다. 이는 접합층의 단결정실리콘과 실리사이드막을 접촉시키는 것이 접촉저항 측면에서 유리하고, N+및 P+접합층에서도 오믹(ohmic) 콘택이 가능하기 때문이다.That is, the present invention is to insert a silicon layer between the bonding layer and the adhesive layer in order to suppress the reaction of the bonding layer (silicon substrate) and the adhesive layer as much as possible. That is, the silicon layer is used as a sacrificial film for providing Si to the adhesive layer to minimize Si loss in the bonding layer. Here, the thickness of the silicon layer is formed to be thin so that all can be converted into a silicide film by reacting with the adhesive layer. This is because contacting the single crystal silicon and the silicide film of the bonding layer is advantageous in terms of contact resistance, and ohmic contact is also possible in the N + and P + bonding layers.

이하, 본 발명의 바람직하고 용이한 실시를 위하여 그 실시예를 소개한다.Hereinafter, the embodiments of the present invention will be introduced for preferred and easy implementation.

첨부된 도면 도 1a 내지 도 1d는 본 발명의 일 실시예에 따른 금속 비트라인 형성 공정을 도시한 것으로, 이하 이를 참조하여 그 공정을 살펴본다.1A to 1D illustrate a metal bit line forming process according to an exemplary embodiment of the present invention. Hereinafter, the process will be described with reference to the drawing.

우선, 도 1a에 도시된 바와 같이 트랜지스터 형성 공정을 마친 실리콘 기판(1) 상에 층간절연막(3)을 증착하고, 층간절연막(3)을 선택식각하여 접합층(2)을 노출시키는 비트라인 콘택홀을 형성한다.First, as shown in FIG. 1A, an interlayer insulating film 3 is deposited on a silicon substrate 1 having a transistor forming process, and the bit line contact to expose the bonding layer 2 by selectively etching the interlayer insulating film 3. Form a hole.

다음으로, 도 1b에 도시된 바와 같이 노출된 접합층(2) 상에 다결정실리콘막(4)을 50∼1000Å 두께로 선택증착한다.Next, the polysilicon film 4 is selectively deposited to a thickness of 50 to 1000 GPa on the exposed bonding layer 2 as shown in FIG. 1B.

이어서, 도 1c에 도시된 바와 같이 전체구조 상부에 50∼1000Å 두께의 Ti막(5)을 증착하고, 그 상부에 역시 50∼1000Å 두께의 TiN막(6)을 MOCVD(Metal Organic CVD)법으로 증착하고, 플라즈마 처리를 통해 확산 베리어 특성을 강화시킨다. 이어서, TiN막(6) 상에 배선 재료인 텅스텐막(7)을 증착한다.Subsequently, as shown in FIG. 1C, a Ti film 5 having a thickness of 50 to 1000 GPa is deposited on the entire structure, and a TiN film 6 having a thickness of 50 to 1000 GPa is also deposited on the upper layer by MOCVD (Metal Organic CVD). Deposition and plasma treatment to enhance diffusion barrier properties. Next, a tungsten film 7 as a wiring material is deposited on the TiN film 6.

다음으로, 도 1d는 후속 열공정에 의해 다결정실리콘막(4)의 Si와 Ti막(5)의 Ti가 반응하여 준안정상인 C49상의 티타늄실리사이드(TiSi2)막(8)이 형성된 상태를 나타낸 것이다. 실리사이드화를 위한 열처리는 Ti막(5) 형성 직후 또는 TiN막(6) 형성 직후 급속열처리(RTA) 방식으로 수행할 수 있으며, 급속열처리 온도는 400∼750℃로 한다.Next, FIG. 1D shows a state in which the Si 49 of the polysilicon film 4 and the Ti of the Ti film 5 react to form a metastable C49-type titanium silicide (TiSi 2 ) film 8 by a subsequent thermal process. will be. The heat treatment for silicidation may be performed immediately after the Ti film 5 is formed or immediately after the TiN film 6 is formed by a rapid heat treatment (RTA) method. The rapid heat treatment temperature is 400 to 750 ° C.

본 발명의 다른 실시예는 다결정실리콘막(4)을 전면증착하는 것이다.Another embodiment of the present invention is to deposit all of the polysilicon film 4.

전술한 실시예에서는 접착층(또는 장벽금속층)으로 Ti/TiN막을 사용하였으나, 실리사이드화가 가능한 접착층이면 이를 대체할 수 있다. 또한, 배선 재료로서 텅스텐 이외의 금속을 사용할 수 있다. 그리고, 단결정실리콘막 등의 실리콘층으로 다결정실리콘막을 대체하여 사용할 수 있다.In the above-described embodiment, a Ti / TiN film is used as the adhesive layer (or barrier metal layer), but it may be replaced with a silicideable adhesive layer. As the wiring material, metals other than tungsten can be used. In addition, the polycrystalline silicon film can be replaced with a silicon layer such as a single crystal silicon film.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

이상에서와 같이 본 발명은 금속배선 특히, 금속 비트라인 형성시의 장애물로 작용하는 실리사이드화에 의한 접합층의 Si 손실을 최소화할 수 있어 반도체 장치의 동작 특성을 개선하는 효과가 있다.As described above, the present invention can minimize the Si loss of the bonding layer due to the silicidation acting as an obstacle when forming the metal wiring, in particular, the metal bit line, thereby improving the operating characteristics of the semiconductor device.

Claims (9)

층간절연막을 관통하여 실리콘 기판상의 접합층을 노출시키는 콘택홀을 형성하는 제1 단계;Forming a contact hole through the interlayer insulating film to expose the bonding layer on the silicon substrate; 상기 제1 단계 수행후, 상기 콘택홀 저면에 실리콘층을 제공하는 제2 단계;A second step of providing a silicon layer on a bottom surface of the contact hole after performing the first step; 상기 제2 단계 수행후, 전체구조 상부에 접착층을 형성하는 제3 단계; 및A third step of forming an adhesive layer on the entire structure after performing the second step; And 상기 접착층과 상기 실리콘층의 상호반응을 유도하여 실리사이드층을 형성하는 제4 단계A fourth step of inducing a mutual reaction between the adhesive layer and the silicon layer to form a silicide layer 를 포함하는 반도체 장치의 금속배선 형성방법.Metal wiring forming method of a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 제3 단계 수행후, 전체구조 상부에 배선 금속층을 형성하는 제5 단계를 더 포함하는 반도체 장치의 금속배선 형성방법.And performing a third step of forming a wiring metal layer on the entire structure after performing the third step. 제 1 항에 있어서,The method of claim 1, 상기 제4 단계 수행후, 전체구조 상부에 배선 금속층을 형성하는 제6 단계를 더 포함하는 반도체 장치의 금속배선 형성방법.And a sixth step of forming a wiring metal layer on the entire structure after performing the fourth step. 제 2 항 또는 제 3 항에 있어서,The method of claim 2 or 3, 상기 실리콘층이 단결정실리콘층 또는 다결정실리콘층인 반도체 장치의 금속배선 형성방법.And wherein said silicon layer is a single crystal silicon layer or a polycrystalline silicon layer. 제 2 항 또는 제 3 항에 있어서,The method of claim 2 or 3, 상기 접착층이 Ti층을 포함하는 반도체 장치의 금속배선 형성방법.The metal wiring forming method of the semiconductor device in which the said contact bonding layer contains a Ti layer. 제 4 항에 있어서,The method of claim 4, wherein 상기 제2 단계에서 상기 실리콘층이 전면증착 방식 또는 선택증착 방식으로 제공되는 반도체 장치의 금속배선 형성방법.The metal layer forming method of the semiconductor device in the second step wherein the silicon layer is provided by a full surface deposition method or a selective deposition method. 제 2 항 또는 제 3 항에 있어서,The method of claim 2 or 3, 상기 제4 단계가 급속열처리 또는 후속 열공정에 의해 이루어지는 반도체 장치의 금속배선 형성방법.Wherein the fourth step is a rapid thermal treatment or a subsequent thermal process. 제 4 항에 있어서,The method of claim 4, wherein 상기 실리콘층이 50 내지 1000Å 두께로 제공되는 반도체 장치의 금속배선 형성방법.And forming a silicon layer with a thickness of 50 to 1000 microns. 제 7 항에 있어서,The method of claim 7, wherein 상기 급속열처리가 400 내지 750℃ 온도에서 이루어지는 반도체 장치의 금속배선 형성방법.And the rapid thermal treatment is performed at a temperature of 400 to 750 캜.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100460065B1 (en) * 2002-07-12 2004-12-04 주식회사 하이닉스반도체 method for manufacturing bit line in semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100460065B1 (en) * 2002-07-12 2004-12-04 주식회사 하이닉스반도체 method for manufacturing bit line in semiconductor device

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