KR100521052B1 - Method of forming a tungsten bit-line in a semiconductor device - Google Patents
Method of forming a tungsten bit-line in a semiconductor device Download PDFInfo
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- KR100521052B1 KR100521052B1 KR10-1999-0025451A KR19990025451A KR100521052B1 KR 100521052 B1 KR100521052 B1 KR 100521052B1 KR 19990025451 A KR19990025451 A KR 19990025451A KR 100521052 B1 KR100521052 B1 KR 100521052B1
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- tungsten
- titanium
- bit line
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- 229910052721 tungsten Inorganic materials 0.000 title claims abstract description 44
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 title claims abstract description 43
- 239000010937 tungsten Substances 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 27
- 229910001080 W alloy Inorganic materials 0.000 claims abstract description 28
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims abstract description 27
- 239000010936 titanium Substances 0.000 claims abstract description 14
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 238000010438 heat treatment Methods 0.000 claims abstract description 12
- 230000004888 barrier function Effects 0.000 claims abstract description 11
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 10
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910021342 tungsten silicide Inorganic materials 0.000 claims abstract description 9
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 6
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 14
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 239000003990 capacitor Substances 0.000 abstract description 9
- 230000008054 signal transmission Effects 0.000 abstract description 2
- 229910001069 Ti alloy Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005121 nitriding Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- NMJKIRUDPFBRHW-UHFFFAOYSA-N titanium Chemical class [Ti].[Ti] NMJKIRUDPFBRHW-UHFFFAOYSA-N 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
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- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체 소자의 텅스텐 비트라인 형성 방법에 관한 것으로, 텅스텐 비트라인의 확산 장벽층으로 비저항이 낮은 티타늄-텅스텐 합금을 형성한 후 질소 분위기에서 급속 열처리를 실시하여, 티타늄-텅스텐 합금층과 접합 영역 계면에 티타늄/텅스텐 실리사이드막이 형성되고 티타늄/텅스텐 합금층 표면에 티타늄 나이트라이드막이 형성되도록 하여, 캐패시터 형성을 위한 후속 열공정에도 우수한 신호 전달 특성을 나타낼 수 있도록 한 반도체 소자의 텅스텐 비트라인 형성 방법이 개시된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a tungsten bit line in a semiconductor device, and to forming a titanium-tungsten alloy having a low resistivity as a diffusion barrier layer of a tungsten bit line, and then performing rapid heat treatment in a nitrogen atmosphere, thereby joining the titanium-tungsten alloy layer. Titanium / tungsten silicide film is formed at the interface of the region and the titanium nitride film is formed on the surface of the titanium / tungsten alloy layer, so that the tungsten bit line forming method of the semiconductor device can exhibit excellent signal transmission characteristics in subsequent thermal processes for forming the capacitor. This is disclosed.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 텅스텐 비트라인의 확산 장벽층으로서 비저항이 낮은 티타늄-텅스텐 합금층을 사용하므로써 이후의 캐패시터 형성을 위한 고온의 열공정시 비트라인과 접합영역의 접합 특성이 열화되는 것을 방지할 수 있는 반도체 소자의 텅스텐 비트라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, by using a titanium-tungsten alloy layer having a low resistivity as a diffusion barrier layer of a tungsten bit line, the bonding characteristics of the bit line and the junction region during high temperature thermal processing for subsequent capacitor formation The present invention relates to a tungsten bit line forming method of a semiconductor device capable of preventing this deterioration.
반도체 메모리 소자에서 비트라인은 트랜지스터로부터 전하를 받아 센스앰프로 전달하는 배선으로 사용된다. 이와 같은 역할을 하는 비트라인은 저항이 작아야 하고, 트랜지스터의 소오스/드레인 지역에서 오믹 콘택(ohmic contact)을 형성해야 하며, 후속 열공정에 의해 열화되지 않는 특성을 가져야 한다. 종래에는 도프트 폴리실리콘과 텅스텐 실리사이드의 적층 구조로 비트라인을 형성하였는데, 이와 같은 구조의 비트라인은 소자의 집적도 증가와 고속의 정보 처리 능력을 요구하는 차세대 반도체 메모리 소자에 있어서는 높은 면저항 값에 기인하여 그 적용에 한계가 있다.In a semiconductor memory device, a bit line is used as a wiring for receiving charge from a transistor and transferring it to a sense amplifier. Bitlines that do this must have a low resistance, form ohmic contacts in the source / drain regions of the transistor, and must not be degraded by subsequent thermal processes. Conventionally, a bit line is formed by a stacked structure of doped polysilicon and tungsten silicide, which is caused by high sheet resistance in a next-generation semiconductor memory device requiring an increase in device density and high information processing capability. There is a limit to its application.
이에 따라 최근에는 도프트 폴리실리콘/텅스텐 실리사이드 구조의 비트라인을 대체하여 고속의 신호전달을 가능하게 하는 텅스텐 비트라인 구조가 연구되고 있다. 텅스텐 비트라인은 데이터를 저장하는 캐패시터가 형성되지 않는 기판의 주변 영역에 형성되며, 이러한 주변 영역에 텅스텐 비트라인을 형성하게 되면 접합 영역이 N+인지 P+인지에 관계없이 비트라인 콘택의 형성이 가능하다. 또한, 비트라인의 저항이 감소되어 소자의 고속 동작을 가능하게 한다. 따라서 기존의 도프트 폴리실리콘/텅스텐 실리사이드 비트라인 구조에서 주변 영역에 NMOS만을 제작하던 형태를 벗어나 주변 영역에 NMOS, PMOS를 모두 형성할 수 있는 장점이 있다.Accordingly, recently, a tungsten bit line structure that replaces a bit line of a doped polysilicon / tungsten silicide structure and enables high-speed signal transmission has been studied. Tungsten bit lines are formed in the peripheral area of the substrate where no capacitors for storing data are formed. When the tungsten bit line is formed in such a peripheral area, the formation of the bit line contact is performed regardless of whether the junction area is N + or P + . It is possible. In addition, the resistance of the bit line is reduced to enable high speed operation of the device. Therefore, the conventional doped polysilicon / tungsten silicide bit line structure has a merit that it is possible to form both NMOS and PMOS in the peripheral region instead of manufacturing only NMOS in the peripheral region.
이러한 텅스텐 비트라인 형성을 위해 텅스텐을 증착할 때에는 WF6/SiH4/H2 기체를 사용한 CVD 방법을 사용하는데, CVD 방법을 사용하는 경우에는 텅스텐을 실리콘 기판이나 산화막 위에 직접 증착할 수 없고, 오믹 콘택을 형성하기 위하여 텅스텐을 증착하기 전 확산 장벽층을 증착해야 한다.When tungsten is deposited to form the tungsten bit line, a CVD method using a WF 6 / SiH 4 / H 2 gas is used. In the case of using the CVD method, tungsten cannot be directly deposited on a silicon substrate or an oxide film. The diffusion barrier layer must be deposited prior to depositing tungsten to form a contact.
종래에는 확산 장벽층으로 티타늄-티타늄 나이트라이드층의 적층 구조를 사용하였다. 그런데, COB(Capacitor Over Bitline) 구조에서는 텅스텐 비트라인 형성 이후 캐패시터를 제작하는 공정을 진행해야 하며, 이 경우 ONO 유전체막 구조의 캐패시터를 형성하게 되면 750℃ 이상의 고온에서 열처리를 실시해야 한다. 이 고온 열처리 과정에서 확산 장벽층의 하부층인 티타늄과 실리콘 기판의 실리콘이 심하게 반응하여 TiSi2로 응집되는 현상이 나타나 콘택 저항이 크게 증가하는 문제점이 있다.In the related art, a laminated structure of a titanium-titanium nitride layer was used as the diffusion barrier layer. However, in the COB (Capacitor Over Bitline) structure, after the formation of the tungsten bit line, a process of manufacturing a capacitor must be performed. In this case, when a capacitor having an ONO dielectric film structure is formed, heat treatment must be performed at a high temperature of 750 ° C or higher. In this high temperature heat treatment process, titanium, which is a lower layer of the diffusion barrier layer, and silicon of the silicon substrate react violently to agglomerate to TiSi 2 , resulting in a large increase in contact resistance.
따라서, 본 발명은 텅스텐 비트라인의 확산 장벽층으로 비저항이 낮은 티타늄-텅스텐 합금을 사용하므로써 후속 캐패시터 형성을 위한 고온 열공정에도 비트라인의 특성이 열화되지 않는 반도체 소자의 텅스텐 비트라인 형성 방법을 제공하는데 그 목적이 있다.Accordingly, the present invention provides a method for forming a tungsten bit line in a semiconductor device in which the characteristics of the bit line are not deteriorated even by a high temperature thermal process for forming a subsequent capacitor by using a low-resistance titanium-tungsten alloy as a diffusion barrier layer of the tungsten bit line. Its purpose is to.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 텅스텐 비트라인 형성 방법은 접합 영역, 워드라인 등의 하부구조가 형성된 반도체 기판 상에 층간 절연막을 형성하고, 상기 반도체 기판 접합 영역이 노출되도록 상기 층간 절연막을 식각하여 비트라인 콘택을 형성하는 단계; 전체구조 상에 티타늄-텅스텐 합금막을 형성하는 단계; 질소 분위기에서 급속 열처리를 실시하고, 이로 인하여 상기 반도체 기판의 접합 영역과 티타늄-텅스텐 합금막의 계면에 육방정계 구조의 티타늄/텅스텐 실리사이드막이 형성되는 한편, 상기 티타늄-텅스텐 합금막 표면에 티타늄 나이트라이드막이 형성되어, 상기 티타늄-텅스텐 합금막과 티타늄 나이트라이드막이 적층된 확산 장벽층이 형성되는 단계; 전체구조 상에 비트라인용 텅스텐층을 형성하고 패터닝하여 텅스텐 비트라인을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다. Tungsten bit line forming method of a semiconductor device according to the present invention for achieving the above object is to form an interlayer insulating film on a semiconductor substrate formed with a substructure, such as a junction region, a word line, and the like to expose the semiconductor substrate junction region Etching the interlayer insulating film to form a bit line contact; Forming a titanium-tungsten alloy film on the entire structure; Rapid heat treatment is performed in a nitrogen atmosphere, thereby forming a titanium / tungsten silicide film having a hexagonal structure at the interface between the junction region of the semiconductor substrate and the titanium-tungsten alloy film, while the titanium nitride film is formed on the surface of the titanium-tungsten alloy film. Forming a diffusion barrier layer in which the titanium-tungsten alloy film and the titanium nitride film are stacked; And forming a tungsten layer for bit lines on the entire structure to form a tungsten bit line.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 1a 내지 1b는 본 발명에 따른 반도체 소자의 텅스텐 비트라인 형성 방법을 설명하기 위해 도시한 소자의 단면도이다.1A to 1B are cross-sectional views illustrating a device for forming a tungsten bit line in a semiconductor device according to the present invention.
도 1a에 도시된 바와 같이, 접합 영역, 워드라인 등의 하부구조가 형성된 반도체 기판(11) 상에 층간 절연막을 형성하고, 반도체 기판(11)의 접합 영역이 노출되는 비트라인 콘택(13)을 형성한다. 이후, 전체구조 상에 티타늄-텅스텐 합금막(14A)을 형성한다. 티타늄-텅스텐 합금막(14A)은 티타늄이 텅스텐에 고용된 형태로 존재하며, 실리콘과 접한 상태에서 열처리를 할 경우 순수 티타늄막이 실리콘과 반응하는 것에 비해 느린 속도로 실리콘과 반응한다. 이는 열처리 초기에 실리콘과 티타늄-텅스텐 합금막(14A)의 계면에서 생성되는 WSi2를 통한 실리콘의 확산이 어려워, 그만큼 티타늄과 실리콘의 반응이 억제되기 때문이다. 여기에서, 티타늄-텅스텐 합금막(14A)내의 티타늄의 조성은 5 내지 15wt%로 한다. 또한, 티타늄-텅스텐 합금막(14A)은 300 내지 600℃의 온도조건 및 5 내지 20mTorr의 압력조건에서 5 내지 15kW의 전력을 공급하여 스퍼터링 방법으로 형성하며, 두께는 200 내지 1000Å이 되도록 한다.As shown in FIG. 1A, an interlayer insulating layer is formed on a semiconductor substrate 11 on which substructures such as a junction region and a word line are formed, and a bit line contact 13 exposing the junction region of the semiconductor substrate 11 is exposed. Form. Thereafter, a titanium-tungsten alloy film 14A is formed on the entire structure. The titanium-tungsten alloy film 14A exists in a form in which titanium is dissolved in tungsten. When the heat treatment is performed in contact with silicon, the titanium-tungsten alloy film 14A reacts with silicon at a slower rate than the reaction with pure silicon. This is because diffusion of silicon through WSi 2 generated at the interface between silicon and the titanium-tungsten alloy film 14A at the initial stage of heat treatment is difficult, and reaction of titanium and silicon is suppressed by that amount. Here, the composition of titanium in the titanium-tungsten alloy film 14A is 5 to 15 wt%. In addition, the titanium-tungsten alloy film 14A is formed by a sputtering method by supplying power of 5 to 15 kW under a temperature condition of 300 to 600 ° C. and a pressure condition of 5 to 20 mTorr, and has a thickness of 200 to 1000 mW.
도 1b는 질소 분위기에서 급속 열처리(RTN)를 실시하여, 반도체 기판(11)의 접합 영역과 티타늄-텅스텐 합금막(14A)의 계면에 육방정계(hexagonal) 구조의 티타늄/텅스텐 실리사이드막((Ti,W)Si2 ;15)이 형성되고, 티타늄-텅스텐 합금막(14A) 표면에 티타늄과 질소의 반응으로 티타늄 나이트라이드막(14B)이 형성되어 티타늄-텅스텐 합금막(14A)과 티타늄 나이트라이드막(14B)이 적층된 확산 장벽층(14)이 형성된 상태를 나타내는 소자의 단면도이다. 여기에서, 질소 분위기의 급속 열처리는 400 내지 700℃의 온도에서 10 내지 20초 동안 실시한다. 티타늄 나이트라이드막(14B)은 텅스텐을 WF6/SiH4/H2/Ar을 이용한 CVD 방법으로 증착하는 경우 텅스텐막이 떨어지는 것을 방지하는 접착층의 역할을 하게 된다.FIG. 1B shows a titanium / tungsten silicide film having a hexagonal structure at the interface between the junction region of the semiconductor substrate 11 and the titanium-tungsten alloy film 14A by performing rapid heat treatment (RTN) in a nitrogen atmosphere. , W) Si 2 ; 15), and the titanium nitride film 14B is formed on the surface of the titanium-tungsten alloy film 14A by the reaction of titanium and nitrogen to form the titanium-tungsten alloy film 14A and titanium nitride. It is sectional drawing of the element which shows the state in which the diffusion barrier layer 14 in which the film 14B was laminated was formed. Here, the rapid heat treatment of the nitrogen atmosphere is carried out for 10 to 20 seconds at a temperature of 400 to 700 ℃. The titanium nitride film 14B serves as an adhesive layer that prevents the tungsten film from falling when the tungsten is deposited by CVD using WF 6 / SiH 4 / H 2 / Ar.
도 1c에 도시된 바와 같이, 전체구조 상에 비트라인용 텅스텐을 증착하고 패터닝하여 텅스텐 비트라인(16)이 형성된다. 여기에서, 텅스텐은 400 내지 500℃의 온도 조건 및 50 내지 100Torr의 압력 조건에서 700 내지 3000Å의 두께로 형성한다. 텅스텐 비트라인은 이전에 실시한 급속 질화 열처리에 의해 형성된 티타늄 나이트라이드(14B)에 의해 하부층과의 접착력이 강화된 특성을 보인다. 이와 같이 형성된 텅스텐 비트라인은 반도체 기판(11)의 접합 영역과 티타늄-텅스텐 합금막(14A)의 계면에 형성된 육방정계(hexagonal) 구조의 티타늄/텅스텐 실리사이드막((Ti,W)Si2 ;15)이 900℃까지 또다른 상으로의 천이가 일어나지 않고 안정된 상태를 유지하는 특성을 갖기 때문에, 후속 ONO 구조의 캐패시터 형성시 750℃ 이상의 고온에서 열처리를 실시하더라도, 콘택 저항을 증가시키지 않고 빠른 신호처리 능력을 갖도록 한다.As shown in FIG. 1C, tungsten bit lines 16 are formed by depositing and patterning tungsten for bit lines over the entire structure. Here, tungsten is formed to a thickness of 700 to 3000 Pa at a temperature condition of 400 to 500 ° C. and a pressure condition of 50 to 100 Torr. The tungsten bit line exhibits a property in which adhesion with the underlying layer is enhanced by titanium nitride 14B formed by the rapid nitriding heat treatment performed previously. The tungsten bit line formed as described above is a hexagonal titanium / tungsten silicide layer ((Ti, W) Si 2 ; 15) formed at an interface between the junction region of the semiconductor substrate 11 and the titanium-tungsten alloy film 14A. ) Has a characteristic of maintaining a stable state without transition to another phase up to 900 ° C, even if heat treatment is performed at a high temperature of 750 ° C or higher during formation of a capacitor of a subsequent ONO structure, fast signal processing without increasing the contact resistance Have the ability.
상술한 바와 같이 본 발명은 텅스텐 비트라인의 확산 장벽층으로 티타늄-텅스텐 합금층과 같이 비저항이 작은 금속재료를 적용하므로써, 비트라인의 특성을 열화시키지 않고 반도체 메모리 소자의 동작 속도를 개선할 수 있는 효과가 있다. 또한, 트랜지스터의 전하를 비트라인을 통하여 신호 증폭장치로 전달할 때 전하 손실이 적으므로 동일한 캐패시터를 사용하는 경우에도 기존의 텅스텐 실리사이드 배선 재료에 비해 감지 성능을 향상시킬 수 있다.As described above, the present invention can improve the operation speed of a semiconductor memory device without deteriorating the characteristics of the bit line by applying a metal material having a small resistivity, such as a titanium-tungsten alloy layer, as the diffusion barrier layer of the tungsten bit line. It works. In addition, since the charge loss is small when the charge of the transistor is transferred to the signal amplifier through the bit line, the sensing performance can be improved compared to conventional tungsten silicide wiring material even when the same capacitor is used.
도 1a 내지 1c는 본 발명에 따른 반도체 소자의 텅스텐 비트라인 형성 방법을 설명하기 위해 도시한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming a tungsten bit line in a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 층간 절연막11 semiconductor substrate 12 interlayer insulating film
13 : 비트라인 콘택 홀 14A : 티타늄-텅스텐 합금막13 bit line contact hole 14A titanium-tungsten alloy film
14B : 티타늄 나이트라이드막 14 : 확산 장벽층14B: titanium nitride film 14: diffusion barrier layer
15 : 티타늄/텅스텐 실리사이드막 16 ; 텅스텐 비트라인15: titanium / tungsten silicide film 16; Tungsten bitline
Claims (8)
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| KR10-1999-0025451A KR100521052B1 (en) | 1999-06-29 | 1999-06-29 | Method of forming a tungsten bit-line in a semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-1999-0025451A KR100521052B1 (en) | 1999-06-29 | 1999-06-29 | Method of forming a tungsten bit-line in a semiconductor device |
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