JPH11214650A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device, whereby a high m.p. metal wiring can be contacted with respect to fine contact holes with a superior barrier property. SOLUTION: An Si substrate 1, on which an MOS transistor composed of a W gate electrode 22 and diffusion layers 24, 25 and a first layer W wiring 21 are formed, is covered with a layer insulation film 31 and contact holes are formed thereinto. A Ti film 41 is formed, a TiSi2 film 42 is formed through a reaction with Si at the bottoms of the contact holes, and unreacted Ti film is removed. Contact holes for the first layer W wiring 21 are formed, a WN film 51 through sputtering and a W film 52 through the CVD are formed, and a second layer W wiring 53 is embedded and formed. The second layer wiring 53 surface is etched to form an SiN film 61 as a hard mask which covers the second layer wiring 53.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a high melting point metal wiring technique useful for an integrated circuit in which elements are integrated at a high density according to a submicron design rule.

[0002]

2. Description of the Related Art Large-scale integrated circuits (LSI) such as DRAMs
In such a case, a multilayer wiring is usually indispensable, and a wiring material needs to have heat resistance in order to further overlap the wiring on the wiring. Tungsten (W) is often used as a heat-resistant wiring material for such an LSI. While preventing the W wiring from reacting with Si, the shallow source of the MOS transistor
As a wiring technology to contact the drain diffusion layer etc.,
The following methods have been proposed.

An insulating film is deposited on a substrate on which a MOS transistor is formed, a contact hole reaching a diffusion layer is formed in the insulating film, and then a titanium (Ti) film is deposited on the entire surface of the substrate by sputtering. Subsequently, a titanium nitride (TiN) film is deposited by a reactive sputtering method. 550 in this state
Heat treatment at ~ 600 ° C. to form titanium silicide (TiSi ₂ ) on the bottom of the contact hole by the reaction between Ti and silicon
To form After that, a W film is deposited by the CVD method to fill the contact hole.

Further, a technique has been proposed in which a shallow wiring groove is formed after the formation of a contact hole, and a wiring layer is simultaneously buried in the contact hole and the wiring groove. Such wiring technology is used for DRAM
An example of application to the bit line of the 1995 Symposium on
VLSI Technology, Digest of Technical Papers, pp.15
-16. In this example, a DRAM having a trench capacitor is described, and a thermal process after forming a bit line is performed at a relatively low temperature of, for example, 600 ° C. or less.

The TiN film has a role as an adhesive layer at the time of W-CVD and a role as a barrier layer for preventing a reaction between W and Si. The minimum film thickness for the TiN film to play a sufficient role as a barrier layer depends on the subsequent process temperature, and increases as the temperature increases. For example, a Ti film is sputtered to a thickness of 10 nm, a TiN film is sputtered continuously, a silicide film is formed at 600 ° C., and then a W film is deposited to a thickness of 500 nm by CVD.
The heat treatment is performed for 2 hours. Under these conditions,
It has been found that the thickness of the TiN film needs to be 20 nm or more.

For wiring contact to the diffusion layer,
A technique of depositing Ti, reacting it with a diffusion layer to form silicide, and further depositing TiN thereon is also disclosed, for example, in Japanese Patent Application Laid-Open No. 2-119129.

[0007]

However, the above-mentioned Ti
In a wiring technique using a barrier made of an N film, if the design rule becomes sub-quarter micron and the diameter of the contact hole is reduced to sub-quarter micron, it becomes difficult to secure sufficient barrier properties. The first reason is that the TiN film formed by the sputtering method has poor coverage, and therefore, when trying to bury the TiN film in a contact hole having a fine diameter and vertical side walls, the thickness of the TiN film becomes thin at the bottom corner of the contact hole. It is. Secondly, in a high-density LSI using a multilayer wiring structure, if a higher-temperature heat step is performed after forming a wiring contacting the diffusion layer, the barrier property is further degraded in the heat step.

Specifically, for example, as an example in which a high-temperature heating step is required after forming a W wiring connected to a diffusion layer, for example, 1997 Symposium on VSLI Technology, Digest of T
D proposed in echnical Papers, pp.17-18
There is RAM technology. In this DRAM technology, a bit line of a memory cell array is formed of a W film, and a contact hole for a plug (hereinafter, referred to as a poly plug) of a polysilicon film serving as a capacitor node is formed in self-alignment with the bit line. , To form a stacked capacitor structure. In order to form a contact hole in a self-aligned manner with respect to the bit line, a step of forming a silicon nitride film mask on the bit line is required. The silicon nitride film can be formed by a plasma CVD method at a relatively low temperature or a low pressure CVD (LPCVD) method requiring a relatively high temperature. From the viewpoint of coverage, the LPCVD method is desirable. Temperature is required. In the proposed DRAM technology, in the memory cell array region, a poly plug is formed on the diffusion layer, and the W film wiring is brought into contact with the poly plug, but not directly with the diffusion layer. However, if the wiring and the diffusion layer contact are formed of the same W film as the bit line in the peripheral circuit, a barrier process at the contact portion of the W wiring cannot be ensured by a subsequent heat process.

The present invention has been made in view of the above circumstances, and provides a semiconductor device capable of contacting a high melting point metal wiring with excellent barrier properties to a fine contact hole, and a method of manufacturing the same. It is intended to be.

[0010]

A semiconductor device according to the present invention has a silicon substrate, an element including a diffusion layer formed on the silicon substrate, and a flat surface on the substrate on which the element is formed. A first insulating film formed in the first insulating film, a contact hole for the diffusion layer formed in the first insulating film, and a contact hole formed in the first insulating film including the contact hole portion to be shallower than the contact hole. A wiring groove, a refractory metal silicide film formed and buried at the bottom of the contact hole by a reaction with the diffusion layer, and recessed from the surface position of the first insulating film around the contact hole and the wiring groove; A wiring made of a laminated film of a refractory metal nitride film and a polycrystalline silicon film buried in a buried state, and a buried type formed in a recess on the wiring so as to have the same surface position as the first insulating film. And having a second insulating film.

In a first method of manufacturing a semiconductor device according to the present invention, a step of forming an element including a diffusion layer on a silicon substrate; a step of forming an insulating film covering the silicon substrate on which the element is formed; Forming a contact hole for the diffusion layer in the insulating film, forming a first refractory metal film at least in the contact hole, and forming the first refractory metal film and the diffusion layer at the bottom of the contact hole Forming a high-melting-point metal silicide film by reacting with the above, removing the unreacted first high-melting-point metal film, and forming at least the inside of the contact hole by a reactive sputtering method in an atmosphere containing nitrogen. A step of forming a refractory metal nitride film; and a step of forming a second refractory metal film overlying the refractory metal nitride film to form a wiring.

Preferably, in the present invention, after forming a contact hole in the insulating film, the method further comprises the step of forming a wiring groove shallower than the contact hole in a wiring forming region including the contact hole. In the step of forming a wiring with a metal film, the second refractory metal film and the refractory metal nitride film are etched back and buried in the contact holes and the wiring grooves. Preferably, in the present invention, a titanium film is used for the first refractory metal film, a tungsten nitride film is used for the refractory metal nitride film, and a tungsten film is used for the second refractory metal film.

According to a second method of manufacturing a semiconductor device according to the present invention, there is provided an element including a gate electrode formed of a first refractory metal film on a silicon substrate and a diffusion layer serving as a source and a drain self-aligned with the gate electrode. First refractory metal film
Forming a layer wiring, and forming an insulating film covering the silicon substrate on which the element and the first layer wiring are formed;
Forming a contact hole for the diffusion layer in the insulating film, and subsequently forming a wiring groove shallower than the contact hole in a wiring forming region including the region of the contact hole; and an insulating film formed with the contact hole and the wiring groove. Forming a second high-melting-point metal film thereon and performing a heat treatment to form a high-melting-point metal silicide film at the bottom of the contact hole by reaction between the second high-melting-point metal film and the diffusion layer; Removing the second refractory metal film, and forming a refractory metal nitride film on the insulating film having the contact holes and the wiring grooves by a reactive sputtering method in an atmosphere containing nitrogen. Forming a third refractory metal film overlying the refractory metal nitride film, and etching back the third refractory metal film and the refractory metal nitride film to form the contact hole and the wiring. In the groove Forming embedded two-layer wiring, and having a.

According to a third method of manufacturing a semiconductor device according to the present invention, there is provided an element including a gate electrode of a first refractory metal film on a silicon substrate and a diffusion layer serving as a source and a drain self-aligned with the gate electrode. Forming a first layer wiring of a high melting point metal film, forming an insulating film covering the element and the silicon substrate on which the first layer wiring is formed, and forming a first layer on the insulating film with respect to the diffusion layer. Forming a second refractory metal film on the insulating film on which the first contact hole is formed, and performing heat treatment to form the second contact hole at the bottom of the first contact hole. Forming a refractory metal silicide film by reacting the refractory metal film with the diffusion layer; removing the unreacted second refractory metal film; Form 2 contact holes Forming a wiring groove shallower than the contact holes in the wiring region including the first and second contact holes; and forming the first and second wiring grooves by a reactive sputtering method in an atmosphere containing nitrogen. Forming a refractory metal nitride film on an insulating film having a contact hole and a wiring groove, forming a third refractory metal film on the refractory metal nitride film, 3) etching back the high melting point metal film and the high melting point metal nitride film to bury a second layer wiring in the first and second contact holes and the wiring grooves.

In the second and third manufacturing methods, preferably, the first and third refractory metal films are made of a tungsten film, the second refractory metal film is made of a titanium film, and the refractory metal nitride film is used. Uses a tungsten nitride film.

In the present invention, a high melting point metal silicide is formed by reacting with a diffusion layer silicon in a contact hole, and then an unreacted high melting point metal is removed, and then a high melting point metal nitride film serving as a barrier is formed. Is going. If the next barrier layer is formed while the unreacted refractory metal film remains on the side wall of the contact hole, if the contact hole is originally extremely small, the barrier layer will be formed in a state where the diameter is further reduced. Therefore, the coverage becomes worse. According to the present invention, since the diameter of the contact hole at the time of forming the barrier layer can be maintained at the size at the time of processing the contact hole, a decrease in coverage can be suppressed, and as a result, a decrease in barrier property can be suppressed.

Further, according to the present invention, while the high melting point metal silicide film is left at the bottom of the contact hole, a high melting point metal nitride film as a barrier layer and an adhesion layer is formed by reactive sputtering in an atmosphere containing nitrogen. However, in this step, an extremely thin barrier film containing silicon nitride is formed on the surface of the refractory metal silicide film by a reaction between silicide and nitrogen. Therefore, the barrier properties when the high melting point metal nitride and the high melting point metal are buried thereafter are excellent, and even if a further heating step is performed after the wiring is formed, the barrier properties are less deteriorated.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will now be given, with reference to an embodiment in which the present invention is applied to a DRAM, of a manufacturing process focusing on a main portion of a memory cell array and a peripheral circuit region. FIG. 1 (a),
(B) is a cross section of the element region of the memory cell array region in a state where the MOS transistor and the first layer wiring are formed;
FIG. 2 shows a cross section of the peripheral circuit region in the same step as FIG. Prior to element formation, an element isolation insulating film 2 is buried in the silicon substrate 1 by, for example, STI technology, and a p-type well 3a and an n-type well 3b are formed. This substrate 1
In the memory cell array region, a gate electrode 5 of a stacked film of a polysilicon film 5a and a first layer W film 5b is formed in a fixed space / line so as to form a word line, and is self-aligned with the gate electrode 5. Then, n + type source / drain diffusion layers 6 and 7 are formed. A silicon nitride film (SiN) serving as a hard mask is formed on the side walls and the upper portion of the gate electrode 5.
Films 11 and 12 are formed, and plugs (hereinafter, referred to as poly plugs) 8 and 9 made of a polysilicon film contacting the diffusion layers 6 and 7 are formed in stripes running in parallel with the gate electrodes in the gaps between the gate electrodes 5. It is embedded and formed. The poly plug 8 is to be connected to a bit line to be formed later, and the poly plug 9 is to be a capacitor node of a stacked capacitor to be formed later. A silicon oxide film 13 is buried in the isolation region of the poly plug.

At this stage, in the PMOS transistor region of the peripheral circuit, as shown in FIG. 2, the same polysilicon film 5a and first layer W film 5b as those in the memory cell array region are arranged on the gate electrode 22 and the element isolation insulating film 2. A first layer wiring 21 is formed, and p + type source / drain diffusion layers 2 are formed.
4, 25 are formed. Silicon nitride films 11 and 12 are formed on the side walls and upper portions of the gate electrode 22 and the first layer wiring 21 in the same manner as in the memory cell array region, and a silicon oxide film 13 is buried in gaps between the wirings to be flattened. .

Thereafter, as shown in FIGS. 3 and 4 respectively corresponding to FIGS. 1 and 2, a silicon oxide film such as BPSG is deposited as an interlayer insulating film 31 for the second layer wiring. Then, as shown in FIG. 4, a contact hole 3 for p + diffusion layer 25 of the peripheral circuit is formed in interlayer insulating film 31.
Form 2

Subsequently, as shown in FIGS. 5 and 6 corresponding to FIGS. 1 and 2, a Ti film 41 is deposited on the entire surface of the substrate by sputtering. Then, heat treatment is performed at a temperature of 550 to 600 ° C., as shown in FIG.
Reacts the Ti film 41 with silicon at the bottom of the film to form a titanium silicide (TiSi ₂ ) film 42. Thereafter, the unreacted Ti film 41 is removed by etching.

Although FIG. 6 shows a state in which the Ti film 41 remains on the TiSi ₂ film 42, the reaction may be performed until all the Ti films become silicide at the bottom of the contact hole 32.

Next, as shown in FIGS. 7 and 8 corresponding to FIGS. 1 and 2, contact holes for the first-layer polysilicon electrode wiring are formed in the memory cell array region and the peripheral circuit region, respectively. The contact holes 33 in the memory cell array region shown in FIG. 7 are connected to the poly plugs 8 connected to the n + diffusion layers 6 of the memory transistors.
This is for contacting the bit line on the element isolation region. In the peripheral circuit, as shown in FIG.
The contact hole 34 for the layer wiring 21 is shown.

With the contact holes 32 to 34 opened as described above, the interlayer insulating film 31 is further selectively etched to correspond to FIGS. 9 and 10 corresponding to FIGS. 1 and 2, respectively.
As shown in FIG. 7, shallow wiring grooves 43 are formed in the wiring burying regions including the contact holes 32 to 34, respectively.

Subsequently, as shown in FIGS. 11 and 12 respectively corresponding to FIGS. 1 and 2, after forming a SiN film 54 on the side walls of the wiring groove 43 and the contact holes 32 to 34,
As a refractory metal nitride film as a barrier layer and an adhesive layer,
A tungsten nitride (WN) film 51 is deposited by sputtering, and a W film 52 to be a second layer wiring is deposited by CVD. Note that titanium nitride (TiN) can be used as the refractory metal nitride film.
An N film is used. Then, the deposited W film 52 and WN
The laminated film of the film 51 is then etched back and buried in the wiring groove 41 so that the surface becomes flat, and the second layer wiring 5 is formed.
3 is assumed. Second layer wiring 53a in memory cell array region
Becomes a bit line as described above.

In this embodiment, the sputtering process of the WN film 51 uses reactive sputtering in a nitrogen atmosphere.
Thereby, as shown in FIG. 12, an extremely thin silicon nitride (SiN) film 44 is formed on the surface of the TiSi ₂ film 42 at the bottom of the contact hole 32 by the reaction between TiSi ₂ and nitrogen. Acts as a barrier film.

After the second layer wiring 53 is buried flat as described above, the surface of the buried second layer wiring 53 is subsequently etched to a predetermined depth. Then, as shown in FIG. 13 and FIG. 14 corresponding to FIG. 1 and FIG.
The film 61 is deposited at a high temperature of about 780 ° C. by the LPCVD method, and is etched back to form the SiN film 61 on the wiring so as to be at the same surface position as the interlayer insulating film 31.

Subsequently, in the memory cell array region, FIG.
As shown in FIG. 7, a contact hole 62 for exposing the surface of poly plug 9 serving as a capacitor node in a state of being self-aligned with bit line 53a covered with silicon nitride film 61.
To form

Although the subsequent steps are omitted, a connection conductor is buried in the contact hole 62, and a capacitor connected to the connection conductor is laminated to form a memory cell having a stacked capacitor structure.

In this embodiment, as described above, the second
The layer wiring 53 is formed by combining the WN film 51 by reactive sputtering with the CV.
D is formed using a laminated structure of the same kind of material by the W film 52 formed by D. Therefore, thereafter, as described with reference to FIGS. 13 and 14, in the step of etching the second layer wiring 53 for forming the SiN film as the hard mask, there is no difference in the etching rate between the two, and the WN film 51 and the W film 52 are uniformly etched. As the barrier layer, for example, a TiN film may be used instead of the WN film 52.
Since the optimum etching gas is different between the TiN film and
In order to reduce the film as in the case of the film, the etching process becomes difficult. In this sense, this embodiment using the combination of the WN film 51 and the W film 52 is preferable.

In this embodiment, the TiN ₂ film 42 remaining at the bottom of the contact hole 33 is formed by forming the WN film 51 by reactive sputtering in an atmosphere containing nitrogen.
An ultra-thin SiN film 44 is formed on the surface of the substrate, which contributes to the improvement of the barrier property. SiN is an insulating film.
If the thickness is m, a MIM junction through which a tunnel current flows is obtained, and the barrier property can be improved without impairing the ohmic contact characteristics. As a result, even if the SiN forming step by LPCVD at about 780 ° C. is performed as described above after the formation of the second layer wiring 53, the barrier property is kept good and the good diffusion for the shallow diffusion layer 25 is achieved. Ohmic contact can be made.

Further, in this embodiment, a contact hole 32 for the diffusion layer 25 is formed first, and TiSi ₂
After the film is formed, a contact hole 34 for the first layer wiring 21 is opened. If you open these at the same time,
There is a possibility that an unnecessary reaction product may be formed on the surface of the first layer wiring 21 made of the W film. However, in this embodiment, there is no such a possibility.
Contact can be made favorable.

Furthermore, in this embodiment, FIGS. 7 and 8
In this step, the unreacted Ti film is removed by etching. If the contact hole also has a sub-quarter micron fine diameter according to the sub-quarter micron design rule, the decrease in the contact hole diameter due to the Ti film greatly reduces the coverage of the contact hole in the next film forming step. In this embodiment, by removing the unreacted Ti film, good coverage can be maintained for the contact hole having a small diameter.

In the step of removing the unreacted Ti film,
If the contact hole 34 is open, the first layer wiring 21
Must be selectively etched for the W film. If a process like this embodiment is used, for example, a normal metal film removing step using a mixed solution of H ₂ O ₂ + H ₂ SO ₄ can be used for this Ti etching,
Process costs can be kept low.

[0035]

As described above, according to the present invention, a high melting point metal wiring can be buried in a contact hole having a fine diameter with respect to a shallow diffusion layer with excellent barrier properties. High density L
When applied to SI, highly reliable wiring can be obtained even when a high-temperature process is performed after the wiring is formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a memory cell array region in a step of forming a first layer embedded wiring of a DRAM according to an embodiment of the present invention.

FIG. 2 is a sectional view of a peripheral circuit region in the same step.

FIG. 3 is a sectional view of a memory cell array region in a step of forming a contact hole in a diffusion layer according to the same embodiment.

FIG. 4 is a sectional view of a peripheral circuit region in the same step.

FIG. 5 is a sectional view of a memory cell array region in a Ti film forming step of the embodiment.

FIG. 6 is a sectional view of a peripheral circuit region in the same step.

FIG. 7 is a cross-sectional view of a memory cell array region in a step of forming a contact hole for a first-layer wiring according to the same embodiment.

FIG. 8 is a sectional view of a peripheral circuit region in the same step.

FIG. 9 is a cross-sectional view of a memory cell array region in a step of forming a wiring groove of a second layer wiring according to the same embodiment.

FIG. 10 is a sectional view of a peripheral circuit region in the same step.

FIG. 11 is a cross-sectional view of a memory cell array region showing a step of forming a second-layer wiring embedded in the same embodiment.

FIG. 12 is a sectional view of a peripheral circuit region in the same step.

FIG. 13 is a cross-sectional view of the memory cell array area in the step of embedding and forming a SiN film on the second-layer wiring of the embodiment.

FIG. 14 is a sectional view of a peripheral circuit region in the same step.

FIG. 15 is a sectional view of a memory cell array region in a step of forming a contact hole for forming a stacked capacitor structure according to the same embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 21 ... 1st layer wiring, 22 ... Gate electrode, 24, 25 ... P + type diffusion layer, 31 ... Interlayer insulating film, 32, 33, 34 ... Contact hole, 42 ... Ti film, 42 ... TiSi ₂ film, 51 ... WN film, 52 ... W film, 53 ... second layer wire, 61 ... SiN film.

Claims (7)

[Claims] An element including a silicon substrate, a diffusion layer formed on the silicon substrate, a first insulating film formed on the substrate on which the element is formed so as to have a flat surface, A contact hole for the diffusion layer formed in the first insulating film; a wiring groove formed shallower than the contact hole in the first insulating film including the contact hole portion; A refractory metal silicide film formed and buried by a reaction with a layer; and a refractory metal nitride buried in the contact hole and the wiring groove so as to be recessed from a surface position of the first insulating film in the periphery. A wiring made of a laminated film of a film and a polycrystalline silicon film; and a second insulating film buried in a recess on the wiring so as to be at the same surface position as the first insulating film. Special Semiconductor device. A step of forming an element including a diffusion layer on the silicon substrate; a step of forming an insulating film covering the silicon substrate on which the element is formed; and forming a contact hole for the diffusion layer in the insulating film. Forming a first refractory metal film at least in the contact hole; and forming a refractory metal silicide film at the bottom of the contact hole by a reaction between the first refractory metal film and the diffusion layer. Removing the first unreacted first high melting point metal film; forming a high melting point metal nitride film in at least the contact hole by a reactive sputtering method in an atmosphere containing nitrogen. Forming a second refractory metal film on the refractory metal nitride film to form a wiring. 3. A step of forming a contact hole in the insulating film and subsequently forming a wiring groove shallower than the contact hole in a wiring forming region including the contact hole, wherein the wiring is formed by the second refractory metal film. The process of forming
3. The method according to claim 2, wherein the second refractory metal film and the refractory metal nitride film are etched back and embedded in the contact holes and the wiring grooves. 4. The method according to claim 1, wherein the first refractory metal film is a titanium film, the refractory metal nitride film is a tungsten nitride film, and the second refractory metal film is a tungsten film. The method for manufacturing a semiconductor device according to claim 2. 5. An element including a gate electrode made of a first refractory metal film, a self-aligned diffusion layer serving as a source and a drain, and a first layer wiring made of a first refractory metal film on a silicon substrate. Forming; forming an insulating film covering the silicon substrate on which the element and the first layer wiring are formed; forming a contact hole for the diffusion layer in the insulating film, and subsequently including a contact hole region Forming a wiring groove shallower than the contact hole in the wiring formation region; forming a second refractory metal film on the insulating film in which the contact hole and the wiring groove are formed; Forming a high-melting-point metal silicide film by reacting the second high-melting-point metal film with a diffusion layer; removing the unreacted second high-melting-point metal film; Anti Forming a refractory metal nitride film on the insulating film having the contact holes and wiring grooves by reactive sputtering, and forming a third refractory metal film on the refractory metal nitride film. A step of etching back the third refractory metal film and the refractory metal nitride film to bury a second-layer wiring in the contact hole and the wiring groove. Production method. 6. An element including a gate electrode made of a first refractory metal film, a self-aligned diffusion layer serving as a source and a drain, and a first layer wiring made of a first refractory metal film on a silicon substrate. Forming an insulating film covering the silicon substrate on which the element and the first layer wiring are formed; forming a first contact hole for the diffusion layer in the insulating film; Forming a second high-melting point metal film on the insulating film having the contact hole formed therein, performing heat treatment, and forming a second high-melting point metal film at the bottom of the first contact hole by a reaction between the second high-melting point metal film and the diffusion layer; Forming a melting point metal silicide film; removing the unreacted second high melting point metal film; forming a second contact hole for the first layer wiring in the insulating film; 1st and 2nd contacts Forming a wiring groove shallower than these contact holes in a wiring region including the first and second contact holes and the insulating film having the first and second contact holes and the wiring groove by a reactive sputtering method in an atmosphere containing nitrogen. Forming a melting point metal nitride film; forming a third high melting point metal film on the high melting point metal nitride film; and forming the third high melting point metal film and the high melting point metal nitride film. Forming a second layer wiring in the first and second contact holes and the wiring grooves by etching back the semiconductor device. 7. The first and third refractory metal films are tungsten films, the second refractory metal film is a titanium film,
7. The method according to claim 5, wherein the refractory metal nitride film is a tungsten nitride film.