KR20000001960A - Semiconductor device - Google Patents

Abstract

PURPOSE: A semiconductor device equipped with a measuring pattern to detect a horizontal alignment error is provided. CONSTITUTION: A semiconductor device equipped with a detecting pattern to determine a horizontal alignment error comprises; a measuring pattern to measure horizontal alignment error in the photo mask; a pair of 1st detecting pattern symmetrically formed on the Y axis as a standard to detect the X axis alignment error; a pair of 2nd detecting pattern symmetrically formed on X axis as a standard to detect the Y axis alignment error.

Description

Semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a measurement pattern for checking horizontal alignment errors that may occur in an exposure process during a semiconductor device manufacturing process.

In general, in the exposure step, which is one of the semiconductor device manufacturing processes, a photosensitive material is coated on a wafer and light is irradiated through a mask on which a predetermined pattern is formed to transfer the pattern to the photosensitive film. In such an exposure process, since a precise pattern of very small line width must be formed, alignment of the mask and the wafer coated with the photosensitive film is very important.

The alignment of the wafer and the mask should be considered separately from the vertical alignment and the horizontal alignment, which will be described with reference to FIG. 1. 1 conceptually illustrates an exposure system in which the vertical alignment is accurate but there is an error in the horizontal alignment. As shown in FIG. 1, the vertical alignment refers to the alignment of the wafer 14, the mask 12, and the light source 10 according to the light traveling direction, and the horizontal alignment refers to the light source (in the vertical direction and the light traveling direction). 10) The mask 12 and the wafer 14 are said to maintain a constant angle. In the example shown in FIG. 1, the light source 10 and the mask 12 are maintained perpendicular to the direction of light travel. However, it can be seen that the wafer 14 deviates by θ from a reference plane perpendicular to the direction of light travel. .

In this case, the paths of light passing from the light source to the wafer are not the same at the "ga" and "b" parts, respectively, so that the focus of the light passing through the mask 12 over the entire surface of the wafer 14 is increased. This is not formed constantly. Therefore, when the exposure process is performed in a state in which the horizontal alignment is not exactly performed as described above, a desired pattern cannot be accurately formed on the photoresist film (not shown) applied on the wafer 10, and eventually, the semiconductor This can cause a defect in the device itself.

Conventionally, in order to check the error of the horizontal alignment as described above, a method of measuring the line width of the pattern formed on the surface using a line width measuring device such as a scanning electron microscope (SEM: Scanning Electron Microscope) was used.

However, this method has a disadvantage in that the measurement results change depending on the measurement position, so that the degree of alignment error cannot be determined consistently. In addition, it takes too much time in the process of measuring the line width by using the line width measuring device adversely affects the overall productivity.

The present invention devised to solve the above problems is to provide a semiconductor device having a horizontal alignment measurement pattern so that the horizontal alignment error can be determined consistently, and a method for checking the horizontal alignment error using the same.

1 is a conceptual diagram of an exposure system for an exposure process during a semiconductor device manufacturing process;

2 illustrates an embodiment of a photomask according to the present invention.

3 illustrates a wafer in which a pattern is formed using the photomask of FIG. 2.

4 shows a check pattern between the die and the die formed on the wafer of FIG.

5 shows a check pattern formed on a wafer using a photomask of another embodiment of the present invention.

* Explanation of the symbols of the main parts of the drawings

10: light source 12: mask

14 wafer 200 reticle

210: field area 220: scribe line area

222: check pattern

In order to achieve the above object, the present invention has a measurement pattern for measuring the horizontal alignment error between the wafer and the photomask for transferring the pattern on the wafer, the measurement pattern is referenced to the Y axis to check the X-axis alignment error At least one first check pattern pair symmetrically and at least one second check pattern pair symmetrical with respect to the X axis to check the Y-axis alignment error. Preferably, one inspection pattern and the other inspection pattern constituting the first inspection pattern pair are formed in different fields during the exposure process, and the inspection pattern and the other inspection pattern constituting the second inspection pattern pair are different from the exposure process. City is formed in different fields. In addition, the measurement pattern includes a plurality of pairs of the first and second check patterns each formed for each layer where horizontal alignment is critical as the manufacturing process proceeds, and the measurement pattern is formed in the scribe area of the wafer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 2 is a view showing an embodiment of a photomask according to the present invention. For convenience of explanation and understanding, a reticle 200 having a ratio of 5 to 1 or 4 to 1 used in a reduced exposure system will be described here as an example.

As shown, the reticle 200 according to the present invention can cut the field region 210 for forming a predetermined pattern in the center portion, and the die formed on the wafer after completing the manufacturing process. In order to form a scribe line so as to include a scribe line region 220 formed on the outer surface of the field region. In addition, a check pattern 222 for checking the horizontal alignment error is further included in the corner portion of the scribe line region 220.

In order to transfer the pattern onto the entire wafer, the pattern is repeatedly transferred a predetermined number of times while moving the reticle 200 by a predetermined distance in consideration of the size of the wafer and the reticle 200. 3 illustrates a wafer 300 in which a pattern is formed by such repeated movement and transfer. As shown, a plurality of dies 310 are formed on the wafer 300, and a scribe line is formed between the plurality of dies 310a and the dies 310b to provide a free space for cutting.

As described above, the present invention is to check the horizontal alignment error of the exposure system by forming the check pattern 222 as described above in a predetermined portion of the reticle 200 corresponding to the region where the scribe line is to be formed. The present invention will be described in more detail with reference to FIG. 4, which is an enlarged view of the "multi" portion of FIG. 3 (hereinafter, a check pattern 222 on the reticle 200 and a check pattern on the wafer 300). Although 322 is physically different from each other, there is no fear of confusion among a person of ordinary skill in the art, and the term "check pattern" will be used for both for convenience of understanding and explanation. )

FIG. 4 is a view illustrating inspection patterns 422a to 422h formed between the die 310a and the die 310b on the wafer 300 after the manufacturing process is performed using the reticle 200 of FIG. 2. to be. As shown, eight check patterns 422 are formed at a predetermined point on the wafer 300, and the x-axis on the wafer 300 with the eight check patterns 422 according to the following principle. Both directional horizontal alignment errors and y-axis horizontal alignment errors can be measured.

That is, by measuring the sizes of the first check pattern pairs 422a and 422b, the y-axis alignment error on the right side of the field area can be measured, and by measuring the sizes of the second check pattern pairs 422c and 422d, the left side of the field area. You can measure the alignment error in the y-axis. That is, if the wafer 300 is inclined in the y-axis direction, the sizes of the check pattern 422a and the check pattern 422b will be different from each other, so if the wafer 300 is measured, the y-axis direction of the wafer 300 is measured. Notice that there was an error in the horizontal alignment.

Also, by measuring the size of the third check pattern 422e and 422f pairs, the x-axis alignment error at the top of the field region can be measured by the same principle, and the size of the fourth check pattern 422g and 422h pairs is measured. As a result, the x-axis alignment error under the field region can be measured.

The pair of check patterns as described above can be easily captured at any position on the wafer 300, thereby eliminating the inconvenience of moving the measuring device back and forth to check for horizontal alignment errors, and when an alignment error is detected. The degree of error can be accurately measured by the difference in the size of the check pattern.

In addition, two check patterns 222 as shown in FIG. 2 need not be formed at four corners of the reticle 200. That is, of the four pairs of check patterns shown in FIG. 4, only the first check pattern pairs 422a and 422b and the third check pattern pairs 422e and 422f are formed to form the x-axis direction and the y-axis direction. You can check for any horizontal alignment errors.

Referring now to FIG. 5, a method by which the alignment error of each layer can be measured collectively after the multilayer process has proceeded will be described. FIG. 5 is a diagram illustrating an inspection pattern 522 formed on the wafer 300 after performing a manufacturing process by forming a check pattern for each layer on a reticle of a layer where horizontal alignment is critical as the manufacturing process proceeds. to be. In the illustrated example, the reticle used for the device isolation layer ISO, the first polysilicon layer P1, the first contact forming layer P2C, the second polysilicon layer P2 and the second contact forming layer P3C is used. Each of the inspection patterns was formed, and the manufacturing process was performed after exposure.

Since the complex check pattern 522 may be formed on the wafer 300 as shown in FIG. 4, the horizontal alignment error in each layer may be easily checked, and the horizontal alignment error check may be performed. The time required for this can be significantly shortened.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, it is possible to eliminate the inconvenience of moving the measuring device around to check the horizontal alignment error, and when the alignment error is detected, the accuracy of the error is accurately measured by the difference in the size of the check pattern. can do. In addition, according to the present invention, it is possible to collectively measure the misalignment of each layer after the multi-layer process has progressed, thereby significantly reducing the time required for the horizontal misalignment check.

Claims (4)

A measurement pattern for measuring a horizontal alignment error between a wafer and a photomask for transferring a pattern to the wafer, The measurement pattern includes at least one first check pattern pair symmetrical about the Y axis to check for an X-axis alignment error, and at least one second check symmetrical about the X-axis to check the Y-axis alignment error. A semiconductor device comprising a pattern pair. The method of claim 1, One inspection pattern and the other inspection pattern constituting the first inspection pattern pair are formed in different fields during the exposure process, and one inspection pattern and the other inspection pattern constituting the second inspection pattern pair are mutually different during the exposure process. A semiconductor device formed in another field. The method according to claim 1 or 2, And the measuring pattern includes a plurality of first and second check pattern pairs each formed for each layer in which horizontal alignment is critical as the manufacturing process proceeds. The method of claim 3, And the measuring pattern is formed in a scribe area of the wafer.