KR20000001883A - Contact hole forming method of semiconductor device - Google Patents
Contact hole forming method of semiconductor device Download PDFInfo
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- KR20000001883A KR20000001883A KR1019980022359A KR19980022359A KR20000001883A KR 20000001883 A KR20000001883 A KR 20000001883A KR 1019980022359 A KR1019980022359 A KR 1019980022359A KR 19980022359 A KR19980022359 A KR 19980022359A KR 20000001883 A KR20000001883 A KR 20000001883A
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
Description
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 후속되는 베리어층의 매립성을 향상시키고 저항을 감소시킬 수 있는 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a contact hole capable of improving embedding of a barrier layer and reducing resistance.
반도체기판과 도전층을 접속시키기 위한 콘택홀이나, 도전층과 도전층을 연결하기 위한 비아홀은, 반도체기판이나 도전층 상에 형성된 층간절연층을 부분적으로 식각함으로써 반도체기판이나 도전층의 표면 일부를 노출시키는 것에 의해 형성된다.The contact hole for connecting the semiconductor substrate and the conductive layer or the via hole for connecting the conductive layer and the conductive layer partially removes the surface of the semiconductor substrate or the conductive layer by partially etching the interlayer insulating layer formed on the semiconductor substrate or the conductive layer. Formed by exposing.
전자기기의 고속화, 고기능화 및 소형화를 위해서 반도체 장치의 집적도가 증가함에 따라, 콘택홀 또는 비아홀(이하 콘택홀)의 크기도 감소하게 되었다. 일반적으로 콘택홀은, 후속공정 진행시 공정의 마진을 부여하며, 특히 미세콘택홀은 하부 도전층의 공정마진을 증가시키게 된다. 그러나, 미세콘택홀은 하부물질과의 접촉면적이 줄어들므로 콘택저항을 증가시키는 원인이 된다. 콘택저항은 CPU, MDL(Merged DRAM Logic) 등의 반도체 로직 제품에 있어서는 그 스피드와 제품의 신뢰성에 직접적인 영향을 미친다.As the degree of integration of semiconductor devices increases for high speed, high functionality, and miniaturization of electronic devices, the size of contact holes or via holes (hereinafter referred to as contact holes) is also reduced. In general, the contact hole provides a process margin during the subsequent process, and in particular, the micro contact hole increases the process margin of the lower conductive layer. However, the micro contact hole is the cause of increasing the contact resistance because the contact area with the underlying material is reduced. Contact resistance directly affects the speed and reliability of a semiconductor logic product such as a CPU or MDL (Merged DRAM Logic).
콘택저항을 감소시키기 위해 종래 제시된 공정들은 금속과 금속을 연결하는 콘택을 얼마나 매끄럽게 개구하느냐에 중점을 두었다. 그러나, 콘택홀의 사이즈가 작아지면서, 콘택홀이 개구되지 않는 오픈 불량이 발생되거나, 플러그 도전층과 같은 물질로 콘택홀 매립하는 것이 어려워지게 되었다.In order to reduce the contact resistance, conventionally proposed processes have focused on how smoothly opening the metal-to-metal contact. However, as the size of the contact hole decreases, open defects in which the contact hole does not open occurs, or it becomes difficult to fill the contact hole with a material such as a plug conductive layer.
도 1 및 도 2는 종래 기술에 따른 콘택홀 형성방법을 설명하기 위해 도시한 단면도들이다.1 and 2 are cross-sectional views illustrating a method for forming a contact hole according to the prior art.
도 1을 참조하면, 반도체 기판(1) 상에 형성된 금속층(3) 위에 캐핑층으로서 티타늄질화막(5)을 형성하고, 그 위에 절연막(7)을 형성한다. 상기 절연막(7) 상에 포토레지스트 패턴(도시되지 않음)을 형성하고 이를 식각마스크로 사용하여 상기 절연막(7)과 티타늄질화막(5)을 건식식각함으로써 콘택홀(a)을 형성한다.Referring to FIG. 1, a titanium nitride film 5 is formed as a capping layer on a metal layer 3 formed on a semiconductor substrate 1, and an insulating film 7 is formed thereon. A photoresist pattern (not shown) is formed on the insulating film 7 and the contact hole a is formed by dry etching the insulating film 7 and the titanium nitride film 5 using the photoresist pattern as an etching mask.
도 2를 참조하면, 상기 콘택홀 내에 티타늄막/티타늄질화막을 증착하여 베리어층(8)을 형성하고, 텅스텐을 증착하여 플러그층(9)을 형성한다. 상기 베리어층(8)은 스퍼터링 방법으로 진행한다.Referring to FIG. 2, a barrier layer 8 is formed by depositing a titanium film / titanium nitride film in the contact hole, and a plug layer 9 is formed by depositing tungsten. The barrier layer 8 proceeds by a sputtering method.
콘택의 CD(Critical Dimension)가 작아지면서 도 1에 도시된 바와 같은 콘택 프로파일은 얻기가 매우 힘들다. 콘택홀이 미세화됨에 따라, 콘택홀의 바닥면과 접촉되는 금속층(3)의 면적은 좁아지게 되고, 이에 따라 콘택저항이 증가된다. 심할 경우, 콘택이 오픈되지 않는 불량이 발생될 수도 있다. 또한, 개구되었다 할지라도 후속 공정인 베리어층 및 플러그층 증착공정 후 평탄화공정으로서 CMP 공정이 진행되면서 텅스텐 플러그층이 떨어져 나가는 현상이 발생된다.As the CD (Critical Dimension) of the contact becomes smaller, the contact profile as shown in FIG. 1 is very difficult to obtain. As the contact hole becomes smaller, the area of the metal layer 3 in contact with the bottom surface of the contact hole becomes narrower, thereby increasing the contact resistance. In severe cases, a failure may occur in which the contact is not opened. In addition, even if it is opened, the tungsten plug layer may fall off as the CMP process proceeds as a planarization process after the barrier layer and plug layer deposition processes, which are subsequent processes.
본 발명이 이루고자 하는 기술적 과제는, 베리어층의 매립성을 향상시키고, 콘택저항을 감소시킬 수 있는 반도체소자의 콘택홀 형성방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for forming a contact hole in a semiconductor device capable of improving embedding of a barrier layer and reducing contact resistance.
도 1 및 도 2는 종래 기술에 따른 콘택홀 형성방법을 설명하기 위해 도시한 단면도들이다.1 and 2 are cross-sectional views illustrating a method for forming a contact hole according to the prior art.
도 3 내지 도 6은 본 발명의 제1 실시예에 따른 콘택홀 형성방법을 설명하기 위해 도시한 단면도들이다.3 to 6 are cross-sectional views illustrating a method for forming a contact hole according to a first embodiment of the present invention.
도 7 및 도 8은 본 발명의 제2 실시예에 따른 콘택홀 형성방법을 설명하기 위해 도시한 단면도들이다.7 and 8 are cross-sectional views illustrating a method for forming a contact hole according to a second embodiment of the present invention.
상기 과제를 이루기 위한 본 발명에 따른 콘택홀 형성방법은, 반도체 기판 상에 금속층 및 캐핑층을 적층하여 형성하고, 상기 캐핑층 상에 절연막을 형성한 다음, 상기 절연막 및 캐핑층을 패터닝하여 콘택홀을 형성한다. 계속해서, 상기 콘택홀 내벽에 형성된 캐핑층을 선택적으로 일정량 습식식각하여 콘택홀의 바닥면적을 증가시키고, 상기 콘택홀 내부에 베리어층을 형성한 후, 상기 베리어층 상에 텅스텐 플러그층을 형성한다.The contact hole forming method according to the present invention for achieving the above object is formed by stacking a metal layer and a capping layer on a semiconductor substrate, forming an insulating film on the capping layer, and then patterning the insulating film and the capping layer to form a contact hole To form. Subsequently, the capping layer formed on the inner wall of the contact hole is selectively wet-etched to increase the bottom area of the contact hole, and a barrier layer is formed in the contact hole, and then a tungsten plug layer is formed on the barrier layer.
베리어층을 형성하기 전, RF 플라즈마를 이용하여 콘택홀의 상단과 하단에 위치한 절연막의 모서리부분을 식각할 수 있다.Before forming the barrier layer, the edges of the insulating layers positioned at the top and bottom of the contact hole may be etched using RF plasma.
또한, 베리어층을 형성하기 전, 콘택홀 바닥부에 형성된 금속층을 소정깊이 습식식각할 수 있다.In addition, before forming the barrier layer, the metal layer formed on the bottom of the contact hole may be wet-etched to a predetermined depth.
상술한 바와 같이 본 발명에 따르면, 콘택홀 내벽의 바닥부에 형성된 캐핑층을 일정량 습식식각하여 콘택홀의 바닥면적을 넓힘으로써 금속층과 베리어층의 접촉면적을 증가시켜 콘택저항을 감소시킬 뿐만 아니라, 후속공정시 텅스텐 플러그층이 떨어져 나가는 것을 방지할 수 있다.As described above, according to the present invention, the capping layer formed on the bottom portion of the inner wall of the contact hole is wet-etched in a predetermined amount to increase the bottom area of the contact hole, thereby increasing the contact area between the metal layer and the barrier layer, thereby reducing the contact resistance. It is possible to prevent the tungsten plug layer from falling off during the process.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3 내지 도 6은 본 발명의 제1 실시예에 따른 콘택홀 형성방법을 설명하기 위해 도시한 단면도들이다.3 to 6 are cross-sectional views illustrating a method for forming a contact hole according to a first embodiment of the present invention.
도 3을 참조하면, 하부구조물(도시되지 않음)이 형성된 반도체 기판(10) 상에 금속층(12)을 형성하고, 상기 금속층(12) 위에 캐핑층으로서 티타늄막(14)과 티타늄질화막(16)을 적층한다. 계속해서, 상기 티타늄질화막(16) 상에 절연물, 예컨대PE-OX 또는 P-TEOS 등을 증착하여 절연막(18)을 형성한다. 상기 절연막(18) 상에 포토레지스트 패턴(도시되지 않음)을 형성하고 이를 식각마스크로 사용하여 상기 절연막(18)과 티타늄질화막(16) 및 티타늄막(14)을 건식식각함으로써 콘택홀(h)을 형성한다.Referring to FIG. 3, a metal layer 12 is formed on a semiconductor substrate 10 on which a substructure (not shown) is formed, and a titanium film 14 and a titanium nitride film 16 are formed as capping layers on the metal layer 12. Laminated. Subsequently, an insulator such as PE-OX or P-TEOS is deposited on the titanium nitride film 16 to form an insulating film 18. By forming a photoresist pattern (not shown) on the insulating film 18 and using it as an etching mask, the insulating film 18, the titanium nitride film 16 and the titanium film 14 are dry etched to form a contact hole (h). To form.
도 4를 참조하면, 티타늄과 티타늄질화물을 선택적으로 습식식각할 수 있는 에쳔트를 사용하여, 상기 콘택홀(h) 내벽의 티타늄(14)과 티타늄질화막(16) 일부를 습식식각함으로써, 콘택홀(h)의 바닥면의 면적을 증가시킨다.Referring to Figure 4, by using an etchant capable of selectively wet etching titanium and titanium nitride, by wet etching a portion of the titanium 14 and the titanium nitride film 16 of the inner wall of the contact hole (h), (h) increase the area of the bottom surface;
계속해서 도 5에 도시된 바와 같이, RF 플라즈마를 이용하여 콘택홀(h)의 상단과 하단에 위치한 절연막(18)의 모서리부분을 식각해낸다.Subsequently, as shown in FIG. 5, edge portions of the insulating layer 18 positioned at the top and bottom of the contact hole h are etched using RF plasma.
도 6을 참조하면, 상기 콘택홀 내부에 베리어층으로서 티타늄막(20)과 티타늄질화막(22)을 형성하고, 그 위에 텅스텐을 증착하여 플러그층(24)을 형성한다. 이후, 도시되지는 않았지만, 통상의 공정 예를 들면, 상기 텅스텐 플러그층(24)에 대한 CMP 공정을 진행하고, 그 위에 금속층을 증착하는 공정을 진행한다.Referring to FIG. 6, a titanium layer 20 and a titanium nitride layer 22 are formed as barrier layers in the contact hole, and tungsten is deposited thereon to form a plug layer 24. Thereafter, although not shown, a conventional process, for example, a CMP process for the tungsten plug layer 24 is performed, and a metal layer is deposited thereon.
상기 본 발명의 제1 실시예에 따르면, 콘택홀 내벽의 바닥부에 형성된 캐핑층(14,16)을 일정량 습식식각하여 콘택홀의 바닥면적을 넓힘으로써 금속층(12)과 베리어층(20,22)의 접촉면적을 증가시켜 콘택저항을 감소시킬 뿐만 아니라, 후속공정시 텅스텐 플러그층(24)이 떨어져 나가는 것을 방지할 수 있다.According to the first embodiment of the present invention, the metal layer 12 and the barrier layers 20 and 22 are formed by wet etching the capping layers 14 and 16 formed in the bottom portion of the inner wall of the contact hole to increase the bottom area of the contact hole. In addition to reducing the contact resistance by increasing the contact area, the tungsten plug layer 24 can be prevented from falling off in a subsequent process.
도 7 및 도 8은 본 발명의 제2 실시예에 따른 콘택홀 형성방법을 설명하기 위해 도시한 단면도들이다. 본 발명의 제2 실시예는 콘택홀 하부에 형성된 금속층(12)을 소정깊이 식각하는 것을 제외하고는 상기 제1 실시예와 동일하다.7 and 8 are cross-sectional views illustrating a method for forming a contact hole according to a second embodiment of the present invention. The second embodiment of the present invention is the same as the first embodiment except that the metal layer 12 formed under the contact hole is etched to a predetermined depth.
도 7을 참조하면, 콘택홀(h) 내벽의 티타늄(14)과 티타늄질화막(16) 일부를 습식식각하는 공정까지 상기 제1 실시예와 동일하게 진행한다. 계속해서, 상기 콘택홀(h)의 바닥부에 형성되어 있는 상기 금속층(12)을 소정깊이 습식식각하여 콘택홀의 바닥면적을 넓힌다. 다음, RF 플라즈마를 이용하여 콘택홀(h)의 상단과 하단에 위치한 절연막(18)의 모서리부분을 식각해낸다.Referring to FIG. 7, the process of wet etching a portion of the titanium 14 and the titanium nitride layer 16 of the inner wall of the contact hole h may be performed in the same manner as in the first embodiment. Subsequently, the metal layer 12 formed on the bottom of the contact hole h is wet-etched to a predetermined depth to increase the bottom area of the contact hole. Next, the edges of the insulating film 18 positioned at the top and bottom of the contact hole h are etched using the RF plasma.
도 8을 참조하면, 상기 콘택홀 내부에 베리어층으로서 티타늄막(20)과 티타늄질화막(22)을 형성하고, 그 위에 텅스텐을 증착하여 플러그층(24)을 형성한다. 이후 도시되지는 않았지만, 상기 제1 실시예에서와 마찬가지로, 통상의 공정 예를 들면, 상기 텅스텐 플러그층(24)에 대한 CMP 공정을 진행하고, 그 위에 금속층을 증착하는 공정을 진행한다.Referring to FIG. 8, a titanium layer 20 and a titanium nitride layer 22 are formed as barrier layers in the contact hole, and tungsten is deposited thereon to form a plug layer 24. Although not shown thereafter, as in the first embodiment, a conventional process, for example, a CMP process for the tungsten plug layer 24 is performed, and a metal layer is deposited thereon.
상기 본 발명의 제2 실시예에 따르면, 콘택홀 바닥부에 형성된 금속층을 소정깊이 습식식각함으로써, 콘택홀의 바닥면적이 상기 제1 실시예보다 더 넓어지고, 따라서 금속층(12)과 베리어층(20,22)의 접촉면적이 더욱 증가된다.According to the second embodiment of the present invention, by wet etching the metal layer formed on the bottom of the contact hole to a predetermined depth, the bottom area of the contact hole is wider than the first embodiment, and thus the metal layer 12 and the barrier layer 20 22, the contact area is further increased.
상술한 바와 같이 본 발명에 따르면, 콘택홀 내벽의 바닥부에 형성된 캐핑층을 일정량 습식식각하여 콘택홀의 바닥면적을 넓힘으로써 금속층과 베리어층의 접촉면적을 증가시켜 콘택저항을 감소시킬 뿐만 아니라, 후속공정시 텅스텐 플러그층이 떨어져 나가는 것을 방지하여 베리어층의 매립성을 향상시킬 수 있다.As described above, according to the present invention, the capping layer formed on the bottom portion of the inner wall of the contact hole is wet-etched in a predetermined amount to increase the bottom area of the contact hole, thereby increasing the contact area between the metal layer and the barrier layer, thereby reducing the contact resistance. The tungsten plug layer may be prevented from falling off during the process, thereby improving embedding of the barrier layer.
Claims (3)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980022359A KR20000001883A (en) | 1998-06-15 | 1998-06-15 | Contact hole forming method of semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980022359A KR20000001883A (en) | 1998-06-15 | 1998-06-15 | Contact hole forming method of semiconductor device |
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| Publication Number | Publication Date |
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| KR20000001883A true KR20000001883A (en) | 2000-01-15 |
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| KR1019980022359A KR20000001883A (en) | 1998-06-15 | 1998-06-15 | Contact hole forming method of semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100383756B1 (en) * | 2000-12-28 | 2003-05-14 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
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1998
- 1998-06-15 KR KR1019980022359A patent/KR20000001883A/en not_active Application Discontinuation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100383756B1 (en) * | 2000-12-28 | 2003-05-14 | 주식회사 하이닉스반도체 | Method of forming a metal wiring in a semiconductor device |
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