KR20000001036A - Multilayer interconnection forming method using chemical mechanical polishing - Google Patents
Multilayer interconnection forming method using chemical mechanical polishing Download PDFInfo
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- KR20000001036A KR20000001036A KR1019980021060A KR19980021060A KR20000001036A KR 20000001036 A KR20000001036 A KR 20000001036A KR 1019980021060 A KR1019980021060 A KR 1019980021060A KR 19980021060 A KR19980021060 A KR 19980021060A KR 20000001036 A KR20000001036 A KR 20000001036A
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- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000005498 polishing Methods 0.000 title abstract description 4
- 239000000126 substance Substances 0.000 title abstract description 3
- 239000010410 layer Substances 0.000 claims abstract description 74
- 239000011229 interlayer Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000002184 metal Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000000151 deposition Methods 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 4
- 238000007517 polishing process Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 239000003870 refractory metal Substances 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims 1
- 238000000206 photolithography Methods 0.000 description 4
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- -1 silicon oxy nitride Chemical class 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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Abstract
Description
본 발명은 반도체 소자 제조방법에 관한 것으로, 특히 화학-기계적 폴리싱 공정을 이용한 다층 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a multilayer wiring using a chemical-mechanical polishing process.
반도체소자가 고집적화됨에 따라 사진공정의 마진을 확보하고 배선길이를 최소화하기 위해 하부구조물을 평탄화시키는 기술이 요구된다. 하부구조물을 평탄화시키기 위한 방법으로는, BPSG(borophosphosilicate glass) 리플로우(reflow), 스핀온글라스(spin on glass; SOG) 에치백(etch back), 및 화학기계폴리싱(chemical mechanical polishing; 이하 "CMP"라 한다) 방법 등이 있다. 이 중에서, CMP 방법은 슬러리(slurry)와 패드의 마찰력을 이용하여 글로벌(global) 평탄화를 달성하는 방법으로서, 리플로우 공정이나 에치백 공정으로 달성할 수 없는 넓은 공간영역의 글로벌 평탄화 및 저온 평탄화 공정을 달성할 수 있어 차세대 소자에서 유력한 평탄화 기술로 대두되고 있다.As semiconductor devices have been highly integrated, a technology for planarizing a lower structure is required to secure a margin of a photographic process and minimize wiring length. Methods for planarizing the substructure include borophosphosilicate glass reflow, spin on glass (SOG) etch back, and chemical mechanical polishing ("CMP"). "") And the like. Among these, the CMP method is a method of achieving global planarization by using friction between slurry and pad, and is a global planarization and low temperature planarization process in a large space that cannot be achieved by a reflow process or an etch back process. Achievement is emerging as a prominent planarization technology in next-generation devices.
이러한 CMP 공정은 하부 구조물의 평탄화를 위한 공정 뿐만 아니라, 배선 형성공정에서도 활용되고 있다. 예를 들면, 절연막을 식각하여 콘택홀이나 비아(via)홀과 같은 개구부를 형성하고 개구부를 도전물로 매립한 후, 절연막 상의 과도한 도전층을 CMP 방법으로 제거함으로써 개구부를 도전물질로 채운다. 이러한 방법에 의해 형성되는 배선으로서 다마신(Damascene) 배선이나, 콘택 플러그(Plug)를 들 수 있다. 이처럼 CMP 공정을 배선 형성에 적용할 경우, 콘택홀이나 비아홀의 어스펙트 비(aspect ratio)의 증가로 인한 단차 도포성 불량으로 야기되는 문제점을 방지할 수 있다.The CMP process is used not only for the planarization of the lower structure but also in the wiring forming process. For example, the insulating film is etched to form openings such as contact holes or via holes, and the openings are filled with a conductive material, and then the openings are filled with the conductive material by removing the excess conductive layer on the insulating film by the CMP method. Examples of the wirings formed by such a method include damascene wiring and contact plugs. In this case, when the CMP process is applied to the wiring line, it is possible to prevent a problem caused by a poor coating property due to an increase in the aspect ratio of the contact hole or the via hole.
소자가 고집적화되어 다층배선이 요구됨에 따라, 제1 배선층으로 제공되는 다마신 배선과, 제2 배선층과 접속되는 콘택 플러그가 하나의 소자 내에 형성된다. 그러나, 종래의 일반적인 제조공정에 따르면, 다마신 배선과 콘택 플러그가 서로 다른 2회의 사진식각공정을 통해 형성되므로, 다마신 배선과 콘택 플러그 간에 미스얼라인(misalign)이 발생될 경우에는, 다마신 배선과 이웃한 콘택 플러그의 단락(short)이 발생될 우려가 있다.As the device is highly integrated and multi-layer wiring is required, damascene wiring provided as the first wiring layer and contact plugs connected with the second wiring layer are formed in one device. However, according to the conventional general manufacturing process, since the damascene wiring and the contact plug are formed through two different photolithography processes, when misalignment occurs between the damascene wiring and the contact plug, damascene There is a fear that a short circuit between the wiring and the adjacent contact plug may occur.
본 발명이 이루고자 하는 기술적 과제는 다마신 배선과 콘택 플러그의 단락을 방지할 수 있는 다층배선 형성방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method for forming a multilayer wiring that can prevent a short circuit between the damascene wiring and the contact plug.
도 1 내지 도 4는 본 발명의 바람직한 실시예에 따른 다층배선 형성방법을 설명하기 위해 도시한 단면도들이다.1 to 4 are cross-sectional views illustrating a method for forming a multilayer wiring according to a preferred embodiment of the present invention.
상기 과제를 달성하기 위한 본 발명에 따른 다층배선 형성방법은, 반도체 기판 상에 평탄화층을 형성하고, 평탄화층 상에 콘택 플러그가 형성될 영역의 상기 평탄화층을 노출시키는 식각저지층을 형성한 후, 제1 층간절연막을 형성한다. 계속해서, 제1 층간절연막과 평탄화층을 선택적으로 제거함으로써, 다마신 배선이 형성될 상기 식각저지층과 콘택 플러그가 형성될 상기 기판 표면을 노출시키는 개구부들을 형성하고, 개구부들이 형성된 결과물 전면에 상기 개구부를 완전히 매립할 수 있을 정도의 두께로 금속층을 형성한 다음, 상기 금속층에 대한 화학-기계적 연마공정을 수행하여 상기 제1 층간절연막 상부에 형성된 금속층을 제거함으로써, 개구부를 매립하는 다마신 배선과 콘택 플러그를 형성한다. 이후, 다마신 배선과 콘택 플러그가 형성된 결과물 전면에 제2 층간절연막을 형성하고, 상기 제2 층간절연막을 선택적으로 제거하여 상기 콘택 플러그 일부를 노출시키는 비아홀을 형성한 다음, 비아홀이 형성된 결과물 상에 상기 콘택 플러그와 접속되는 금속 배선을 형성한다.According to the present invention, a method for forming a multilayer wiring according to the present invention includes forming a planarization layer on a semiconductor substrate, and forming an etch stop layer exposing the planarization layer in a region where a contact plug is to be formed on the planarization layer. A first interlayer insulating film is formed. Subsequently, by selectively removing the first interlayer insulating film and the planarization layer, openings are formed to expose the surface of the substrate on which the etch stop layer and the contact plug on which damascene wiring is to be formed are formed, and the openings are formed on the entire surface of the resultant. Forming a metal layer with a thickness sufficient to completely fill the opening, and then performing a chemical-mechanical polishing process on the metal layer to remove the metal layer formed on the first interlayer insulating film, thereby filling the opening with the damascene wiring; Form a contact plug. Subsequently, a second interlayer insulating film is formed on the entire surface of the resultant product in which the damascene wire and the contact plug are formed, and the second interlayer insulating film is selectively removed to form a via hole exposing a part of the contact plug. A metal wiring connected to the contact plug is formed.
상기한 바와 같이, 본 발명에 따르면 동일한 사진식각공정을 통해 다마신 배선과 콘택 플러그가 형성되므로, 다마신 배선과 콘택 플러그 간에 미스얼라인으로 인한 단락 발생 가능성이 없다.As described above, according to the present invention, since the damascene wiring and the contact plug are formed through the same photolithography process, there is no possibility of a short circuit due to misalignment between the damascene wiring and the contact plug.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명함으로써 본 발명을 상세하게 설명한다. 그러나 본 발명은 이하에서 개시되는 실시예에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있으며, 단지 본 실시예들은 본 발명의 개시가 완전하도록함과 동시에, 통상의 지식을 가진자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이다. 이하에서 개시되는 실시예에서 어느 한 막이 다른 막 또는 기판위에 존재하는 것으로 지칭될 때, 다른 막 또는 기판 바로 위에 있을 수도 있고, 층간막이 존재할 수도 있음을 밝혀둔다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be embodied in various forms, and only the embodiments of the present invention may be completed by the present invention to those skilled in the art. It is provided to fully inform the category. In the embodiments disclosed below, when either film is referred to as being on another film or substrate, it is noted that it may be directly over the other film or substrate and an interlayer film may be present.
도 1 내지 도 4는 본 발명의 바람직한 실시예에 따른 다층배선 형성방법을 설명하기 위해 도시한 단면도들이다.1 to 4 are cross-sectional views illustrating a method for forming a multilayer wiring according to a preferred embodiment of the present invention.
도 1을 참조하면, P형 또는 N형의 반도체 기판(50) 상에, N형 또는 P형 트랜지스터(도시되지 않음)와 같은 하부구조물에 의해 굴곡이 형성된 반도체 기판 표면을 평탄화시키고 절연시킬 목적으로, 평탄화층(52)을 형성한다. 상기 평탄화층(52) 상에, 이후의 개구부 형성시 상기 평탄화층(52)의 손상을 방지할 목적으로 식각저지층(54)을 형성한 다음 패터닝하여, 콘택 플러그가 형성될 영역의 상기 평탄화층(52) 일부를 노출시킨다.Referring to FIG. 1, for the purpose of planarizing and insulating a semiconductor substrate surface on which a bend is formed by a substructure such as an N-type or P-type transistor (not shown), on a P-type or N-type semiconductor substrate 50. The planarization layer 52 is formed. On the planarization layer 52, an etch stop layer 54 is formed and then patterned for the purpose of preventing damage to the planarization layer 52 in the subsequent opening formation. The planarization layer of the region where the contact plug is to be formed (52) Expose some.
상기 평탄화층(52)은 유동성 있는 절연물, 예컨대 BPSG, PSG, BSG 등과 같은 불순물이 도우프된 산화물을 증착하여 형성하거나, HTO, LTO 등과 같은 불순물이 도우프되지 않은 산화물 즉, USG(Undoped Silicate Glass)를 이용하여 형성할 수 있으며, 바람직하게는, 상기 평탄화층(52)을 약 10000Å∼15000Å의 두께로 형성한 후 CMP 공정을 이용하여 요철이 존재하는 상부 표면을 평탄하게 만든다.The planarization layer 52 is formed by depositing an oxide doped with a flowable insulator, such as BPSG, PSG, BSG, or the like, or an oxide that is not doped with impurities such as HTO, LTO, or USG (Undoped Silicate Glass). ), And preferably, the planarization layer 52 is formed to a thickness of about 10000 kPa to 15000 kPa, and then the upper surface where the unevenness exists is flattened using a CMP process.
상기 식각저지층(54)은 소정의 이방성 식각에 대해, 상기 평탄화층(52)을 구성하는 물질 보다 식각비가 작은 물질, 예를 들면, 실리콘 옥시 나이트라이드, 비정질실리콘, 또는 다결정실리콘으로 형성하며, 더욱 바람직하게는 실리콘 나이트라이드로 형성한다. 또한, 상기 식각저지층(54)은, 상기 소정의 이방성 식각에 견딜 수 있을 정도의 두께 예컨대, 500Å∼1000Å의 두께로 형성한다.The etch stop layer 54 is formed of a material having a smaller etching ratio than a material constituting the planarization layer 52, for example, silicon oxy nitride, amorphous silicon, or polycrystalline silicon, for a predetermined anisotropic etching. More preferably, it is formed of silicon nitride. In addition, the etch stop layer 54 is formed to a thickness sufficient to withstand the predetermined anisotropic etching, for example, a thickness of 500 kPa to 1000 kPa.
도 2를 참조하면, 식각저지층(54)이 형성된 결과물 상에 절연물, 예컨대 산화물을 증착하여 제1 층간절연막(56)을 형성한다. 상기 제1 층간절연막(56) 상에, 다마신 배선과 콘택 플러그가 형성될 영역을 노출시키는 포토레지스트 패턴(도시되지 않음)을 형성한 다음, 포토레지스트 패턴을 식각마스크로 적용하고 상기 제1 층간절연막(56)과 평탄화층(52)을 선택적으로 제거함으로써, 다마신 배선이 형성될 영역의 상기 식각저지층(54)과 콘택 플러그가 형성될 영역의 상기 기판(50)을 부분적으로 노출시키는 개구부들(D, P)을 형성한다.Referring to FIG. 2, an insulating material, for example, an oxide is deposited on the resultant on which the etch stop layer 54 is formed to form a first interlayer insulating film 56. A photoresist pattern (not shown) is formed on the first interlayer insulating layer 56 to expose a region where the damascene wiring and the contact plug are to be formed. Then, the photoresist pattern is applied as an etching mask and the first interlayer is formed. By selectively removing the insulating film 56 and the planarization layer 52, an opening that partially exposes the etch stop layer 54 in the region where the damascene wiring is to be formed and the substrate 50 in the region where the contact plug is to be formed. Form (D, P).
여기서, 상기 식각저지층(54)에 대해 식각 선택비가 큰 조건으로 상기 제1 층간절연막(56)과 평탄화층(52)을 건식식각함으로써, 콘택 플러그가 형성될 영역의 평탄화층(52)이 제거되는 동안 다마신 배선이 형성될 영역의 평탄화층(52)이 제거되지 않도록 하는 것이 바람직하다.In this case, the first interlayer insulating layer 56 and the planarization layer 52 are dry etched under the condition that the etching selectivity layer 54 has a large etching selectivity, thereby removing the planarization layer 52 in the region where the contact plug is to be formed. It is preferable that the planarization layer 52 of the region where the damascene wiring is to be formed is not removed during the process.
도 3을 참조하면, 개구부(D, P)가 형성된 결과물 전면에 상기 개구부를 완전히 매립할 수 있을 정도의 두께로 금속, 예컨대 텅스텐(W)을 증착하여 도전층을 형성한다. 다음, 상기 도전층에 대한 CMP 공정을 수행하여 상기 제1 층간절연막(56) 상부에 형성된 도전층을 제거함으로써, 개구부를 매립하는 다마신 배선(58)과 콘택 플러그(60)를 형성한다.Referring to FIG. 3, a conductive layer is formed by depositing a metal, for example tungsten (W), to a thickness sufficient to completely fill the opening on the entire surface of the resultant in which the openings D and P are formed. Next, the CMP process is performed on the conductive layer to remove the conductive layer formed on the first interlayer insulating layer 56, thereby forming the damascene wiring 58 and the contact plug 60 filling the openings.
본 발명의 바람직한 실시예에 따르면, 제1 층간절연막(56) 상부에 형성된 금속층을 제거하는 상기 CMP 공정 후, 추가적으로 상기 금속층과 제1 층간절연막을 과도하게 연마한다.According to a preferred embodiment of the present invention, after the CMP process of removing the metal layer formed on the first interlayer insulating film 56, the metal layer and the first interlayer insulating film are additionally excessively polished.
또한, 상기 금속층을 형성하기 전, 개구부가 형성된 결과물 전면에 질화티타늄과 같은 내화 금속(refractory metal)을 증착하여 장벽금속층(도시되지 않음)을 형성하는 것이 바람직하다.In addition, before forming the metal layer, it is preferable to form a barrier metal layer (not shown) by depositing a refractory metal such as titanium nitride on the entire surface of the resultant product in which the opening is formed.
도 4를 참조하면, 다마신 배선(58)과 콘택 플러그(60)가 형성된 결과물 전면에, 절연물 예컨대 산화물을 증착하여 제2 층간절연막(62)을 형성하고, 사진식각공정을 이용하여 콘택 플러그(60) 일부를 노출시키는 비아홀을 형성한다. 계속해서, 결과물 전면에 금속, 예컨대 알루미늄을 증착한 후 패터닝함으로써 상기 콘택 플러그(60)와 접속되는 금속 배선(64)을 형성한다.Referring to FIG. 4, a second interlayer insulating layer 62 is formed by depositing an insulator, for example, an oxide, on the entire surface of the resulting damascene wire 58 and the contact plug 60, and using a photolithography process to form a contact plug ( 60) form via holes exposing a portion. Subsequently, a metal, for example, aluminum is deposited on the entire surface of the resultant, and then patterned to form a metal wiring 64 connected to the contact plug 60.
상기 금속 배선(64)은 따라서, 상기 콘택 플러그(60)를 통해 반도체 기판(50) 특히, 활성영역(도시되지 않음)과 전기적으로 접속된다.The metal wire 64 is thus electrically connected to the semiconductor substrate 50, in particular an active region (not shown), via the contact plug 60.
이상, 본 발명을 구체적인 실시예를 들어 상세하게 설명하였으나, 본 발명은 상기 실시예에 한정되지 않고, 본 발명의 기술적 사상의 범위 내에서 당 분야에서 통상의 지식을 가진 자에 의하여 여러 가지 변형이 가능하다.The present invention has been described in detail with reference to specific embodiments, but the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention. It is possible.
상기한 바와 같이, 본 발명에 따르면 한번의 사진식각공정을 통해 다마신 배선과 콘택 플러그가 형성될 개구부를 형성하므로, 다마신 배선과 콘택 플러그 간에 미스얼라인으로 인한 단락 발생 가능성이 없다.As described above, according to the present invention, since the opening for forming the damascene wiring and the contact plug is formed through one photolithography process, there is no possibility of a short circuit due to misalignment between the damascene wiring and the contact plug.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980021060A KR20000001036A (en) | 1998-06-08 | 1998-06-08 | Multilayer interconnection forming method using chemical mechanical polishing |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980021060A KR20000001036A (en) | 1998-06-08 | 1998-06-08 | Multilayer interconnection forming method using chemical mechanical polishing |
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| KR20000001036A true KR20000001036A (en) | 2000-01-15 |
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| KR1019980021060A KR20000001036A (en) | 1998-06-08 | 1998-06-08 | Multilayer interconnection forming method using chemical mechanical polishing |
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1998
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