KR19990088171A - Borderless contact to diffusion with respect to gate conductor and methods for fabricating - Google Patents

Abstract

The present invention employs a double insulating film stack as a mask to define the contact conductor shape for the entire chip, and to define a relatively thin damage protection layer on the exposed conductive layer after defining the gate conductor shape. To provide a borderless contact for the gate conductor to the diffusion. In one embodiment, an insulating layer is formed on a substrate, a conductive layer is provided on the insulating layer, a second insulating layer is provided on the conductive layer, a third insulating layer is provided on the second insulating layer, Removing the preselected portions of the second and third insulation layers, providing a damage prevention layer in the portions from which the second and third insulation layers have been removed, removing the preselected portions of the third insulation layer, removing the damage prevention layer, The borderless contact is formed by removing the exposed portion of the conductive layer and removing the exposed portion of the second insulating layer.

Description

Semiconductor structure and manufacturing method therefor {BORDERLESS CONTACT TO DIFFUSION WITH RESPECT TO GATE CONDUCTOR AND METHODS FOR FABRICATING}

The present invention relates to providing a diffusionless borderless contact to a gate conductor. According to the present invention, the diffuser contact is superimposed on the gate conductor without shorting to the gate. In particular, the present invention relates to a method of providing a borderless contact to a diffusion and a gate conductor by employing a single contact masking process. The invention also relates to a semiconductor structure having the desired borderless contact. The invention is particularly applicable to fabricating logic with SRAM cells and embedded SRAMs.

In forming a semiconductor device, it is necessary to make the required electrical connection between specific areas of the device formed on the substrate and to prevent connection between various other areas of the device formed on the substrate. One technique to achieve this is to use photoresist and masking techniques, which pattern the areas to be exposed for photoelectric contact in the photoresist and develop the patterned photoresist, thereby exposing the required areas located below. Let's go. This technique usually requires several consecutive masks to perform the entire process, and each subsequent mask must be aligned correctly during the process run. However, as technology improves to form smaller and smaller devices, it becomes increasingly difficult to maintain accurate overlay tolerance, so that even a small portion of an area that needs to remain covered even by small misalignment of the mask. Boundary "is exposed. Thus, for example, the electrical connection by overlay deposition of metal will connect not only the required position but also the exposed boundary portion of the undesired position.

Thus, what have been called borderless contacts have been manufactured. However, for example in the case of SRAM cells, the limiting factor in shrinking the cell is the contact to the diffusion associated with the gate conductor. This limiting factor is such that the diffusion contact is not shorted to the gate conductor. This has been achieved by simply providing sufficient distance between the diffuser contact and the gate so that it never intersects the gate within the process tolerances where the diffuser contact is employed. Borderless contacts provide a means of preventing electrical shorts when the contacts cross the border, thereby reducing the distance between the border and the contact by allowing the contact to cross over a "boundary" when the SRAM cell is a gate. Furthermore, in borderless contacts, it is necessary to contact the borderless element itself, such as in the case of an SRAM cell, to contact the gate conductor. In order to achieve this, a separate gate contact mass was previously used, but for this a separate important mask step is added. Accordingly, what is needed is a method of implementing borderless contacts to gate contacts and diffusions that do not cause short circuits and require no additional masking steps.

The present invention relates to providing a diffusion-free contact for a gate conductor. In particular, according to the present invention, it is possible to prevent a short circuit and to implement a borderless contact. Moreover, according to a preferred aspect of the present invention, borderless contacts are implemented by employing a single contact mask.

More specifically, the present invention relates to a semiconductor structure comprising a semiconductor substrate, a conductive region on the substrate, a borderless contact adjacent to the conductive region, the conductive region comprising an intermittent self-aligned insulating cap for protecting the borderless contact. Has a capless area for contacting the conductive regions.

The invention also relates to a method of manufacturing such a semiconductor structure. In particular, the process according to the present invention includes providing a semiconductor substrate, providing a first insulating layer on the semiconductor substrate, and forming a conductive layer on the first insulating layer. A second insulating layer is formed on the conductive layer and a third insulating layer is formed on the second insulating layer. Next, the process includes selectively removing portions of the second and third insulating layers in accordance with the predetermined pattern, and forming a damage prevention layer in the portions from which the second and third insulating layers have been removed. The damage prevention layer is a self-aligned layer formed by oxidizing the conductive layer so that the third insulating layer can be removed. The preselected portion of the remaining third insulating layer is selectively removed according to the predetermined pattern, and the damage prevention layer is removed without etching the conductive layer. Now, the exposed portion of the conductive layer not covered with the second insulating layer is removed. The second insulating layer exposed by the removal of the third insulating layer is removed to form the required semiconductor structure.

In accordance with another aspect of the present invention, there is provided another method of fabricating a structure having borderless contacts for diffusion associated with a gate conductor. This alternative process includes providing a defined conductive gate structure on a semiconductor substrate and blanket depositing a barrier layer followed by blanket depositing a first insulating layer. The top of the gate is exposed by polishing the first insulating layer using a gate stack of gate and barrier layers serving as a polish stop. The selected portion of the barrier layer and the underlying gate portion are etched to correspond to the area to be isolated from the contact to the diffusion. Subsequently, after depositing a conformal barrier layer, the recesses created in the gate region are filled with the polysilicon layer. The polysilicon is polished over the barrier layer. The exposed barrier layer is removed and a second insulating layer is deposited. As a result, a material is formed that forms a contact for the diffusion and the gate in the region not covered by the isolation cap.

In another embodiment of the present invention, the required structure provides a conductive gate on a semiconductor substrate, blanket deposits a barrier layer over the gate and the substrate, and blankets a non-conformal first insulating layer over the barrier layer. It is made by vapor deposition. The unbonded layer is formed thicker on the horizontal surface as compared to the vertical sidewalls of the gate structure. A sacrificial metal layer is deposited and optionally polished, the polishing proceeds over a protruding insulating peak above the conductive gate line. The insulating layer is etched over the underlying barrier layer. After filling the recessed region in the insulating layer over the gate region, which will have a protective cap, it is planarized to fit over the remaining portion of the sacrificial layer. The removal of the sacrificial layer then leaves a cap on top of the gate region that will act as an etch stop and insulating material for subsequent etching and filling processes to provide self aligned contacts. The structure is covered with a second insulating layer that can later be planarized. This structure is then patterned and etched into contacts for the borderless diffusion to the conductive gate line that already has the cap. Portions not covered with the cap of the conductive gate line may form a contact through the same etching used to pattern the diffusion contacts.

Yet another embodiment of the present invention includes blanket depositing a barrier layer over a preformed gate and a semiconductor substrate and depositing a first insulating layer over the barrier layer. The insulating layer is planarized and the structure is masked so that the open region corresponds to the gate where the cap will be formed in a subsequent process. In a subsequent process, the first insulating layer on the gate is etched in the region where the gate where the cap is to be formed is located. A second barrier layer is selectively deposited over the exposed barrier zone remaining on top of the gate. The second insulating layer is deposited and then planarized. In this step, the contact for the diffusion that is borderless to the gate can be patterned and etched.

Another embodiment of fabricating a structure according to the present invention comprises blanket depositing a barrier layer over a semiconductor substrate and a preformed gate structure, depositing an adhesion promoting layer over the barrier layer, and over the adhesion promotion layer. Blanket depositing the first insulating layer. The first insulating layer is polished to an adhesion layer located on top of the gate. Chemically amplified photoresist is deposited. The portion of the resist that is in direct contact with the adhesion promoter layer is modified to poor removal after exposure and baking. The resist is then exposed to electromagnetic radiation, then baked and developed. The portion in contact with the adhesion promoting layer in the resist remains unremoved even after development by denaturation, acting as a cap over the gate portion to be protected from contact with the diffusion. The first insulating layer is etched to expose the underlying adhesion promoting layer, and then the adhesion promoting layer is also removed by etching, and the underlying barrier layer is partially etched. This results in a difference in thickness in the barrier layer from the top of the gate structure to the diffusion, which will be needed to form a contact self alignment for the gate. Next, all remaining resist is removed and the adhesion layer is removed from above the gate portion. The second insulating layer is blanket deposited and then planarized and patterned to provide self aligned contacts to the gate.

In another variation of the process, the initial polishing of the first insulating layer is terminated with a relatively thin layer of insulating layer left over the gate and masked to select the area over the gate where the cap will be formed in a subsequent process. Subsequently, the gate region to be provided with the surplus cap may be exposed by etching, and then the process may proceed as described above.

Another process in accordance with the present invention includes blanket depositing a barrier layer over a preformed gate structure, blanket depositing a layer of oxidizable material, and depositing a second barrier layer. By depositing and then patterning the planarization layer, the second barrier layer over the gate portion to be delimited is exposed. Removal of the planarization layer removes the second barrier layer in the exposed area. The remaining planarization layer is removed to provide a layer of oxidizable material exposed to the portion of the gate that will be delineated. The exposed oxidizable material is then oxidized. The remaining second barrier layer is removed. Removal of the remaining oxidizable material forms a structure with oxidized material that forms a cap in the gate in the preselected area where the gate will be demarcated with respect to the diffusion. This structure can be processed by a standard process in which the oxide layer acts as an etch stop, so that during the contact etch process for the diffusion, the contacts will not be shorted to the gate region.

Other objects and advantages of the invention will be readily understood by those skilled in the art from the following detailed description, which is intended to illustrate only preferred embodiments of the invention by illustrating the best mode contemplated for carrying out the invention. It is written. As will be appreciated later, it is possible to implement the invention in other different embodiments without departing from the scope of the invention, and some details of the invention may be varied in various and obvious respects. Accordingly, the detailed description is to be regarded as illustrative in nature and not as restrictive.

1 to 5 are schematic diagrams of structures at various stages of a process according to an embodiment of the invention,

6 to 8 are schematic views of the structure at various stages of another process according to the invention,

9-12 are schematic views of structures at various stages of a process according to another embodiment of the invention,

13-15 are schematic views of structures at various stages of a process according to another embodiment of the invention,

16-21 are schematic diagrams of structures at various stages of a process according to another embodiment of the process of the present invention,

22 is a schematic diagram of a structure according to the present invention.

Explanation of symbols for the main parts of the drawings

1: semiconductor substrate 2: first insulating layer

3: conductive layer

4 zone for self-aligned silicide formation

6: second insulating layer 7: third insulating layer

For better understanding of the invention, reference will now be made to the drawings, which schematically illustrate process steps according to one embodiment of the invention. According to the present invention, the first insulating layer 2 is provided on the semiconductor substrate 1. The semiconductor substrate 1 is typically silicon but may be any other kind of semiconductor material, such as group III-V semiconductors. The insulating layer 2 may be grown on a substrate or provided by a deposition technique such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The insulating layer 2 may also be provided by thermally oxidizing the substrate 1 to provide silicon dioxide. Typically, this insulating layer has a thickness of about 20 kPa to about 350 kPa, more typically about 30 kPa to about 100 kPa, and acts as a gate insulator.

A conductive material 3, such as a doped polycrystalline silicon layer, is provided on the insulating layer 2. The conductive layer 3 may form a gate electrode in a semiconductor element to be formed on a semiconductor substrate. Typically, the conductive layer 3 has a thickness of about 500 kPa to about 4000 kPa, more typically about 1500 kPa to about 3000 kPa.

The second insulating layer 6 is provided on the conductive layer 3. Typically, the second insulating layer has a thickness of about 300 kPa to about 1500 kPa, more typically about 500 kPa to about 1000 kPa. In addition, the insulating layer 6 is typically formed by oxidizing the deposited tetraethylorthosilicate by heating to a temperature of about 400 ° C. to about 750 ° C. to form an oxide, or more generally by CVD deposition. It can be an oxide.

Then, a third insulating layer 7 is provided on the second insulating layer 6. The third insulating layer 7 typically has a thickness of about 500 kPa to about 2500 kPa, more typically about 1000 kPa to about 2000 kPa, and even more typically about 1500 kPa to about 2000 kPa. . Moreover, the third insulating layer is typically at least about twice as thick as the second insulating layer. However, the relative thickness between the second insulating layer and the third insulating layer will vary depending on the relative etch rate ratio between the second insulating layer and the third insulating layer.

Selected portions of the insulating film stacks of the second and third insulating layers are removed, for example, by etching, according to a predetermined pattern. For example, the selected portion is removed according to a pattern that defines the gate conductor shape for the entire chip. Specifically, the selected portion may be removed by employing conventional photolithographic techniques such as applying and patterning photosensitive resist material 8 to provide the desired gate structure. The patterned photoresist acts as a mask to remove the third insulating layer and then the exposed portions of the second insulating layer while the other portions of the second and third insulating layers are protected from etching.

When the third insulating layer is nitride, it may be removed by reactive ion etching or downstream plasma source etching. Likewise, oxide layer 6 may be removed via reactive ion etching.

Next, the remaining photoresist is removed, for example, by dissolving in a suitable solvent. After removal of the photoresist, a damage preventing layer 9 may be provided over the conductive layer from which the second and third insulating layers have been removed (see FIG. 2). The damage protection layer can be provided by thermally oxidizing the polysilicon conductive layer, and typically has a thickness of about 20 kPa to about 350 kPa, preferably about 60 kPa to about 150 kPa, and about 100 kPa is typical. The oxide can grow thermally over polysilicon but not over the nitride layer. This oxide layer provides a nitride etch stop.

The preselected portion of the third insulating layer is removed in accordance with the predetermined pattern using a mask (see FIG. 3). The third insulating layer can be etched through reactive ion etching and provides a gate contact. The remaining resist is then dissolved in a suitable solvent to remove it.

Next, the thin anti-damage layer is removed, since the thickness of the anti-damage layer is considerably thin compared to the exposed second insulating layer, the second insulating layer still remains while the anti-damage layer is removed (see FIG. 4).

The conductive layer portion is removed using both the second and third insulating layers as masks (see FIG. 5). The exposed portion of the second insulating layer is then removed by exposing the third insulating layer to expose the underlying conductive layer, which provides a region 4 for conventional logic contact and subsequent self-aligned silicide formation. Let's do it.

As can be seen above, the method according to the present invention enables the use of a masking layer to allow conventional gate formation in the area where no borderless contact is required and a self aligned silicide process should be performed. As can be seen, this mask protects the insulator stack in the area where borderless contact to the gate is needed, and the nitride cap insulator is removed throughout the rest, but the oxide is not removed. Residual etch stop oxide is removed from the top of the conductor via a short oxide etch.

An advantage of this method according to the invention is that it provides optimum dimensional control by performing gate conductor lithography on a flat surface. Moreover, gate conductor etching is performed using hard masks (nitrides and oxides) known to provide improved dimensional control. These advantages are realized by the present invention, which provides a means for forming borderless contacts on devices where density is required for gate conductivity. Furthermore, reference is made to FIG. 22, which illustrates the advantages achievable by the present invention, in particular due to the presence of a third insulating layer which allows for the misalignment of contact studs 70, such as tungsten, to be provided in a subsequent process. . The third insulating layer prevents underlying conductive material 3, such as doped polycrystalline silicon, from contacting the stud. In Fig. 22, reference numerals 71 and 72 denote source and drain regions, 73 denote an optional auxiliary nitride etch, 74 denote an interlevel dielectric, 75 denote metal wiring, and 76 denote sidewall isolation.

They may be provided through techniques well known in the art and need not be described in more detail herein.

In another embodiment according to the present invention (see FIG. 6), the device is processed to include forming a gate structure, but before a contact is made to the gate and the diffusion, a standard barrier layer such as silicon nitride 22 is formed. Blanket deposition is carried out on the insulating layer 2 on the substrate 1 and on the gate structure 21. The conductive gate 3 is provided by polycrystalline silicon, the upper portion of which is silicided. Insulating layer 23 is blanket deposited over layer 22. The insulating layer 23 may be silicon dioxide and may be provided by a deposition technique such as chemical vacuum deposition or physical vacuum deposition. Typically, silicon nitride layer 22 has a thickness of about 100 GPa to about 1000 GPa, more typically about 250 GPa to about 750 GPa. In addition, insulating layer 23 typically has a thickness of about 2000 kPa to about 5000 kPa, more typically about 3000 kPa to about 4000 kPa.

An important part of this alternative process of the present invention is the step of polishing the insulating layer 23 to the gate structure by using chemical-mechanical polishing (CMP), in which the gate stack acts as a polishing stop and is shown in FIG. As shown, the top of the gate is exposed.

According to a preferred aspect of the present invention, the wafer is patterned using photoresist 24, with openings in the patterned photoresist corresponding to the area of the gate to be isolated from the contact for the diffusion (see FIG. 7). Subsequently, by etching the patterned region, not only a portion of the gate structure but also the exposed silicon nitride cap 22 and silicide located at the upper portion of the gate are removed to provide a recessed gate structure. The etchant employed is preferably a chemically reactive ion etch in which the insulating layer 23 surrounding the gate structure does not etch to a detectable degree.

The remaining resist layer 24 can then be removed and the recessed polycrystalline silicon can be silicided if necessary. Subsequently, in a preferred aspect of this embodiment according to the present invention, a conforming barrier layer, such as silicon nitride, for filling the gate recess can be deposited.

Next, the silicon nitride barrier layer 25 is subjected to directional etching or CMP to remove nitrides that are not located in the grooves created by partial removal of the gate.

A second insulating layer, such as silicon dioxide, is deposited, for example by chemical vacuum deposition, to provide a layer 26 that forms a contact for the diffusion and the gate in the region not covered with the silicon nitride cap (see FIG. 8).

In accordance with a third embodiment of the present invention (see FIG. 9), a conforming barrier, such as silicon nitride, is formed over a previously formed silicided polysilicon gate 21 and a gate oxide 2 on a semiconductor substrate 1. Layer 30 is blanket deposited. The matching barrier layer, which is preferably silicon nitride, typically has a thickness of about 100 kPa to about 1000 kPa, more typically about 250 kPa to about 750 kPa. Next, an unattached insulating layer is provided, for example, from a silan oxide, wherein layer 31 is formed thicker on the horizontal surface as compared to the vertical sidewall surface adjacent the gate structure. Typically the thin film 31 should be at least about 1.5 times thicker on the horizontal surface than the sidewall surface, and more typically about twice the thickness, in a typical example about 0.2 μm thick on the horizontal surface and about thick on the sidewall. 0.05 μm.

Typically, this layer has a thickness of about 100 mm 3 to about 500 mm 3, more typically about 200 mm 3 to about 300 mm 3. Subsequently, a sacrificial layer 32 such as tungsten or TiN + tungsten is deposited. The sacrificial layer typically has a thickness of about 0.15 to about 0.4 μm, more typically about 0.2 to about 0.3 μm, and in certain instances has a thickness of about 0.3 μm. Subsequently, the sacrificial layer 32 is polished to an oxide and then polished to the oxide peak protruding from the upper portion of the gate. Polishing is an optional process. As an alternative at this stage of the process, the wafer can be patterned so that the portion where the cap is needed is opened on the polysilicon line. The wafer is then etched over the nitride layer located below to remove the oxide layer. This etching process is optional for the tungsten sacrificial layer 32 (see FIG. 10).

By removing the remaining resist (see FIG. 11), a structure is obtained in which the area above the polysilicon line on which the cap is to be formed becomes a recessed area surrounded by the sacrificial layer 32. The recess is filled, for example by employing CVD silicon nitride 34 and planarized to fit over the sacrificial layer 32 through a subsequent polishing process.

The sacrificial layer 32 may be removed by, for example, a wet dip etching process. Accordingly, a cap is provided over the polysilicon line, which will act as an etch stop and insulation material when etching and filling self aligned contacts.

The unbonded oxide 31 can remain intact. This structure can now be applied with an additional oxide layer 35 of doped silicate glass, such as silicate glass doped with boron and / or phosphorus. The other oxide layer 31 may then be polished, resulting in standard patterning and etching steps for the formation of contacts to the diffusion without borders for the polysilicon lines on which the caps are formed. Structure is obtained. Areas where the cap of the polysilicon line is not formed may be contact formed through the same etching.

In another embodiment (see FIG. 13), a conformal barrier layer, such as silicon nitride 51, having a thickness of approximately 2000 GPa is blanket deposited. An adhesion promoting layer, such as titanium nitride 52, may be deposited, for example, by sputtering. The adhesion promoting layer typically has a thickness of about 50 mm 3 to about 1500 mm 3, more typically about 300 mm 3 to about 700 mm 3, and in certain instances has a thickness of about 500 mm 3. The doped silicate glass 53 is deposited to provide an insulating layer. This insulating layer typically has a thickness of about 2000 kPa to about 6000 kPa, more preferably about 3000 kPa to about 5000 kPa, and in certain instances has a thickness of about 4000 kPa. The doped silicate glass, such as BPSG, is then polished by CMP to the etch stop layer on the polysilicon line to expose the titanium nitride on the polysilicon line. The photoresist 54 can then be deposited, for example, by spinning. Thereafter, the photoresist 54 is exposed to electromagnetic radiation having an appropriate wavelength, baked and then developed. The photoresist is a chemically amplified photoresist that is susceptible to denaturation by a substrate, such as APEX, a p-hydroxy styrene-based DUV photoresist available from Shipley. By employing a chemically amplified resist, the portion of the resist that is in direct contact with titanium nitride will be modified. Thus, after exposure, baking, and developing, the resist is completely developed in contact with the titanium nitride, but the resist layer in the area in contact with the titanium will remain.

The modified resist cap located on a portion of the polysilicon line acts as a protective barrier to preserve nitride on top of the polysilicon line (see FIG. 14). The doped silicate glass can be removed, for example, by wet etching with an aqueous HF acid etchant, exposing the underlying titanium nitride layer. Exposed portions of the titanium nitride layer can be removed, for example, by reactive ion etching. This etching will also remove a portion of the silicon nitride underneath the titanium nitride. This results in a thickness difference in the nitride thin film from the top of the polysilicon line to the diffusion, which will be used to make contact magnetic alignment for the polysilicon gate. The remaining resist material is then removed by, for example, a plasma stripping technique and the titanium nitride on the polysilicon line is removed. The doped silicate glass is then deposited, planarized, and patterned to etch the self aligned contacts to the gate.

In an alternative variant of the present process, the initial polishing process of the doped silicate glass 53 may be performed such that a small portion of, for example, about 0.2 μm is left over the gate region. Subsequently, a block mask is provided to determine on the gate the region where the cap will be formed in a subsequent process. Reactive ion etching will expose the region with excess nitride of silicon nitride in the polysilicon 21.

16-21 show another embodiment of the present invention. In this alternative process, a matching barrier layer 61, such as silicon nitride, is deposited over the preformed polysilicon gate structure 21 and over the gate insulator. A layer of oxidizable material 62 such as aluminum is deposited. This layer typically has a thickness of about 100 mm 3 to about 500 mm 3, more typically about 200 mm 3 to about 300 mm 3, in this example about 250 mm 3. A second barrier layer 63 such as silicon nitride is then blanket deposited over the oxidizable layer 62. This layer typically has a thickness of about 200 mm 3 to about 1000 mm 3, more typically about 400 mm 3 to about 600 mm thick. A planarization layer, such as an organic antireflective coating (ARC) 64, is typically formed on top of the polysilicon gate 21 to a thickness of about 100 mm to about 500 mm, more typically from about 200 mm to about 300 mm Deposit to thickness. The thickness of the planarization layer is typically approximately the height of the gate 21, for example approximately 0.2 μm. The photoresist layer 65 is then applied and patterned, for example using a contact mask. The wafer is then reactive ion etched to remove selected portions of the ARC layer, which stops when the barrier layer located on top of the gate, such as silicon nitride layer 63, is exposed. The exposed silicon nitride located above the gate is removed through selective reactive ion etching in the selected portion. The remaining resist and ARC are then removed through a standard oxygen or ozone fusion stripping process to expose the layer of oxidizable material 62, such as titanium nitride or aluminum, at the gate portion to be debounded. .

The exposed oxidizable material 62, such as aluminum, is thermally oxidized, for example, by placing the wafer in a rapid thermal annealing tool or furnace. Residual silicon nitride 63 is removed via, for example, chemical wet etching. The underlying oxidizable layer 62 is removed by etching, leaving an oxide cap layer 66, such as aluminum oxide, on top of the gate that needs to be demarcated with respect to the diffusion. The remaining process can be performed, where oxide 66 acts as an etch stop so that during contact etch to the diffusion, the contact will not be shorted to the gate.

Also, in any of the above processes, if desired, the cap can be made protruding against the polysilicon line to ensure short-circuit protection for the gate and to control the capacitance between the gate and the contact.

The foregoing description of the invention illustrates and describes the invention. In addition, while the disclosure discloses and describes only preferred embodiments of the invention, as mentioned above, the invention may be used in a variety of other combinations, modifications, environments, and as described above and / or in the art or It will be appreciated that variations or modifications may be made within the scope of the inventive concept as indicated herein corresponding to the knowledge. The above described embodiments illustrate the best mode for implementing the present invention, and those skilled in the art can use the present invention within such or other embodiments as well as various modifications required by the specific application or use of the present invention. Should be interpreted. Accordingly, the above description should not be construed as limiting the invention to the forms described herein only. In addition, the appended claims should be construed as including other embodiments.

The present invention has the advantage of implementing borderless contacts to diffusions associated with gates that are not shorted with the gates using a single contact mask that does not require an additional masking process.

Claims (35)

① semiconductor substrate, (2) a conductive region on the semiconductor substrate, (3) include borderless contacts adjacent to the conductive region, Wherein the conductive region comprises an intermittent self-aligned insulating cap having at least two different layers of material to provide the borderless contact and a capless region for connecting the conductive regions. The method of claim 1, And the self-aligned insulating cap is silicon nitride located over silicon dioxide. The method of claim 1, And the conductive region is polycrystalline silicon. The method of claim 1, And the semiconductor substrate is silicon. The method of claim 1, And the conductive region is a conductive gate. The method of claim 1, And the semiconductor structure is a conductive gate in an SRAM cell. The method of claim 1, And the self-aligned insulating cap includes a silicon dioxide layer of about 500 GPa to about 1000 GPa under a silicon nitride layer of about 1000 GPa to about 2000 GPa. ① providing a semiconductor substrate, ② providing a first insulating layer on the semiconductor substrate, (3) providing a conductive layer on the first insulating layer; ④ providing a second insulating layer on the conductive layer, (5) providing a third insulating layer of a material different from said second insulating layer on said second insulating layer, ⑥ selectively removing a portion of the third insulating layer and the second insulating layer according to a predetermined pattern; (7) providing a damage preventing layer on the conductive layer in the region where the second insulating layer and the third insulating layer are removed; ⑧ selectively removing a portion of the remaining third insulating layer, ⑨ removing the damage prevention layer; (B) removing said conductive layer in portions exposed by removal of said second insulating layer, (B) removing said second insulating layer of the portion exposed by removing said third insulating layer. Semiconductor structure manufacturing method comprising a. The method of claim 8, And the second insulating layer is an oxide. The method of claim 9, And the oxide has a thickness of about 300 GPa to about 1500 GPa. The method of claim 9, And the oxide has a thickness of about 500 GPa to about 1000 GPa. The method of claim 8, And the third insulating layer is silicon nitride. The method of claim 12, And the silicon nitride has a thickness of about 1000 GPa to about 2000 GPa. The method of claim 12, And the silicon nitride has a thickness of about 1500 kPa to about 2000 kPa. The method of claim 8, And the conductive layer is polycrystalline silicon. The method of claim 8, And the damage prevention layer is silicon oxide. The method of claim 16, And the silicon oxide has a thickness of about 20 GPa to about 350 GPa. The method of claim 16, And the silicon oxide has a thickness of about 60 GPa to about 150 GPa. (1) forming a gate structure on the semiconductor substrate; (2) providing a barrier layer over said gate structure; (3) providing a first insulating layer over said barrier layer; (4) chemical mechanical polishing the first insulating layer using the gate structure serving as a polishing stop; Selectively etching a portion of the barrier layer and selectively etching a gate portion located below the etched portion of the barrier layer to correspond to a region to be later isolated from the contact to the diffusion; (6) forming a conformal conductive layer filling the gate recess; (7) polishing the mating conductive layer over the remaining barrier layer, ⑧ removing the remaining exposed barrier layer, (9) forming a second insulating layer in the region not covered by the carrier cap to form contacts for the diffusion and the gate; Semiconductor structure manufacturing method comprising a. The method of claim 19, Wherein said barrier layer is semiconductor nitride, said first insulating layer is silicon dioxide, said second insulating layer is silicon dioxide, and said gate and said mating conductive layer are polysilicon. (1) forming a gate structure on the semiconductor substrate; (2) forming a barrier layer over the gate structure; (3) forming a non-bonded insulating layer on the barrier layer, wherein the unbonded insulating layer has a thicker horizontal surface than the vertical sidewall surface adjacent the gate structure; ④ forming a sacrificial metal layer on the unattached insulating layer; ⑤ by selectively polishing the sacrificial layer over an insulating layer located above the gate structure to pattern the sacrificial layer, thereby opening an area to be provided with a protective cap on the gate; ⑥ etching the sacrificial layer; ⑦ forming and polishing the second insulating layer Semiconductor structure manufacturing method comprising a. The method of claim 21, And the non-compatible insulating layer is formed from silane oxide. The method of claim 21, And the sacrificial layer is tungsten. The method of claim 21, Wherein said barrier layer is silicon nitride and said second insulating layer is silicon dioxide. The method of claim 21, And wherein said unbonded layer is at least 1.5 times thicker on said horizontal surface than on said sidewall surface. (1) forming a gate structure on the semiconductor substrate; (2) forming a conforming barrier layer over the gate structure; (3) forming a first conformal insulating layer over said barrier layer; ④ planarizing the first insulating layer, (5) selectively etching said first insulating layer in a region where a cap will be formed later on said gate; (6) selectively depositing a second barrier layer over the exposed barrier layer remaining over the selected portion of the gate; (7) forming a second insulating layer and planarizing the insulating layer; ⑧ patterning and etching the contact for the diffusion without boundary to the gate Semiconductor structure manufacturing method comprising a. The method of claim 26, Wherein the first and second barrier layers are silicon nitride and the first and second insulating layers are silicon dioxide. (1) forming a gate structure on the semiconductor substrate; (2) forming a conforming barrier layer over the gate structure; (3) forming an adhesion promoting layer on the barrier layer; ④ forming a first insulating layer on the adhesion promoting layer, (5) polishing the first insulating layer up to the adhesion layer located on the gate structure; ⑥ depositing chemically amplified photoresist; ⑦ removing the portion of the photoresist that is not in contact with the adhesion promoting layer by exposing, baking and developing the photoresist to electromagnetic radiation; (8) etching the first insulating layer; (9) etching the adhesion promoting layer exposed by etching the first insulating layer; (B) etching the exposed barrier layer by etching the adhesion promoter layer; (B) removing all photoresist and adhesion layers remaining on the gate portion; (B) depositing and planarizing a second insulating layer over the structure; 패 patterning to provide self-aligned contacts to the gate Semiconductor structure manufacturing method comprising a. The method of claim 28, Polishing the first insulating layer terminates to provide a relatively thin insulating layer over the gate, and masking to selectively provide an area on the gate to be later formed with a cap. The method of claim 29, And the adhesion promoting layer is titanium nitride. (1) forming a gate structure on the semiconductor substrate; (2) forming a conforming barrier layer over the gate structure; (3) forming an oxidizable material on the barrier layer; ④ forming a second barrier layer over the oxidizable layer; ⑤ forming a planarization layer on the second barrier layer, (6) patterning said second barrier layer to expose an oxidizable layer on said gate by removing portions over said gate that will be demarcated; (7) oxidizing the exposed oxidizable material; ⑧ removing the second barrier layer; ⑨ removing the oxidizable material; ⑩ providing contacts to the gate through diffusion Semiconductor structure manufacturing method comprising a. The method of claim 31, wherein And wherein said oxidizable material is aluminum. The method of claim 31, wherein And the planarization layer is an antireflective coating. The method of claim 31, wherein And the barrier layers are silicon nitride. The method of claim 31, wherein And the insulating layer is silicon dioxide.