KR19990084521A - DRAM device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a DRAM device and a method of manufacturing the same, wherein a second insulating film is formed on a first insulating film formed on a semiconductor substrate, and the second insulating film and the first insulating film are sequentially etched to form a storage electrode contact hole. Spacers are formed on both sidewalls of the storage electrode contact hole, and a portion of the thickness of the second insulating layer is etched to form a spacer protrusion. The storage electrode is formed on the storage electrode contact hole and the second insulating layer by including the spacer protrusion. By the method of manufacturing a DRAM device, it is possible to prevent the storage electrode from falling off or to collapse the storage electrode in a subsequent cleaning process, thereby forming a storage electrode having a good pattern.

Description

DRAM DEVICE AND METHOD OF FABRICATING THE SAME

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a DRAM cell capacitor and a method for manufacturing the same.

As the integration of DRAM devices increases, not only the size of the cell transistors, but also the area occupied by the cell transistors decreases. However, even if the size of the cell transistor is reduced, since the capacitance of the cell capacitor cannot be reduced, various DRAM cell capacitor manufacturing methods have been devised to ensure the capacitance of the cell capacitor. One of them is a method of securing the capacitance of the cell capacitor by raising the storage electrode in the Z-axis by an amount in which the surface area of the storage electrode is reduced in the X-axis and the Y-axis, thereby compensating for the reduced surface area.

1 is a view showing a conventional DRAM cell capacitor at the time of misalignment.

Referring to FIG. 1, a gate 14 is formed on a semiconductor substrate 10 with a gate oxide film (not shown) interposed therebetween. For example, the gate 14 is formed by stacking a polysilicon film 14a, a tungsten silicide film 14b, and a silicon nitride film 14c in this order. Source / drain regions (not shown) are formed in the semiconductor substrate 10 on both sides of the gate 14. The first insulating layer 18 is formed on the semiconductor substrate 10 including the gate 14.

A pad poly 20 is formed through the first insulating layer 18 and electrically connected to the source / drain regions. The second insulating layer 22 is formed on the first insulating layer 18 including the pad poly 20. A portion of the second insulating layer 22 is etched to form a storage contact hole, and the storage contact hole is filled with a conductive layer to form a storage electrode contact plug 24a electrically connected to the pad poly 20. A polysilicon film, for example, is formed on the second insulating film 22 including the storage electrode contact plug 24a to have a thickness of 10000 GPa.

A photoresist film (not shown) is formed on the polysilicon film, and a storage electrode is defined and patterned. The polysilicon film is etched by a poly etch back process in which the photoresist film pattern is used as a mask to form the same storage electrode 24.

In the process of etching the polysilicon film, a storage electrode, that is, a polysilicon film, an etch back process (a polysilicon film removing process having a thickness within the range of 13000 kPa-15000 kPa is applied) is performed, so that the storage electrode contact plug is performed. Significant overetching occurs for the storage electrode 24 in the upper region of 24a and the second insulating film interface region.

When the storage electrode 24a is misaligned with respect to the storage contact plug 24a, the storage electrode 24 may be formed at an upper region of the storage contact plug 24a and the insulating layer interface region due to the overetching. As a result, the polysilicon film is overetched further, resulting in a smaller junction area between the storage electrode contact plug 24a and the storage electrode 24. Thus, the upper portion of the storage contact plug 24a loses its ability to support the storage electrode 24 having a height of 10000 mm 3. As a result, the storage electrode 24 may fall away or the storage electrode 24 may collapse in a subsequent cleaning process, causing unwanted electrical shorts in the DRAM device and forming bad memory cells.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a method of manufacturing a DRAM cell capacitor which can prevent the storage electrode from falling off or falling down in the subsequent cleaning process. Another object of the present invention is to provide a method for manufacturing a DRAM cell capacitor capable of forming a storage electrode of a good pattern.

1 is a cross-sectional view showing a conventional misaligned DRAM device;

2A through 2E are flowcharts sequentially illustrating a manufacturing process of a DRAM device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10, 100: semiconductor substrate 12, 102: device isolation region

14, 104: gate 18, 22, 108, 112: insulating film

114, 118: silicon nitride film 24, 110, 120: polysilicon film

(Configuration)

According to a feature of the present invention proposed to achieve the above object, a method of manufacturing a DRAM device includes the steps of forming a second insulating film on a first insulating film formed on a semiconductor substrate; Forming a storage electrode contact hole by sequentially etching the second insulating film and the first insulating film; Forming spacers on both side walls of the storage electrode contact hole; Etching a portion of the thickness of the second insulating film to form a spacer protrusion; And forming the storage electrode including the spacer protrusion on the second insulating layer including the storage electrode contact hole.

According to a feature of the present invention proposed to achieve the above object, a DRAM cell capacitor includes a storage electrode contact hole through which an insulating film formed on a semiconductor substrate and a portion of the semiconductor substrate surface is exposed; Spacers formed on both sidewalls of the storage electrode contact hole and having a height greater than that of the storage electrode contact hole; The storage electrode may include a storage electrode formed on the insulating layer, including a spacer between the inside of the storage contact hole and at least one side wall.

Referring to FIG. 2E, spacers are formed on both sidewalls of the storage electrode contact hole, and a portion of the thickness of the second insulating layer is etched to form a spacer protrusion. The storage electrode is formed on the storage electrode contact hole and the second insulating layer by including the spacer protrusion. According to the method of manufacturing a DRAM device, by forming a storage electrode including a portion of a spacer formed on both side walls of the storage electrode contact, a portion of the upper spacer serves as a storage electrode support, and the storage electrode is separated or The storage electrode can be prevented from falling down during the subsequent cleaning process.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. 2A to 2E.

2A through 2E are flowcharts sequentially illustrating a method of manufacturing a DRAM cell capacitor according to the present invention.

First, referring to FIG. 2A, an isolation region 102 is formed by defining an active region and an inactive region on a semiconductor substrate 100, and a gate oxide layer (not shown) interposed therebetween. 104 is formed. The gate 104 is formed by laminating a polysilicon film 104a, a tungsten silicide film 104b, and a silicon nitride film 104c in this order. Source / drain regions (not shown) are formed in the semiconductor substrate 100 on both sides of the gate 104.

The first insulating layer 108 is formed on the semiconductor substrate 100 including the gate 104, and the pad poly 110 penetrates the first insulating layer 108 and is electrically connected to the source / drain regions. Is formed. A second insulating film 112 is formed on the first insulating film 108 including the pad poly 110, and then a bit line is formed through a lamination, photo and etching process of the bit line film (not shown). do. For example, the bit line is a multilayer film in which a polysilicon film and a tungsten silicide film are laminated.

A third insulating film is formed on the second insulating film 108 including the bit line. For example, a BPSG film (not shown) is formed.

A silicon nitride film 114 is formed on the third insulating film so as to have a thickness within a range of 70 GPa-100 GPa. This is to prevent damage to the lower insulating film in the wet etching and cleaning process of the subsequent process. The HTO film 116 is formed on the silicon nitride film 114 to have a thickness of about 3000 kPa. The HTO layer 116 prevents the silicon nitride layer 114 from being etched during the subsequent etching of the polysilicon layer for forming the storage electrode.

A photoresist film (not shown) is formed on the HTO film 116, and the photoresist film is subjected to a photolithography process so that a portion of the HTO film 116 is exposed at a portion where a storage electrode contact is to be formed. It is etched to form a photoresist layer pattern (not shown).

The photoresist film pattern is used as a mask so that the HTO film 116, the silicon nitride film 114, the third insulating film, the second insulating film 112, and the first insulating film 108 are sequentially etched to form the pad poly 110. The storage electrode contact hole is exposed.

Including the storage electrode contact hole, a silicon nitride film for spacer formation (not shown) is formed on the HTO film 116 to have a thickness of 200 to 500 Å. The thickness of the silicon nitride film is changed according to the size of the contact hole. The spacer nitride forming silicon nitride layer is anisotropically etched to form spacers 118 on both sidewalls of the storage electrode contact hole. In this case, when the nitride film for spacer formation is etched, a portion of the upper portion of the HTO film 116 may be etched according to an etching selectivity of the silicon nitride film and the HTO film 116.

Subsequently, the spacer protrusion 118a is formed by etching the upper portion of the HTO layer 116 with a thickness of 2000Å-2500Å.

Next, a polysilicon film for forming a storage electrode is formed on the HTO film 116 including a storage electrode contact hole. In this case, the storage electrode contact hole is completely filled with the polysilicon film. Subsequently, a photoresist film is formed on the polysilicon film for forming the storage electrode, and a photolithography process is performed to form a photoresist film pattern defining the storage electrode.

The photoresist layer pattern is used as a mask to etch the polysilicon layer for forming the storage electrode to form the storage electrode 120. In this case, the spacer protrusion 118a is formed at a lower portion of the storage electrode 120.

According to the present invention, in the conventional DRAM cell capacitor manufacturing method, when the storage electrode and the storage electrode contact are misaligned during the formation of the storage electrode, the upper portion of the upper portion of the storage contact is formed by a polysilicon film etching process performed based on the storage electrode 10000 ms. As the polysilicon layer is over-etched, the storage electrode is separated or the storage electrode is collapsed in a subsequent cleaning process, and the storage electrode is formed by including a portion of the spacer formed on both side walls of the storage electrode contact. The spacer protrusion serves as a storage electrode support, thereby preventing the storage electrode from falling off or falling down of the storage electrode during the subsequent cleaning process.

Claims (8)

Forming a second insulating film 116 on the first insulating films 108 and 114 formed on the semiconductor substrate 100; Forming a storage electrode contact hole by sequentially etching the second insulating film 116 and the first insulating film 108, 114; Forming spacers (118) on both side walls of the storage electrode contact hole; Etching a portion of the thickness of the second insulating film 116 to form the spacer protrusion 118a; And forming the storage electrode (120) including the spacer protrusion (118a) on the second insulating film (116) including the storage electrode contact hole. The method of claim 1, The first insulating film (108, 114) is a DRAM cell capacitor manufacturing method comprising a multi-layer film in which a BPSG film and a silicon nitride film (114) is sequentially stacked in the upper region. The method of claim 2, The silicon nitride film 114 is formed to have a thickness within the range of 70 ~ 100 Å. The method of claim 1, And the second insulating film 116 is an HTO film. The method of claim 1, The second insulating film 116 is formed to have a thickness of about 3000 kPa, and after the etching process, the second insulating film has a thickness within the range of 500 kPa to 1000 kPa, and the spacer 118 is formed to have a thickness within the range of 200 kPa to 500 kPa. DRAM cell capacitor manufacturing method. The method according to claim 1 or 5, The spacer 118 is a method of manufacturing a DRAM cell capacitor formed of a silicon nitride film. A storage electrode contact hole penetrating an insulating film formed on the semiconductor substrate 100 and exposing a portion of the surface of the semiconductor substrate 100; Spacers 118 formed on both sidewalls of the storage electrode contact hole and having a height greater than that of the storage electrode contact hole; And a storage electrode (120) formed on the insulating layer including spacers (118) on at least one sidewall of the storage contact hole. The method of claim 7, wherein The spacer 118 is a DRAM cell capacitor formed of a silicon nitride film.