KR19990081403A - Main amplifier circuit of semiconductor memory - Google Patents

Abstract

The present invention relates to a main amplifier circuit of a semiconductor memory, and the main amplifier circuit of a conventional semiconductor memory amplifies the input data to a power supply voltage by separately using an amplifying means for amplifying the input data and an amplifying means for amplifying the output data. When the time is delayed and the time for storing the memory cell is shortened and the semiconductor memory operates at high speed, an error occurs in the stored data. In view of the above problems, the present invention includes: an input data amplifier for amplifying input data input from the outside and applying and maintaining the amplified input data to input / output lines and inverted input / output lines; A transmission control unit for selectively transmitting and controlling input data or output data; An equalizer for precharging and equalizing the input / output lines and the inverted input / output lines; A main amplifier circuit of a semiconductor memory including a latch unit for amplifying and holding output data output from a memory cell, the main amplifier circuit comprising: a first amplifier for amplifying and maintaining the non-amplified input data according to a write enable signal to the latch unit; A transmission unit; And further comprising a second transfer section for transferring and controlling output data amplified and held in the latch section to the output buffer section in accordance with a read enable signal, using the input data amplifying means and the output data amplifying means simultaneously. By increasing the time to amplify and store in the memory cell, there is an effect of storing the data without error even when the memory operates at high speed.

Description

Main amplifier circuit of semiconductor memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main amplifier circuit of a semiconductor memory, and more particularly, to a main amplifier circuit of a semiconductor memory, which is suitable for storing accurate data in a memory cell during a high-speed operation of the memory by amplifying and outputting input data within a short time. will be.

In general, the conventional semiconductor memory amplifies the input data in the main amplifier, applies it to the bit line through the input / output control circuit and the sense amplifier, and stores it in a specific memory cell. The main amplifier may include a precharge and equalization unit which precharges the input / output line and the inverting input / output line with the same voltage and reduces the error thereof; Amplifying means for amplifying the input data; And amplifying means for amplifying data of the memory cell output from the sense amplifier. The main amplifier circuit of the conventional semiconductor memory will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of a general semiconductor memory, which includes a memory cell unit 1, which is an entity that stores data including a plurality of memory cells; A sense amplifier 2 for amplifying data input / output to the memory cell unit 1 through the bit line and the inverted bit line; An enable controller (3) for enabling control of the bit line and the inverted bit line; In the state in which the bit line and the inverted bit line are enabled by the enable control unit 3, amplify the data output through the sense amplifier 2 and output the result to the input / output pad 7 through the output path 5. The main amplifier 4 receives the data applied through the input / output pad 7 through the input path 6 and amplifies and applies the data to the sense amplifier 2.

FIG. 2 is a circuit diagram of a main amplifier of a conventional semiconductor memory. As shown in FIG. 2, the input data applied to the input / output line IO and the inverting input / output line IOB according to the data driving signals MPIT, MPIB, MNIT, and MNIB is supplied. A write data driver 10 which amplifies and outputs the voltage VDD; The input data amplified by the write data driver 10 is turned off during a write operation according to a transfer control signal MAOP, and is turned on during a read operation and applied to the input / output line IO and the inverted input / output line IOB. A transmission control unit 20 for controlling the transmission of the output data of the semiconductor memory; An equalization unit 30 for precharging and equalizing the input / output line IO and the inverting input / output line IOB according to the input / output line equalization signal MAP; The latch unit 40 latches output data of a memory cell applied through the input / output line IO and the inverting input / output line IOB according to a main amplifier enable signal MAE, and outputs the result to the outside through a read path. do.

The write data driver 10 is connected in series between the input / output line IO and the inverting input / output line IOB, receives a power supply voltage VDD at its contact point, and receives the data driving signals MPIT and MPIB. PMOS transistors PM1 and PM2 that are conductively controlled according to " A source and a drain are connected to the input / output line IO or the inverting input / output line IOB and the ground, respectively, and the NMOS transistor NM1 is electrically controlled according to the data driving signals MNIT and MNIB applied to the respective gates. ), (NM2).

The transmission control unit 20 is conductingly controlled according to the transmission control signal MAOP to apply and control the data applied to the input / output line IO and the inverting input / output line IOB, respectively, PMOS transistors PM3 and PM4. It consists of.

The equalizer 30 includes a PMOS transistor PM5 connected to the input and output lines IO and the inverted input and output lines IOB, respectively, and electrically connected and controlled according to the input / output line equalization signal MAP; It is connected in series between the input / output line IO and the inverting input / output line IOB, receives a precharge voltage VP at its contact point, and conducts according to the input / output line equalization signal MAP applied to each gate. PMOS transistors PM6 and PM7 controlled.

The latch 40 is enabled according to the main amplifier enable signal MAE to latch and 41 amplify and latch output data of a semiconductor memory cell applied to the input / output line IO and the inverting input / output line IOB. )Wow; The output buffer unit 42 outputs data latched by the latch unit 41 to the outside according to the main amplifier enable signal MAE.

The operation of the main amplifier circuit of the conventional semiconductor memory configured as described above will be described below.

First, when there is no input / output of data, the input / output line equalization signal MAP is applied at a low potential for a predetermined time to conduct all of the PMOS transistors PM5 to PM7, thereby allowing the input / output line IO and the inverting input / output line IOB. The precharge voltage VP is applied to and equalized.

Then, during the write operation, input data is applied through the input / output line IO and the inverting input / output line IOB through the write path. For convenience of explanation, the following operation will be described on the assumption that a high potential signal is applied to the input / output line IO and a low potential signal is applied to the inverting input / output line IOB.

As such, when low potential input data is applied to the input / output line IO and the inverted I / O line IOB, the data driving signals MPIT and MNIT are all low potential, the data driving signal MPIB, Both MNIBs are applied at high potential to turn on and turn off the PMOS transistors PM1 and PM2, respectively, and to turn off and turn on the NMOS transistors NM1 and NM2, respectively. According to the operation of the MOS transistor, a power supply voltage VDD is applied to the input / output line IO, and a ground voltage is applied to the inverting input / output line IOB.

Accordingly, the input data is amplified by the power supply voltage VDD, which is maintained as the transmission control signal MAOP is applied at high potential, which is sensed by the sense amplifier and stored in the memory cell.

In this case, a predetermined time is required until the input / output line IO becomes the power supply voltage VDD.

During a read operation, data of a semiconductor memory is applied through the input / output line IO and the inverting input / output line IOB, which is an input / output line IO and an inverting input / output line IOB already equalized by the transmission controller 20. Is amplified and latched in the latch portion 41 of the latch 40 and is output to the outside through the output buffer 42.

However, when the operation speed of the semiconductor memory becomes faster and the time for writing data to the semiconductor memory cell becomes shorter, the input data amplified by the conventional data driver is applied to the sense amplifier through a plurality of delay elements, thereby further writing operation time. This is shortened, and thus there is a problem that can not be stored in the correct data to speed up the speed. In particular, when the potential of the data stored in a specific memory cell and the current data to be stored is different, the problem of data error becomes larger.

It is an object of the present invention to provide a main amplifier circuit of a semiconductor memory capable of maintaining a time for storing input data in a memory cell even when the operation speed of the semiconductor memory increases.

1 is a block diagram of a general semiconductor memory.

2 is a main amplifier circuit diagram of a conventional semiconductor memory.

Fig. 3 is a main amplifier circuit diagram of the semiconductor memory of the present invention.

*** Description of the symbols for the main parts of the drawings ***

10: write data drive unit 20: transmission control unit

30: equalization part 40: latch

41: latch portion 42: output buffer portion

50: first transmission unit 60: second transmission unit

The above object includes an input data amplifier for amplifying input data input from the outside and applying and maintaining the amplified input data to input / output lines and inverted input / output lines; A transmission control unit for selectively transmitting and controlling input data or output data; An equalizer for precharging and equalizing the input / output lines and the inverted input / output lines; A latch unit for amplifying and holding output data output from the memory cell; In the main amplifier circuit of the semiconductor memory consisting of an output buffer unit for buffering the output data amplified and held in the latch unit to output to the outside, the amplified by applying the non-amplified input data to the latch unit in accordance with a write enable signal And a first transmission unit to be maintained; This is achieved by further comprising a second transfer unit for transferring and controlling output data amplified and held in the latch unit according to a read enable signal to the output buffer unit, which will be described in detail with reference to the accompanying drawings. Is as follows.

FIG. 3 is a main amplifier circuit diagram of the semiconductor memory of the present invention. As shown in FIG. 3, other configurations are the same as those of the related art, except that the write data driver 10 is not amplified according to the write enable signal WTEN. A first transmission unit (50) which applies and controls the input data to the latch unit (41); The output data of the semiconductor memory applied to the input / output line IO and the inverting input / output line IOB and amplified and latched by the latch section 41 is applied to the output buffer section 42 according to the read enable signal RDEN. It further comprises a second transmission unit 60 to.

Each of the first transmitters 50 is conductively controlled according to the write enable signal WTEN, and transmits input data through an input / output line IO and an inverted input / output line IOB, respectively. (TG2).

Each of the second transfer units 60 is conductively controlled in accordance with the read enable signal RDEN to transmit the input data latched by the latch 41 to the output buffer unit 42. (TG4).

The operation of the main amplifier circuit of the semiconductor memory of the present invention configured as described above will be described below.

First, when there is no data input / output from the semiconductor memory, the input / output line equalization signal MAP is applied at a low potential to precharge and equalize the input / output line IO and the inverting input / output line IOB.

Next, when input data is applied through the input / output line IO and the inverting input / output line IOB, the write enable signal WTEN and the data driving signals MPIT, MPIB, MNIT, and MNIB are applied.

At this time, the PMOS transistors PM1 and PM2 of the transmission control unit 20 are both turned off. Accordingly, data applied to the input / output line IO and the inverting input / output line IOB is a power supply voltage VDD. ) And the ground voltage. In this case, all of the transfer gates TG1 and TG2 of the first transfer unit 50, to which the write enable signal WTEN is applied, are turned on and applied to the input / output line IO and the inverting input / output line IOB. The input data is applied to the latch unit 41, and the latch unit 41 converts the input data to the power supply voltage VDD value before the write data driver 10 amplifies the input data to the power supply voltage VDD value. Amplify and maintain.

Accordingly, the time required for input data to be stored in the semiconductor memory cell is increased, so that accurate data can be stored even when the semiconductor memory is speeded up.

In addition, when data stored in a memory cell is output, output data applied to the input / output line IO and the inverting input / output line IOB is applied to the latch unit 41 through the transmission control unit 20 to supply power voltage. Amplified to (VDD) value, the output data amplified and maintained as the transmission gates TG3 and TG4 of the second transmission unit 6 receiving the read enable signal RDEN become conductive is output buffered. It is applied to the unit 40 and eventually output to the outside.

As described above, the present invention uses the latch portion used in the read operation of the semiconductor memory as a means for amplifying the input data in the write operation, thereby increasing the writing time of the input data into the memory cell, thereby allowing accurate data to be stored even at a high speed of the semiconductor memory. There is an effect that can be stored in a cell.

Claims (3)

An input data amplifier for amplifying input data input from the outside and applying and maintaining the amplified input data to the input / output line and the inverted input / output line; A transmission control unit for selectively transmitting and controlling input data or output data; An equalizer for precharging and equalizing the input / output lines and the inverted input / output lines; A latch unit for amplifying and holding output data output from the memory cell; In the main amplifier circuit of the semiconductor memory consisting of an output buffer unit for buffering the output data amplified and held in the latch unit to output to the outside, the amplified by applying the non-amplified input data to the latch unit in accordance with a write enable signal And a first transmission unit to be maintained; And a second transfer unit configured to transfer and control output data amplified and held in the read enable signal to the output buffer unit. 2. The apparatus of claim 1, wherein the first transfer unit is electrically controlled in accordance with a write enable signal to transfer the unamplified input data applied to the input / output line and the inverted input / output line to two input terminals of the latch unit. A main amplifier circuit of a semiconductor memory, comprising a second transfer gate. 2. The first and second transfer gates of claim 1, wherein the second transfer unit is electrically controlled with a read enable signal, respectively, to transfer and output the output data amplified and held by the latch unit to two input terminals of the output buffer unit. A main amplifier circuit of a semiconductor memory, which is configured.