KR19990080173A - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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KR19990080173A
KR19990080173A KR1019980013236A KR19980013236A KR19990080173A KR 19990080173 A KR19990080173 A KR 19990080173A KR 1019980013236 A KR1019980013236 A KR 1019980013236A KR 19980013236 A KR19980013236 A KR 19980013236A KR 19990080173 A KR19990080173 A KR 19990080173A
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film
insulating film
semiconductor device
metal
forming
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KR1019980013236A
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KR100254774B1 (en
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박건욱
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김규현
아남반도체 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

반도체 소자 제조시 폴리 실리콘과 전극용 금속막 사이를 절연하기 위하여 적층 구조의 절연막을 증착하여 반도체 소자를 제조하는 방법에 관한 것으로, 소자 분리 영역이 정의된 실리콘 웨이퍼의 각 활성 영역에 반도체 소자를 각각 형성하고, 실리콘 웨이퍼의 전면에 화학 기상 증착법에 의해 적층 구조 절연막을 증착한 다음, 화학 기계적 연마 공정에 의해 평탄화한다. 그리고, 절연막 표면에 드러나는 취약면을 보호하기 위한 PETEOS막을 증착한 후, 전극 연결을 위한 콘택트 홀을 형성하고, 콘택트 베리어 메탈을 형성하여 열처리 공정을 통해 콘택트 실리사이드를 형성한 다음, 금속막을 증착하고, 패터닝하여 금속 전극 패턴을 형성한다. 이렇게 하여, PETEOS막이 화학 기계적 연마 공정 이후 적층 구조 절연막의 표면에 드러나는 취약면을 보호하고, 후속 공정의 영향에 대한 저항성, 특히 인장 응력에 대한 저항성을 증대시킴으로써 후속 금속 전극 패턴 형성을 쉽게 할 수 있을 뿐만 아니라 반도체 소자의 제조 수율을 향상시킬 수 있다.The present invention relates to a method of manufacturing a semiconductor device by depositing an insulating film having a laminated structure in order to insulate between polysilicon and an electrode metal film during fabrication of a semiconductor device. The multilayer structure insulating film is deposited by chemical vapor deposition on the entire surface of the silicon wafer, and then planarized by a chemical mechanical polishing process. Then, after depositing a PETEOS film to protect the weak surface exposed on the surface of the insulating film, forming a contact hole for electrode connection, forming a contact barrier metal to form a contact silicide through a heat treatment process, and then deposit a metal film, Patterning to form a metal electrode pattern. In this way, the PETEOS film can easily form the subsequent metal electrode pattern by protecting the weak surface exposed to the surface of the laminated structure insulating film after the chemical mechanical polishing process, and increasing the resistance to the influence of the subsequent process, especially the tensile stress. In addition, the manufacturing yield of the semiconductor device can be improved.

Description

반도체 소자 제조 방법Semiconductor device manufacturing method

본 발명은 반도체 소자 제조 방법에 관한 것으로, 더욱 상세하게는 반도체 소자 제조시 폴리 실리콘과 전극용 금속막 사이를 절연하기 위하여 적층 구조의 절연막을 증착하여 반도체 소자를 제조하는 방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device by depositing an insulating film of a laminated structure in order to insulate between polysilicon and a metal film for electrodes in manufacturing a semiconductor device.

일반적으로 반도체 소자는 구조적으로 트랜지스터와, 바이폴러 IC(integrated circuit), MOS(metal-oxide-semiconductor) IC로 구분할 수 있다. 이러한 반도체 소자는 기본적으로 실리콘 웨이퍼에 베이스/이미터/컬렉터 또는 게이트/소스/드레인과 같은 각 소자의 전극 영역이 형성된 구조를 가진다. 현재 일반적으로 사용되고 있는 반도체 소자 제조 공정을 설명하면 다음과 같다. 먼저, 하나의 실리콘 웨이퍼에 각각의 반도체 소자가 형성될 활성 영역을 정의한 다음, 웨이퍼 일관 가공(FAB, fabrication) 공정에 의해 정의된 각 활성 영역에 각각의 반도체 소자를 형성한다. 그리고, 최종 단계로 전극을 형성하기 위하여 각 전극 영역과 접속되는 금속막 패턴을 형성하게 된다. 이때, 금속막 패턴에 의한 각 소자의 전극 영역이 전기적으로 단락(short)되는 것을 방지하기 위하여 금속막과 각 소자의 전극 영역이 형성된 실리콘 웨이퍼를 절연시켜야만 한다.In general, semiconductor devices may be structurally divided into transistors, bipolar integrated circuits (ICs), and metal-oxide-semiconductor (MOS) ICs. Such a semiconductor device basically has a structure in which electrode regions of respective devices, such as a base / emitter / collector or a gate / source / drain, are formed on a silicon wafer. Referring to the semiconductor device manufacturing process that is generally used as follows. First, an active region in which each semiconductor element is to be formed on one silicon wafer is defined, and then a semiconductor element is formed in each active region defined by a wafer fabrication (FAB) fabrication process. In order to form the electrode in the final step, a metal film pattern connected to each electrode region is formed. In this case, in order to prevent the electrode region of each device from being electrically shorted by the metal film pattern, the silicon wafer on which the metal film and the electrode region of each device are formed must be insulated.

이러한 금속막과 실리콘 웨이퍼(각 소자의 전극 영역)의 절연을 위한 절연막은 화학 기상 증착법(CVD, chemical vapor deposition)에 의한 PSG(phospho-silicate glass)막 또는 BPSG(boro-phospho-silicate glass)막을 주로 사용한다. 현재 PSG막 또는 BPSG막 형성에 사용되는 화학 기상 증착 장비를 도 1에 예시하였다. 도 1에서와 같이 화학 기상 증착 장비는 증착에 필요한 반응 가스를 공급하는 인젝터(I)가 다중으로 형성된 핫 플레이트 방식을 이용하거나 적외 복사 가열 방식을 이용한 인 라인형(in-line type) 반응기가 이용된다.The insulating film for insulating the metal film and the silicon wafer (electrode region of each device) may be formed of a phospho-silicate glass (PSG) film or a boro-phospho-silicate glass (BPSG) film by chemical vapor deposition (CVD). Mainly used. Chemical vapor deposition equipment currently used to form PSG film or BPSG film is illustrated in FIG. 1. As shown in FIG. 1, the chemical vapor deposition apparatus uses an in-line type reactor using a hot plate method in which an injector I is provided in multiple layers to supply a reactive gas for deposition, or an infrared radiation heating method. do.

따라서, 벨트 컨베이어(B)의 이동에 따라 벨트 컨베이어에 적재된 실리콘 웨이퍼(1,11)에는 각 인젝터(I)에서 공급되는 반응 가스에 의하여 화학 반응이 일어나고, 이러한 반응에 의하여 PSG막 또는 BPSG막이 적층된다.Accordingly, as the belt conveyor B moves, chemical reactions occur in the silicon wafers 1 and 11 loaded on the belt conveyor by the reaction gas supplied from each injector I. As a result, the PSG film or the BPSG film is formed. Are stacked.

그러면, 도 1과 같은 화학 기상 증착 장비로 BPSG 적층 절연막을 증착하는 종래의 모스 트랜지스터를 제조하는 방법을 설명하면 다음과 같다.Next, a method of manufacturing a conventional MOS transistor for depositing a BPSG stacked insulating layer using a chemical vapor deposition apparatus as shown in FIG. 1 will be described.

먼저, 도 2a에서와 같이 실리콘 웨이퍼(1)의 소자 분리 영역에 트랜치(2) 또는 LOCOS(local oxidation of silicon) 방법에 의한 필드 산화막을 형성하여 실리콘 웨이퍼(1)상에 모스 트랜지스터가 형성될 활성 영역을 정의한다. 그리고, 정의된 활성 영역에 게이트 산화막과 폴리 실리콘을 증착한 후, 패터닝(patterning)하여 게이트 전극을 형성한다. 그 다음, 형성된 게이트 전극을 레지스터로 실리콘 웨이퍼의 활성 영역에 불순물을 도핑하여 소스/드레인 영역을 형성하고, 게이트 전극의 측벽에 스페이서를 형성함으로써, 각각의 활성 영역에 모스 트랜지스터(3, 4)를 형성한다. 이후, 후속 공정에서 절연막으로 증착되는 BPSG막이 수분 함량이 많으므로, 이에 의한 실리콘 웨이퍼(1) 및 모스 트랜지스터(3,4)의 결함 방지 및 알칼리 이온이 실리콘 웨이퍼(1)로 확산되는 것을 방지하기 위하여 PMD(pre metal dielectric) 라이너(liner)막(5)을 형성한다.First, as shown in FIG. 2A, a MOS transistor is formed on a silicon wafer 1 by forming a field oxide film by a trench 2 or a local oxidation of silicon (LOCOS) method in an isolation region of the silicon wafer 1. Define the area. The gate oxide film and the polysilicon are deposited in the defined active region, and then patterned to form a gate electrode. Then, the MOS transistors 3 and 4 are formed in each active region by forming a source / drain region by doping impurities into the active region of the silicon wafer with the formed gate electrode as a resistor and forming a spacer on the sidewall of the gate electrode. Form. Thereafter, the BPSG film deposited as the insulating film in the subsequent process has a high moisture content, thereby preventing defects of the silicon wafer 1 and the MOS transistors 3 and 4 and preventing diffusion of alkali ions into the silicon wafer 1. In order to form a PMD (pre metal dielectric) liner (5).

그 다음, 후속 공정에서 모스 트랜지스터의 전극 연결을 위해 형성되는 금속막과 폴리 실리콘(또는 소스/드레인 영역)과의 절연을 위한 절연막 형성을 위하여 PMD 라이너막이 형성된 실리콘 웨이퍼(1)를 도 1과 같은 인 라인형 화학 기상 증착 장비에 투입한다. 그러면, 벨트 컨베이어(B)에 의해 실리콘 웨이퍼(1)가 이동되면서 각 인젝터(I)에서 공급되는 반응 가스에 의해 화학 반응이 발생하여 실리콘 웨이퍼(1)상에 도 2b와 같이 적층된 구조의 BPSG막(6)이 형성된다. 이후, 절연 특성 향상을 위하여 적층 구조로 증착된 BPSG막(6)을 치밀화하고, 어느 정도의 평탄화를 얻기 위해 열처리 공정을 통해 고밀도화한다.Next, a silicon wafer 1 having a PMD liner film formed thereon for forming an insulating film for insulating the metal film formed for the electrode connection of the MOS transistor and the polysilicon (or source / drain region) in a subsequent process is shown in FIG. In-line chemical vapor deposition equipment. Then, as the silicon wafer 1 is moved by the belt conveyor B, a chemical reaction is generated by the reaction gas supplied from each injector I, and the BPSG having the structure stacked on the silicon wafer 1 as shown in FIG. 2B. The film 6 is formed. Thereafter, the BPSG film 6 deposited in a laminated structure is densified to improve insulation characteristics, and is densified through a heat treatment process to obtain a degree of planarization.

그 다음, 실리콘 웨이퍼 전면을 화학 기계적 연마(CMP; chemical mechanical polishing) 공정에 의해 적층 구조로 증착된 BPSG막(6)을 연마하여 도 2c에서와 같이 웨이퍼 전면을 평탄화한다. 그리고, 도 2d에서와 같이 각 모스 트랜지스터의 전극 연결을 위해 금속막과 각 모스 트랜지스터(3, 4)의 폴리 실리콘(또는 소스/드레인 영역)이 연결될 부위를 정의하기 위하여 포토 리소그래피(photo lithography) 공정에 의해 BPSG막(6)을 식각하여 콘택트 홀(7)을 형성한다.Then, the BPSG film 6 deposited on the silicon wafer front surface in a laminated structure by a chemical mechanical polishing (CMP) process is polished to planarize the front surface of the wafer as shown in FIG. 2C. As shown in FIG. 2D, a photolithography process is used to define a portion to which the metal film and the polysilicon (or source / drain regions) of each of the MOS transistors 3 and 4 are connected to connect the electrodes of the MOS transistors. The BPSG film 6 is etched to form the contact holes 7.

그 다음, 후속 금속 전극 형성시 콘택트 저항 감소, 이온 확산 등을 방지하기 위하여 도 2e에서와 같이 티타늄(Ti)막(8)과 질화 티타늄(TiN)막(9)으로 구성된 콘택트 베리어(barrier) 메탈막을 형성하고, 열 공정을 통해 콘택트 실리사이드를 형성한다. 이후, 스퍼터링 등을 통해 금속막을 증착하고, 패터닝하여 금속 전극 패턴을 형성함으로써 모스 트랜지스터를 완성한다.Next, a contact barrier metal composed of a titanium (Ti) film 8 and a titanium nitride (TiN) film 9 as shown in FIG. 2E to prevent contact resistance reduction and ion diffusion during subsequent metal electrode formation. A film is formed and the contact silicide is formed through a thermal process. Subsequently, the MOS transistor is completed by depositing a metal film through sputtering or the like to form a metal electrode pattern.

이와 같이 적층 구조 BPSG막을 절연막으로 이용하여 종래의 방법에 따라 반도체 소자를 제조할 경우, 화학 기계적 연마 공정 후 적층 구조 절연막의 표면에 적층의 계면(단절된 층)이 드러나게 되며, 이 계면은 적층된 다른 층의 절연막보다 취약하게 된다.As described above, when a semiconductor device is manufactured according to a conventional method using a laminated structure BPSG film as an insulating film, an interface (a disconnected layer) of the laminate is exposed on the surface of the laminated structure insulating film after a chemical mechanical polishing process, and this interface is formed on another stacked layer. It becomes weaker than the insulating film of a layer.

따라서, 이 드러난 절연막 표면의 계면은 후속의 세정 공정이나 콘택트 홀 형성을 위한 리소그래피 공정 등의 외부 영향에 의해 손상을 받게 되며, 지속적인 외부 영향을 받은 후, 그 상부에 형성되는 콘택트 베리어 메탈막의 큰 인장 응력과 콘택트 실리사이드 형성을 위한 열 처리 공정에 의한 손상에 의해 단절된 층이 계면을 따라 들고일어나게(peeling) 되므로, 후속 금속 전극 패턴을 형성하는 데 어려움이 있을 뿐만 아니라 반도체 소자의 제조 수율을 저하시킨다.Therefore, the exposed interface of the insulating film surface is damaged by an external influence such as a subsequent cleaning process or a lithography process for forming contact holes, and after a continuous external influence, a large tension of the contact barrier metal film formed thereon Since the layer disconnected due to stress and damage by the heat treatment process for contact silicide formation is peeled along the interface, it is not only difficult to form subsequent metal electrode patterns, but also lowers the manufacturing yield of the semiconductor device.

본 발명은 이와 같은 문제점을 해결하기 위하여 안출한 것으로, 그 목적은 적층 구조 절연막을 화학 기계적 연마에 의해 평탄화하였을 경우 표면에 드러나는 취약한 계면을 보호하고, 상부 박막의 인장 응력 및 후속 열 처리 공정에 따른 손상에 대한 저항성을 향상시키는 데 있다.The present invention has been made to solve the above problems, the object of which is to protect the weak interface exposed to the surface when the laminated structure insulating film is planarized by chemical mechanical polishing, and according to the tensile stress of the upper thin film and the subsequent heat treatment process To improve the resistance to damage.

도 1은 반도체 소자 제조 공정중 절연막 증착에 사용되는 화학 기상 증착 장비를 개략적으로 도시한 구성도이고,1 is a schematic diagram illustrating a chemical vapor deposition apparatus used for insulating film deposition during a semiconductor device manufacturing process;

도 2a 내지 도 2e는 도 1의 화학 기상 증착 장비를 이용하여 종래의 방법에 따라 반도체 소자인 모스 트랜지스터를 제조하는 공정을 개략적으로 도시한 공정 순서도이고,2A to 2E are process flowcharts schematically illustrating a process of manufacturing a MOS transistor, which is a semiconductor device, according to a conventional method using the chemical vapor deposition apparatus of FIG. 1,

도 3a 내지 도 3f는 도 1의 화학 기상 증착 장비를 이용하여 본 발명의 일 실시예에 따라 반도체 소자인 모스 트랜지스터를 제조하는 방법을 도시한 공정 순서도이다.3A to 3F are process flowcharts illustrating a method of manufacturing a MOS transistor, which is a semiconductor device, according to an embodiment of the present invention using the chemical vapor deposition apparatus of FIG. 1.

상기와 같은 목적을 달성하기 위하여, 본 발명은 적층 구조 절연막을 평탄화하기 위한 화학 기계적 연마 공정 이후, 평탄화된 적층 구조 절연막 표면에 드러나는 취약면을 보호하기 위하여 PETEOS막을 패드 막으로 증착한 다음, 후속 공정을 통해 반도체 소자를 제조하는 것을 특징으로 한다.In order to achieve the above object, the present invention after the chemical mechanical polishing process for planarizing the laminated structure insulating film, to deposit a PETEOS film with a pad film to protect the weak surface exposed on the planarized laminated structure insulating film surface, and then the subsequent process It is characterized by manufacturing a semiconductor device through.

이하, 첨부된 도면을 참조로 하여 본 발명에 따른 바람직한 일 실시예를 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

도 3a 내지 도 3f는 도 1과 같은 화학 기상 증착 장비를 이용하여 적층 절연막을 증착하는 본 발명의 일 실시예에 따른 모스 트랜지스터를 제조 방법을 공정 순서에 따라 도시한 실리콘 웨이퍼의 단면도이다.3A to 3F are cross-sectional views of silicon wafers in accordance with a process sequence of a method of manufacturing a MOS transistor according to an embodiment of the present invention for depositing a multilayer insulating film using a chemical vapor deposition apparatus as shown in FIG. 1.

먼저, 도 3a에서와 같이 실리콘 웨이퍼(11)의 소자 분리 영역에 트랜치(12) 또는 LOCOS 방법에 의한 필드 산화막을 형성하여 실리콘 웨이퍼(11)상에 모스 트랜지스터가 형성될 활성 영역을 정의한다. 그리고, 정의된 활성 영역에 게이트 산화막과 폴리 실리콘을 증착한 후, 패터닝하여 게이트 전극을 형성한다. 그 다음, 형성된 게이트 전극을 레지스터로 실리콘 웨이퍼의 활성 영역에 불순물을 도핑하여 소스/드레인 영역을 형성하며, 게이트 전극의 측벽에 스페이서를 형성함으로써, 각각의 활성 영역에 모스 트랜지스터(13, 14)를 형성한다. 이후, 후속 공정에서 절연막으로 증착되는 BPSG막이 수분 함량이 많으므로, 이에 의한 실리콘 웨이퍼(11) 및 모스 트랜지스터(13,14)의 결함 방지 및 알칼리 이온이 실리콘 웨이퍼(11)로 확산되는 것을 방지하기 위하여 PMD 라이너막(15)을 형성한다.First, as shown in FIG. 3A, a field oxide film is formed in the isolation region of the silicon wafer 11 by the trench 12 or the LOCOS method to define an active region in which the MOS transistor is to be formed on the silicon wafer 11. The gate oxide film and the polysilicon are deposited in the defined active region, and then patterned to form a gate electrode. Next, the MOS transistors 13 and 14 are formed in each active region by forming a source / drain region by doping impurities into the active region of the silicon wafer using the formed gate electrode as a resistor and forming a spacer on the sidewall of the gate electrode. Form. Thereafter, the BPSG film deposited as the insulating film in the subsequent process has a high moisture content, thereby preventing defects of the silicon wafer 11 and the MOS transistors 13 and 14 and preventing diffusion of alkali ions into the silicon wafer 11. The PMD liner film 15 is formed for this purpose.

그 다음, 후속 공정에서 모스 트랜지스터의 전극 연결을 위해 형성되는 금속막과 폴리 실리콘(또는 소스/드레인 영역)과의 절연을 위한 절연막 형성을 위하여 PMD 라이너막이 형성된 실리콘 웨이퍼(11)를 도 1과 같은 인 라인형 화학 기상 증착 장비에 투입한다. 그러면, 벨트 컨베이어(B)에 의해 실리콘 웨이퍼(11)가 이동되면서 각 인젝터(I)에서 공급되는 반응 가스에 의해 화학 반응이 발생하여 실리콘 웨이퍼(11)상에 도 3b와 같이 적층된 구조의 BPSG막(16)이 형성된다. 그 다음, 절연 특성 향상을 위하여 적층 구조로 증착된 BPSG막(16)을 치밀화하고, 어느 정도의 평탄화를 얻기 위해 열처리 공정을 통해 고밀도화한다.Subsequently, a silicon wafer 11 having a PMD liner layer formed thereon to form an insulating layer for insulation between a metal film formed for electrode connection of a MOS transistor and polysilicon (or a source / drain region) in a subsequent process is illustrated in FIG. In-line chemical vapor deposition equipment. Then, as the silicon wafer 11 is moved by the belt conveyor B, a chemical reaction is generated by the reaction gas supplied from each injector I, so that the BPSG having a structure stacked on the silicon wafer 11 as shown in FIG. 3B. The film 16 is formed. Then, the BPSG film 16 deposited in the laminated structure is densified to improve the insulation characteristics, and is densified through a heat treatment process to obtain a degree of planarization.

그 다음, 실리콘 웨이퍼 전면을 화학 기계적 연마 공정에 의해 적층 구조로 증착된 BPSG막(16)을 연마하여 도 3c에서와 같이 웨이퍼 전면을 평탄화한다. 이때, 적층 구조의 BPSG막(16)의 표면에는 단절된 BPSG 층의 발생으로 인한 계면이 드러나게 된다. 그 다음, 적층 구조 BPSG막(16)을 화학 기계적 연마에 의해 평탄화하였을 경우 표면에 드러나는 취약한 계면을 보호하고, 상부 박막의 인장 응력 및 후속 열 처리 공정에 따른 손상에 대한 저항성을 향상시키기 위하여 도 3d에서와 같이 평탄화된 BPSG막(16) 상부에 플라즈마 화학 기상 증착법에 의해 소정의 두께로 BPSG막보다 압축력이 있는 PETEOS(plasma enhanced thetraethyle orthosilicate)막(17)을 패드 막으로 증착한다.Then, the BPSG film 16 deposited on the silicon wafer front surface in a laminated structure by a chemical mechanical polishing process is polished to planarize the front surface of the wafer as shown in FIG. 3C. At this time, the interface due to the generation of the disconnected BPSG layer is exposed on the surface of the BPSG film 16 of the laminated structure. Next, in order to protect the fragile interface exposed to the surface when the laminated structured BPSG film 16 is planarized by chemical mechanical polishing, and to improve resistance to damage due to tensile stress of the upper thin film and subsequent heat treatment process. As described above, a PETEOS (plasma enhanced thetraethyle orthosilicate) film 17 having a compressive force than the BPSG film is deposited as a pad film on the planarized BPSG film 16 by a plasma chemical vapor deposition method.

그 다음, 도 3e에서와 같이 각 모스 트랜지스터의 전극 연결을 위해 금속막과 각 모스 트랜지스터(13, 14)의 폴리 실리콘(또는 소스/드레인 영역)이 연결될 부위를 정의하기 위하여 포토 리소그래피 공정에 의해 PETEOS막(17)과 BPSG막(16)을 식각하여 콘택트 홀(18)을 형성한다.Next, PETEOS is formed by a photolithography process to define a portion to which a metal film and a polysilicon (or source / drain region) of each of the MOS transistors 13 and 14 are connected for electrode connection of each MOS transistor, as shown in FIG. 3E. The film 17 and the BPSG film 16 are etched to form the contact holes 18.

그 다음, 후속 금속 전극 형성시 콘택트 저항 저감, 이온 확산 등을 방지하기 위하여 도 3f에서와 같이 티타늄막(19)과 질화 티타늄막(20)으로 구성된 콘택트 베리어 메탈막을 형성하고, 열 공정을 통해 콘택트 실리사이드를 형성한다. 이후, 스퍼터링 등을 통해 금속막을 증착하고, 패터닝하여 금속 전극 패턴을 형성함으로써 모스 트랜지스터를 완성한다.Then, in order to prevent contact resistance reduction and ion diffusion during subsequent metal electrode formation, a contact barrier metal film composed of the titanium film 19 and the titanium nitride film 20 is formed as shown in FIG. 3F, and the contact is made through a thermal process. Forms silicides. Subsequently, the MOS transistor is completed by depositing a metal film through sputtering or the like to form a metal electrode pattern.

이와 같이 본 발명은 적층 구조 절연막을 평탄화하기 위한 화학 기계적 연마 공정 이후, PETEOS막을 패드 막으로 증착함으로써 화학 기계적 연마 공정 이후 적층 구조 절연막의 표면에 드러나는 취약면을 보호하고, 후속 공정의 영향에 대한 저항성, 특히 인장 응력에 대한 저항성을 증대시켜 후속 금속 전극 패턴 형성을 쉽게 할 수 있을 뿐만 아니라 반도체 소자의 제조 수율을 향상시킬 수 있다.As described above, the present invention protects the weak surface exposed on the surface of the laminated structure insulating film after the chemical mechanical polishing process by depositing a PETEOS film as a pad film after the chemical mechanical polishing process to planarize the laminated structure insulating film, and resists the influence of subsequent processes. In particular, the resistance to tensile stress can be increased to facilitate the formation of subsequent metal electrode patterns as well as to improve the production yield of semiconductor devices.

Claims (2)

소자 분리 영역이 정의된 실리콘 웨이퍼의 각 활성 영역에 반도체 소자를 각각 형성하는 단계와;Forming a semiconductor device in each active region of the silicon wafer in which the device isolation region is defined; 상기 각 활성 영역에 반도체 소자가 형성된 실리콘 웨이퍼의 전면에 화학 기상 증착법에 의해 적층 구조 절연막을 증착하는 단계와;Depositing a laminated structure insulating film on the entire surface of the silicon wafer on which the semiconductor element is formed in each active region by chemical vapor deposition; 상기 적층 구조 절연막을 화학 기계적 연마 공정에 의해 평탄화하는 단계와;Planarizing the laminated structure insulating film by a chemical mechanical polishing process; 상기 평탄화된 적층 구조 절연막을 포토 리소그래피 공정에 의해 전극 연결을 위한 콘택트 홀을 형성하는 단계와;Forming a contact hole for connecting the planarized stacked structure insulating film to an electrode by a photolithography process; 상기 콘택트 홀이 형성된 적층 구조 절연막 전면에 콘택트 베리어 메탈을 형성하고, 열처리 공정을 통해 콘택트 실리사이드를 형성하는 단계와;Forming a contact barrier metal on an entire surface of the multilayer structure insulating film on which the contact hole is formed, and forming contact silicide through a heat treatment process; 상기 적층 구조 절연막을 전면에 금속막을 증착한 후, 패터닝하여 콘택트 홀을 통해 반도체 소자의 전극과 연결된 금속 전극 패턴을 형성하는 단계를 포함하되,Depositing a metal film on the entire surface of the multilayer insulating film, and then patterning the metal film to form a metal electrode pattern connected to an electrode of the semiconductor device through a contact hole, 상기 화학 기계적 연마 공정에 의한 적층 구조 절연막의 평탄화 단계 이후, 평탄화된 적층 구조 절연막 표면에 드러나는 취약면을 보호하기 위한 패드 막을 증착하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조 방법.And depositing a pad film for protecting a weak surface exposed on the surface of the planarized multilayer insulating film after the planarization of the laminated insulating film by the chemical mechanical polishing process. 청구항 1 에 있어서, 상기 패드 막은 PETEOS막으로 형성하는 것을 특징으로 하는 반도체 소자 제조 방법.The method of claim 1, wherein the pad film is formed of a PETEOS film.
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KR100688023B1 (en) * 2005-12-28 2007-02-27 동부일렉트로닉스 주식회사 Method of fabricating semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100688023B1 (en) * 2005-12-28 2007-02-27 동부일렉트로닉스 주식회사 Method of fabricating semiconductor device

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