KR19990076386A - Decoded data rearrangement device - Google Patents
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- KR19990076386A KR19990076386A KR1019980011313A KR19980011313A KR19990076386A KR 19990076386 A KR19990076386 A KR 19990076386A KR 1019980011313 A KR1019980011313 A KR 1019980011313A KR 19980011313 A KR19980011313 A KR 19980011313A KR 19990076386 A KR19990076386 A KR 19990076386A
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Abstract
The present invention relates to an apparatus and method for decoding decoded data output from a Trellis Decoder for a Grand Alliance (hereinafter abbreviated as "GA") 8 VSB (Vesigital Side band) using a Viterbi decoding algorithm The present invention relates to a decoded data rearrangement apparatus for outputting a decoded data rearranged by a trellis decoder in a trellis decoder for efficiently rearranging data in a trellis decoder, A plurality of mode control signals for rearranging the delay control signal for delaying the decoded data output from the lattice decoder and delayed decoded data thereof, Thereby delaying the decoded data output from the decoder. Also, by rearranging a plurality of decoded data output from the data delay unit according to a mode control signal selectively generated in the data rearrangement unit, decoded data can be efficiently rearranged only by a simple delay element without using an SRAM.
Description
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for receiving a digital transmission standard such as an HDTV (High Definition Television) scheme, and more particularly, to a system and method for receiving a digital broadcasting standard such as a grand alliance (hereinafter abbreviated as " GA ") 8VSB The present invention relates to a decoded data rearrangement apparatus for outputting decoded data output from a trellis decoder for efficiently rearranging decoded data output from a Trellis Decoder for a Vesigital side band.
Generally, in a digital communication system, an error control and correction technique is used to overcome a channel obstacle such as a noise or a fading phenomenon.
The error correction technique includes a channel coding technique on the transmission side and a channel decoding technique on the receiving side. The coding technique includes a coding rate R = 1/2, a constraint length K = 3, a generating polynomial ) to the G1 = 1 + X + X 2 , G2 = 1 + X 2 of the convolutional encoder (Convolution encoder), the decoding technique is to use a Viterbi decoder (Viteri decoder).
As shown in FIG. 1, the convolutional encoder mainly used as the encoding technique includes a 2-bit shift register 11 and two adders 12 and 12 'for performing modulo-2 addition The outputs G1 and G2 of the decoder are determined by the states of the contents of the 2-bit shift register 11 and the input 13, and the output states according to time are determined by the Trellis Diagram same.
Each of the points in the lattice diagram of FIG. 2 represents each state that the shift register 11 can have. A branch of the solid line indicates a transition when the input is '0' '1', and the numbers on each branch indicate the values of G1 and G2 that are output when the branch transition occurs.
At this time, as two paths are added to each state, the Viterbi decoder of the receiving side selects only the possible paths of the two paths by means of the Viterbi decoding algorithm called Maximum Likelihood Decoding The path that is not possible is discarded. The selected path is called a survivor path, and a survivor path (for example, a bold solid line in FIG. 2 represents a state 1 (01) at time unit 10) of a decision depth (decision depth or truncation depth) ) Is the survivor path of the survivor).
Therefore, the decoding by the Viterbi algorithm is performed by selecting the survivor path most likely among the survivor paths maintained by each state and tracing back.
As shown in FIG. 3, the lattice decoder based on the Viterbi algorithm includes a branch metric calculating section 21 for calculating a branch metric of a reference value of each branch of a lattice diagram, An add-compare-select (ACS) arithmetic unit 23 for selecting a survivor path in each state and computing a state value of the survivor path (state metric) A normalization arithmetic unit 24 for subtracting a similar value, a state metric memory 25 for storing a state value, a maximum likelihood detection unit 25 for detecting the most probable survivor path among the survivor paths in each state, A path memory 27 for storing information on survivor paths in each state, and a maximum likelihood value detecting device 26 for outputting the values of the maximum likelihood value detecting device 26, Trace back to perform tracking Unit (28).
The back tracking device 28 is composed of a path storage device, a multiplexer, and a register, which are storage devices for storing a survivor path as much as the depth of the crystal, and the size of the register is K (constraint length) -1, and the size of the path storage device is M (= 2 K-1 ) * L (crystal depth), and an M: 1 multiplexer is required.
The backtracking by the backtracking device of the lattice decoder having such a configuration is executed by using the survivor path information at each previously stored time unit.
That is, the state at the time unit j m j = a survivor information of j b j s mj one time, the state of the former from the state of the time unit j-1 present on the survivor path m j-1 = a j-1 b j-1 becomes m j-1 = b j s mj . In this case, since it is known from the structure of the convolutional encoder that b j = a j-1, s mj = b j-1 , decoding detects a state having a minimum value every unit of time, The entire state is determined using the survivor path information stored in the device, and this process is repeatedly executed by a decision depth (hereinafter referred to as " L ").
Meanwhile, in the ATSC 8VSB mode, 12-symbol intra-segment interleaving is adopted at the transmitter side in preparation for NTSC co-channel interference.
FIG. 4 is a structure of a trellis code interleaver used in the ATSC 8VSB mode, and Table 1 below shows an output of a trellis code interleaver.
<Table 1>
4 includes an input stage 31 for receiving interleaver data, an output stage 33 for arranging and outputting the lattice-encoded data and the precoded data in an appropriate manner, and an input stage 31 and an output stage 33 And a lattice coder 32 composed of twelve lattice encoders and pre-coder having the same structure.
In the above, the twelve lattice coder and the precoder each denote the first through twelfth lattice encoders and the precoder in the order of 32a - 32l from top to bottom.
In the lattice-coding interleaver configured as described above, the data in units of bytes output from the convolutional interleaver is processed in units of bytes by each of the 12 convolutional encoders. Each byte unit data generates 4 symbols of coded data through one encoder. The symbol data input to the convolutional encoder is input two bits from the most significant bit (MSB). Since data of each byte unit is encoded through one convolutional encoder, 12-byte data is required to be encoded through 12 convolutional encoders.
One segment consists of 828 symbols, that is, 207 bytes of data. Since this is not a multiple of 12, conversion is performed in units of 4 segments (828 = 12 * 69 bytes) in order to convert byte data into symbol data. The first symbol 7,6 of the first byte data in the field is coded through a first lattice coder and a pre-coder 32a, and the first symbol 7,6 of the second byte is coded through a second lattice coder And the pre-coder 32b, and the first symbol 7,6 of the 12th byte is coded through the 12th lattice coder and the pre-coder 32l. The second symbol 5,4 of the first byte in the segment is encoded through the first trellis encoder and pre-coder 32a and the second symbol 5,4 of the second byte is encoded through the first trellis encoder and the pre- 32b, each byte data is coded on a symbol-by-symbol basis.
In the segment synchronous signal section, the four encoders corresponding to the synchronous signal section do not output the encoded symbol data because the symbol data is not input. The four symbol data are delayed for 12 periods and then input to the respective encoders and encoded. Therefore, as shown in Table 1, in the first segment of each field, symbol data encoded in the normal order from the first lattice coder and the pre-coder 32a to the twelfth lattice coder and the pre-coder 321 are output In the second segment, the symbol data from the fourth lattice coder and the pre-coder 32d to the twelfth lattice coder and the precoder 321 are output first, and then the third lattice coder and the pre-coder 32a receive the third And the coded symbol data up to the lattice coder and the precoder 32c are output. In the third segment, the eighth lattice coder and the pre-coder 32h are transmitted from the ninth trellis encoder and pre-coder 32i to the twelfth lattice encoder and the pre-coder 32l, and then from the first lattice encoder and the pre- Coded symbol data are output. The data symbol after repeating the 3-segment pattern in the field and inserting the data segment sync signal causes the distance of 12 symbols to fall.
Table 2 below shows the order of multiplexing of byte-symbol conversion and lattice coder.
5 is a lattice-coding deinterleaver which includes a data input terminal 41 for inputting quantized and phase-corrected coded data, a data output terminal 43 for outputting lattice-decoded data, And 12 lattice decoders 42 provided between the data output terminals 43 and having the same structure.
In the above, the twelve lattice decoders 42 denote the first to twelfth lattice decoders in the order from the top to the bottom in the order of 42a to 42l
Here, each lattice decoder has the same structure as that of Fig. 3, and its functions and actions are the same.
Each of the lattice decoders operates as a symbol clock, receives symbol data of a decision depth L, and outputs one byte of decoded data every four symbol clocks.
The operation of the trellis code deinterleaver configured as described above is as follows.
The symbol data of the first segment in the received field is input to the first trellis decoder 42a, the second symbol data is input to the second trellis decoder 42b, and the 12th symbol data is input to the twelfth trellis decoder 421 And decoded.
(12, 24, 36, ...), (12, 24, 36, ...). Since no data is input to the four lattice decoders corresponding to the input sequence in the segment synchronous signal period, the output of the lattice decoder outputs invalid data irrelevant to normal decoding. Here, symbol data after 12 clocks are respectively input to four lattice decoders corresponding to the segment sync signal interval and decoded.
In the above Table 2, the last symbol data of the 0th segment is input to the 12th lattice decoder and decoded, but the 1st symbol data of the 1st segment is input to the 5th lattice decoder rather than the 1st lattice decoder and decoded. That is, the decoding order is (# 4, # 5, ..., # 11, # 0, ..., # 3) on the basis of the lattice decoder in the first segment. This is because a segment sync signal of a 4-symbol clock amount is inserted between the last symbol data of the 0-th segment and the first symbol data of the 1-th segment. (# 0, # 1, ..., # 9, ..., # 7) in the order of the grid decoder in the second segment, ., # 11).
The order of the output byte data of the trellis code deinterleaver shown in Fig. 5 and the order of the byte data input to the lattice-symbol interleaver on the transmitter side do not coincide with each other, because the order of the decoders used for each segment changes by 4 units do.
Therefore, it is necessary to rearrange the decoded data output from the trellis code deinterleaver. In order to solve this problem, as shown in Table 2, the byte-symbol conversion and the multiplexing of the lattice coder are performed in units of four segments, that is, in units of 828 bytes. Therefore, a single- port RAM) to store the decoded data in the memory, and when reading the stored data from the memory, the read address generation is controlled to rearrange the decoded data.
Therefore, conventionally, in order to rearrange the decoded data output from the lattice decoder, two single-port RAMs each having a capacity of 828 bytes and a separate complicated read address generating circuit for generating a read address for controlling the two single- It is disadvantageous in that the configuration of the apparatus is complicated and the chip size is relatively large.
SUMMARY OF THE INVENTION Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art,
The present invention relates to an apparatus and method for decoding decoded data output from a Trellis Decoder for a Grand Alliance (hereinafter abbreviated as "GA") 8 VSB (Vesigital Side band) using a Viterbi decoding algorithm Which is output from a lattice decoder that rearranges the decoded data efficiently.
Technical Solution According to an aspect of the present invention,
A plurality of mode control signals for rearranging a delay control signal for delaying decoded data output from each lattice decoder in a lattice-coding deinterleaver for decoding data encoded by a lattice encoder on the transmission side and delayed decoded data, A control signal generating means for generating a control signal;
Data delay means for delaying the decoded data output from each of the lattice decoders in accordance with the delay control signal generated by the control signal generating means;
And data rearrangement means for rearranging a plurality of decoded data output from the data delay means according to a mode control signal selectively generated by the control signal generation means.
The control signal generating means generates the delay control signal and the mode control signal using a counter that increases in byte clock units.
The control signal generating means generates a delay control signal to be activated once every 12-byte clock.
The control signal generating means divides the 12-byte data into 4-byte units and sets them to 0, 1, and 2, respectively, and sets the first to third mode control signals .
Also, the first mode control signal is a control signal generated so that the order of 4-byte data is 0, 1, 2.
Also, the second mode control signal is a control signal generated so that the arrangement order of the 4-byte data is 1, 0, and 0, respectively.
Also, the third mode control signal is a control signal generated so that the arrangement order of the 4-byte data is 2,0,1.
The data delay means is characterized in that the first to twelfth delayers for delaying the decoded data outputted from the respective lattice decoders are arranged in parallel in accordance with the delay control signal outputted from the control signal generating means.
The data rearrangement means rearranges the decoded data output from each of the delay units in the data delay means in units of 4 bytes according to the first to third mode control signals selectively output by the control signal generation means And a data multiplexer for outputting the data.
1 is a block diagram of a general convolutional encoder,
FIG. 2 is a lattice diagram according to the convolutional encoder of FIG. 1,
FIG. 3 is a block diagram of a lattice decoder using a general Viterbi decoding algorithm.
FIG. 4 is a schematic configuration diagram of a lattice-coding interleaver having a plurality of lattice coders,
FIG. 5 is a schematic configuration diagram of a trellis code deinterleaver having a plurality of grating decoders,
6 is a block diagram of a decoded data rearranging device output from a lattice decoder according to the present invention;
7 is a diagram showing a relationship between a counter and a control signal for rearranging decoded data in the present invention.
Description of the Related Art
100: control signal generator
200: Data delay unit
201 to 212: first to twelfth delayers
300: Data rearrangement unit
310: Data multiplexer
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
6 is a block diagram of a decoded data rearranging device according to the present invention.
As shown in the figure, a delay control signal for delaying decoded data output from each lattice decoder in a trellis decoder in a trellis code deinterleaver for decoding data coded by a lattice encoder on the transmission side, and a delay control signal for rearranging the delayed decoded data A control signal generator (100) for selectively generating a plurality of mode control signals; A data delay unit (200) for delaying decoded data output from each of the lattice decoders according to a delay control signal generated by the control signal generator (100); And a data rearrangement unit 300 for rearranging a plurality of decoded data output from the data delay unit 200 according to a mode control signal selectively generated by the control signal generation unit 100.
The control signal generator 100 generates the delay control signal and the mode control signal using a counter that increases in byte clock units.
In addition, the control signal generator 100 generates a delay control signal to be activated once every 12-byte clock.
The control signal generator 100 divides the 12-byte data into 4-byte units and sets the 0-byte, 1-bit, and 2-byte data, respectively, And generates a control signal.
Also, the first mode control signal is a control signal generated so that the order of 4-byte data is 0, 1, 2.
Also, the second mode control signal is a control signal generated so that the arrangement order of the 4-byte data is 1, 0, and 0, respectively.
Also, the third mode control signal is a control signal generated so that the arrangement order of the 4-byte data is 2,0,1.
The data delay unit 200 includes first to twelfth delay units 201 to 212 for delaying decoded data output from the respective lattice decoders according to a delay control signal output from the control signal generation unit 100, ) Are arranged in parallel.
The data rearrangement unit 300 further includes delay units 201 through 212 in the data delay unit 200 according to first through third mode control signals selectively output from the control signal generation unit 100, And a data multiplexer 310 for rearranging and outputting the decoded data, which are respectively output in the 4-byte unit.
The decoded data rearranging apparatus according to the present invention thus configured generates a delay control signal and a mode control signal using a counter (not shown in the figure) that increments in byte clock units in the control signal generator 100 . The first to twelfth delay units 201 to 212 in the data delay unit 200 delay the decoded data output from each of the lattice decoders in the trellis code deinterleaver according to the delay control signal. The data rearrangement unit 300 rearranges a plurality of pieces of decoded data in units of bytes output from the data delay unit 200 according to a mode control signal output from the control signal generation unit 100, And outputs decoded data.
Hereinafter, the operation of the decoded data rearranging apparatus according to the present invention will be described in more detail.
5, the format of the decoded data is as shown in Table 3 when the decision depth for determining the back tracking specification in each lattice decoder constituting the trellis code deinterleaver is L = 22.
<Table 3>
In general, the 1 segment 832 symbol is 208 bytes, which consists of 1 byte of data segment sync signal and 207 bytes of data. Therefore, since the convolutional encoding on the transmitting side is performed in units of four segments of 828 bytes, the decoded data format is repeated in units of four segments as shown in Table 3 above.
In Table 3, the digits indicate the positions in units of bytes in the segment. Decoded data of 12 bytes are output from the 12 lattice decoders of Fig. 5 during 12 clocks from the position to the byte clock unit. In other words, the decoded data in the 0th segment is divided into byte positions (4, 5, 6, ..., 15), (16, 17, 18, ..., 27), ..., (196, 197, ., 207 output decoded data of 12 bytes each in byte clock. In Table 3, interval_1 indicates a section requiring decoded data to be rearranged in a segment in which the decoded data output timing in each segment is smaller than 3 * L. This is the result of intra-segment interleaving on the transmitting side as described above. When 12-byte data are divided into 4-byte units and are named 0, 1, and 2, , (2, 0), (1, 0, 0), ..., and is out of order with the data on the transmission side. In addition, the interval_2 corresponds to the data order of the transmission side in the section where the decoded data output timing in each segment is larger than 3 * L.
Since the lattice-code interleaving on the transmitting side is made up of 828 units, the lattice-decoding deinterleaving on the receiving side is also performed in units of 828 bytes.
On the other hand, the order of the output byte data of the trellis code deinterleaver as shown in FIG. 5 and the order of the byte data input to the lattice-symbol interleaver on the transmitter side coincide with each other, It is necessary to rearrange the decoded data output from the trellis code deinterleaver. For this purpose, the present invention performs rearrangement of the decoded data using twelve delay elements as shown in FIG.
That is, the control signal generator 100 generates a delay control signal to be activated once every 12-byte clock and transmits the generated delay control signal to the data delay unit 200. That is, as shown in FIG. 7, by performing counting in units of bytes as in (a) using an internal byte counter (not shown in the figure), and when the count value becomes 12 bytes, And activates the signal to a high signal (High).
The data delay unit 200 may be configured to synchronize decoded data output from each of the lattice decoders # 0 to # 11 in the trellis code deinterleaver according to an active delay control signal generated in the control signal generator 100, To the first to twelfth delay units 201 to 212 in synchronization with the byte clock input for the first to twelfth delay units 201 to 212, respectively.
In this case, the first lattice decoder (# 0) in the trellis code deinterleaver is connected to the first delay unit 201 and the second lattice decoder (# 1) is connected to the second delay unit 202 in the input / Likewise, the twelfth lattice decoder (# 11) is connected to the lattice decoder and the delay unit in such a manner that input and output are connected to the twelfth delay unit (212).
The control signal generator 100 generates decoded data in units of bytes output from the first to twelfth delay units 201 to 212 by using an internal byte counter C B And generates a mode control signal for re-arranging. That is, the format of the decoded data is repeated in 4-segment units as shown in Table 3, and when divided into 12-byte units, 18, 17, 17, 17 [69 (18 + 17 + 17 + 17 ) * 12 = 828) of the segment mode (S_MODE).
At this time, the mode control signal is as follows.
Dec_sel = (C B + 4 * MODE) 12%
If MODE = if (S_MODE'event) then (MODE + 1)% 3 else MODE
Therefore, when the 12-byte data is divided into units of 4 bytes and designated as 0, 1, and 2, the mode control signal includes a first mode control signal MODE0 for arranging decoded data in order of 0, , A second mode control signal MODE1 for causing the decoded data to be arranged in the order of 1, 2, 0, and a third mode control signal MODE2 for arranging the decoded data in the order of 2, 0, 1 are generated .
The first to third mode control signals MODE0 to MODE2 are selectively transmitted from the control signal generator 100 to the receiving side after being encoded by the transmission side lattice coder, And the data is transferred to the data rearrangement unit 300.
The data rearrangement unit 300 may delay the first to the twelfth delay units in the data delay unit 200 according to the first to third mode control signals MODE0 to MODE2 selectively generated by the control signal generation unit 100, The decoded data in units of bytes output from the units 201 to 212 are rearranged and output.
That is, the 12-byte decoded data output from the first to the twelfth delay units 201 to 212 are grouped into 4-byte units in the order of the lattice decoders and set as one unit data. For example, each output of the lattice decoder # 0 to the lattice decoder # 3 is grouped into one unit data, which is referred to as 0 as described above. Similarly, each output of the lattice decoder # 4-lattice decoder # 7 is grouped into one unit data, which is denoted by 1. Further, each output of the lattice-decoder # 8-lattice decoder # 11 is grouped into one unit, which is denoted by 2 as one unit data.
In this manner, 12-byte data is converted into 0, 1, and 2-byte data of 4-byte units, and the order of 0, 1, and 2 data of the 4-byte unit in accordance with the mode control signal generated in the control signal generation unit 100 is Rearranged and delivered to the rear end.
As described above, according to the present invention, it is possible to easily rearrange data decoded by a lattice decoder in a Forward Error Correction Decoder of an ATSC 8VSB receiving system without using a single port RAM (SRAM) It is possible to reduce the chip size of the error corrector and also to test the forward error corrector.
In the conventional SRAM, a complicated control signal generation circuit is indispensably required in order to generate an address generation signal for reading and writing. However, in the present invention, the rearrangement of decoded data is performed using only a simple delay element without using the SRAM The address generation circuit can be eliminated. Therefore, the chip area can be reduced in the hardware implementation, and the error correction capability of the lattice decoder can be maximally improved.
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| KR1019980011313A KR100273092B1 (en) | 1998-03-31 | 1998-03-31 | Device for rearrangement of decoding data |
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| KR1019980011313A KR100273092B1 (en) | 1998-03-31 | 1998-03-31 | Device for rearrangement of decoding data |
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