KR19990075361A - Time error detection method of transceiver - Google Patents

Abstract

A method of detecting a time error of a transmitter and a receiver includes the steps of sequentially receiving a plurality of bits of sampling data; Receiving the sampling data and sequentially storing the sampling data; Reading the first, second and third data according to the input order among the sampling data; Receiving the first, second, and third data, determining a sign of the first and third data, and outputting a result; And outputting time error correction data according to the determined result value.

Description

METHOD FOR DETECTING TIMING ERROR OF TRANSCEIVER

The present invention relates to a transceiver, and more particularly to a time error detection method.

In general, the transceiver or modem technology is phase recovery and symbal timing recovery. In general, the time detection uses Gardner or a similar detection method. The timing detect algorithm proposed by Gardner works independently of the characteristics of the time detector even in the presence of a phase error. That is, the phase locked loop (PLL) and the time locked loop (TLL) operate independently of each other. In other words, even if there is a phase error, the axiom of sin ² x + cos ² x = 1 is applied and the phase error is canceled. As a result, the effect of carrier recovery is neglected, and the time acquisition progresses in parallel with the carrier recovery.

The expression for the time error function u (r) is as follows.

(r) - Q (r) - I (r) = I {r - (1/2)} * - One) ]

Here, I and Q denote I and Q channels in QPSK, respectively, and r denotes an r-th bit. It can be seen that this computation method requires two samples per symbol. The implementation of this method can be implemented by adjusting the sampling point through a digital controlled oscillator (NCO). The filtered QPSK signal containing the phase error [Delta] [theta] for examining the phase independence in QPSK is expressed as follows.

r (t) = {a (t) + jb (t)}

= {a (t) + jb (t)} * {cos?? + sin?

(t) cos ?? - b (t) sin??} + j * {a (t) cos?

. Therefore, when the orthogonal channel component is obtained again,

I (t) = a (t) cos?? - b (t) sin?

Q (t) = a (t) sin?? - b (t) cos?

.

When this equation is solved by substituting it into the timing error equation defined at the beginning,

a (t) - a (t - 1)} cos (cos [iota] (T) - b (t) - b (t - 1)} sin [Delta] (t-1)} cds △ θ], and if this is solved again,

= A {t - (1/2) } * {a (t) - a (t - 1)} cos 2 △ θ + b {t - (1/2)} * {b (t) - b (t - 1)} sin ² ??

+ a {t - (1/2)} * {a (t) - a (t - 1)} sin ² ?? - 1)} cos ² ??

+ b {t - (1/2)} * {b (t) - b (t) (t - 1)} sin △ θ cos △ θ - a {t - (½)} * {a } * {b (t) - b (t - 1)} sin?? cos?

In the above equation, the third and fourth lines are canceled each other, and the first and second lines are arranged as shown in the following equation by using the axiom of sin ² x + cos ² x = 1.

b (t) - b (t - 1)} + b {t - (1/2)

In conclusion, in the above equation, the phase error Δθ is canceled and is not reflected in the output of the detector at all. Therefore, even if synchronization is not performed, this time detection and calculation method operates independently. That is, the carrier recovery (CR) and the code time recovery (STR) can be performed simultaneously at the same time, thereby achieving quick synchronization. The above formula shows that two multiplication circuits, two subtraction circuits, and one addition circuit are needed. In fact, most of the time detection circuits use only one channel in order to reduce the size of the hardware, even though the independence of CR and CR is degraded. Therefore, a {t - (1/2)} * {a (t) - a (t - 1)} is used in the above conclusion.

However, the addition of the multiplication circuit still increases the size of the hardware, and then the ROM table method is used. This method is a method of obtaining an appropriate error value by addressing a peak value and a trans value inputted into the input. However, this method also causes a problem that the size of the hardware is large and the speed is slow.

It is therefore an object of the present invention to provide a time error detection method that can reduce the size of hardware and thus increase the speed of time error detection.

1 is a flowchart of a time error detection method according to the present invention;

FIG. 2 is a waveform diagram showing a sampled waveform in which no time error has occurred; FIG. And

3 is a waveform diagram showing a sampled waveform in which a time error occurs.

DESCRIPTION OF REFERENCE NUMERALS

10: Sampling data input step 20: Sampling data storage step

30: first, second and third data reading steps

40: first, second and third data code judgment step

50: time error data output step according to the judgment result value

(Configuration)

According to an aspect of the present invention, there is provided a method of detecting a time error of a transceiver, the method comprising: sequentially receiving a plurality of bits of sampling data; Receiving the sampling data and sequentially storing the sampling data; Reading the first, second and third data according to the input order among the sampling data; Receiving the first, second, and third data, determining a sign of the first and third data, and outputting a result; And outputting time error correction data according to the determined result value.

(Action)

In this way, it is possible to reduce the size of the hardware and increase the speed of time error detection.

(Example)

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

1 is a flowchart of a time error detection method according to the present invention.

Referring to FIG. 1, a time error detection method according to the present invention includes a sampling data input step 10, a sampling data storing step 20, a data reading step 30, a data code determination step 40, And a data output step (50). The sampling data input step 10 is a step of converting the analog signal supplied to the input terminal of the receiver into a digital signal and inputting the sampled data. The sampling data storing step 20 is a step in which the sampled data are sequentially stored in a storage circuit. The data reading step 30 is a step of sequentially reading the sampling data stored in the storage circuit. The data code determination step 40 determines the sign of the read data and outputs the result. The time error correction data output step 50 is a step of outputting an error value based on the determination result.

2 is a waveform diagram showing a sampled waveform in which no time error has occurred.

Referring to FIG. 2, the waveform shown in FIG. 2 is a flow of an input signal. When the input signal is input in the order of -1, 1, 1, -1, the signal is sampled twice the simbol rate. The peak values are arranged in the order of -1, 1, 1, -1 according to the input order. From the first peak point (peak 1) and the second peak point (peak 2), it can be seen that the values of the two peak points (peak 1 and peak 2) are -1 and 1, respectively. At this time, it is assumed that a value sampled in the middle of the peak points peak1 and peak2, that is, a value of the first trans1 is an error. Since the value of the first transformer trans1 located between the peak points peak1 and peak2 is zero, the sampled position is correct and the error value becomes zero.

The second peak point peak 2 and the third peak point peak 3 are different from each other between the second peak point peak 2 and the third peak point peak 3, It is determined whether or not the codes are different from each other. In the case of the peak points (peak2 and peak3), since the sign is positive, the value of the second trans (trans2) is not meaningful. That is, the value of the second trans (trans2) does not help the time error detection. It is determined whether the signs of the peak points (peak 3 and peak 4) are different between the third peak point (peak 3) and the fourth peak point (peak 4). In the case of the peak points (peak 3 and peak 4), since the value of the third peak (peak 3) is 1 and the value of the fourth peak point (peak 4) is -1, Lt; / RTI > However, since the value of the third trans (trans3) located between the peak points (peak3 and peak4) is zero, the sampled position is correct and the error value becomes zero.

3 is a waveform diagram showing a sampled waveform in which a time error occurs.

Referring to FIG. 3, FIG. 3 shows a waveform in which the sampling time of input signals is delayed. The value of the first peak point PeK1 is negative and the value of the second peak point PeK2 is positive in the values of the peak points PeK1 and PeK2. At this time, the value of the first trans (trans1) is a time error value. Since the value of the first trans (trans1) is positive and the value of the second peak point (peak2) is also positive, the signal is input with a delayed sampling time. Therefore, a value obtained by multiplying the value of the first trans 1 by -1 is a time error value.

The value of the third peak point (peak 3) is positive and the value of the fourth peak point (peak 4) is negative in the values of the peak points (peak 3 and peak 4). At this time, the value of the third trans (trans3) is a time error value. At this time, since the value of the third transformer (trans3) is negative, a value obtained by multiplying the value of the third transformer (trans3) by -1 is a time error value.

Hereinafter, the time error detection method of the present invention will be described with reference to FIGS. 1 to 3. FIG.

1 to 3, the time error detecting method of the present invention includes a sampling data input step 10, a sampling data storing step 20, a data reading step 30, a data code judging step 40, And an error correction data output step (50). The sampling data input step 10 is a step of converting the analog signal supplied to the input terminal of the receiver into a digital signal and inputting the sampled data. The sampling data storing step 20 is a step in which the sampled first, second, and third data are sequentially stored in a storage circuit. For example, when 6-bit sampling data is input, the first, second, and third sampling data are sequentially stored in the storage circuit and sequentially output.

The data reading step 30 sequentially reads the sampled first, second, and third data sequentially stored in the storage circuit. That is, the step of reading out the first, second, and third data stored in the sampling data storing step 20 in the stored order and outputting the data to the data code determining step 40. The data code determination step 40 determines the sign of the read first, second, and third data, and outputs the result. For example, as shown in FIG. 3, the first data, that is, the value of the first peak point (peak 1) is compared with the third data, that is, the value of the third peak point (peak 3) (trans) as a time error value and outputs the result.

The time error correction data output step 50 is a step of outputting an error value based on the determination result. For example, when the value of the first peak point (peak 1) is negative and the value of the second peak point (peak 2) is positive, the first trans value is positive, The first trans value is multiplied by -1 and output. When the value of the second peak point (peak 2) is positive and the value of the third peak point (peak 3) is negative, the second trans value is negative, Multiply the trans value by -1. Since the value of the second peak point (peak 2) and the value of the third peak point (peak 3) are positive, the value of the second trans is ignored. That is, 0 is output.

In this manner, time errors occurring upon input can be detected using the sign and trans points of peak peaks of the input sampling data.

As described above, by using a method of detecting a time error occurring at the time of input using the sign and trans points of peak peaks of input sampling data, it is possible to reduce the size of the hardware, Speed can be improved.

Claims (1)

A time error detection method for a transceiver comprising: Sequentially receiving a plurality of bits of sampling data; Receiving the sampling data and sequentially storing the sampling data; Reading the first, second and third data according to the input order among the sampling data; Receiving the first, second, and third data, determining a sign of the first and third data, and outputting a result; And outputting time error correction data according to the determined result value.