KR19990074900A - Inductor of semiconductor device and manufacturing method thereof - Google Patents

Abstract

The present invention relates to an inductor of a semiconductor device and a method of manufacturing the same. For this purpose, a conductive layer is filled in the trench formed in the substrate and used as an inductor. As a result, the series resistance of the inductor can be reduced by making the cross sectional area wider than that of the conductive layer having the same planar layout, and therefore, the queue factor of the inductor can be prevented from lowering. The trenches are formed within the shortest distance within the resolution of the design rule and the exposure apparatus to increase the integration degree of the semiconductor device. Therefore, the distance between the conductive layers filling the trench also becomes the most recent distance, thereby increasing the inductor capacity. Furthermore, since the cavity is formed around the trench, the possibility of forming a parasitic capacitor between the substrate and the inductor conductive layer is extremely low. Even if parasitic capacitors are formed, the air permittivity is very low, so the capacitance of the parasitic capacitors is low. Therefore, it is possible to prevent the capacity of the inductor from being lowered due to dielectric loss and the self-resonance frequency of the inductor from lowering. In addition, when the inductor having the above-described structure is applied to the transmission line, the delay time RC of the transmission line is shortened because the capacitance C of the parasitic capacitor becomes very low.

Description

Inductor of semiconductor device and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an inductor of a semiconductor device having a high Q-factor, a self resonant frequency, and a large inductance, and a method of manufacturing the same.

To date, most monolithic microwave integrated circuits (hereinafter referred to as MMICs) are constructed using gallium arsenide (GaAs) substrates. However, as semiconductor devices have been highly integrated, much attention has been paid to MMIC configurations using silicon substrates.

Silicon substrates have higher conductivity than arsenic gallium substrates. Thus, it is difficult to fabricate MMIC components such as inductors or transmission lines with desired performance on silicon substrates. In particular, the inductor generates aluminum loss due to the formation of a parasitic capacitor formed between the silicon substrate and the conductive layer forming the inductor, has a low resonance frequency, and has a lower conductivity than gold (Au) used in gallium arsenide substrates. The use of the metal layer causes a problem of lowering the cue-factor. In addition, the fact that the inductor occupies a large area in the layout is also an obstacle to implementing the MMIC using a silicon substrate.

However, on-chip inductors have many advantages over off-chip inductors, such as easier design of low power circuits and improved noise characteristics by active devices. Accordingly, various prior arts for implementing an on-chip inductor using a silicon substrate from which the above-mentioned problem is eliminated have been proposed.

1 is a silicon oxide film (SiO ₂ ) 14 having a first metal layer 12 formed on a substrate 10 having a high resistance and having a via hole 20 thereon as one of the related arts. ), A nitride film (Si ₃ N ₄ ) 16 and a SiON (18) film are sequentially formed, and the second metal layer 22 connected to the first metal layer through the via hole 20 on the SiON film 18. (See IEEE J. Solid-State Circuits, vol. 31, no 1, pp. 4-9, 1996, "High Q Inductors for Wireless Applications in a Complementary Silicon Bipolar Process"). ).

In addition, referring to FIG. 2, in the inductor according to the related art, an interlayer insulating film 26 is formed on a silicon substrate 24, and the first to third metal layers 28, 30, and 32 are formed on the interlayer insulating film 26. The first and second via holes V1 and V2 are formed between the first and third metal layers 28, 30, and 32. In addition, a fourth metal layer 34 is formed on the interlayer insulating layer 26. The fourth metal layer 34 is connected to the third metal layer 32 through a third via hole V3 formed on the third metal layer 32. Although the multi-layered metal layer forms wires in various places in the interlayer insulating film 26, the first metal layer 28 is connected to only one wire. The remaining wirings have a multi-layered structure with only the second to fourth metal layers 30, 32, and 34 without being in contact with the first metal layer 28 (IEEE Trans. Microwave Theory Tech., Vol. 44, no. 1, pp. 100-104, 1996, "Microwave Inductors and Capacitors in Standard Multilevel Interconnect Silicon Technology").

3 illustrates a polyimide layer 35 having a first metal layer 33 formed on a substrate 31 and including a via hole 37 exposing the first metal layer 33 on the entire surface of the resultant material 31. Is formed, and the inductor according to the prior art is formed on the polyimide film 35, the second metal layer 39 in contact with the first metal layer 33 (IEDM tech. Dig., Pp 717-720, 1995, "Monolithic Planar RF Inductor and Waveguide Structures on Silicon with Performance Comparable to those in GaAs MMIC,".

The inductors according to the related art described above with reference to FIGS. 1 to 3 are limited in narrowing the distance between the inductor metal layers. Therefore, there is a problem that it is difficult to obtain a large inductance in common.

Therefore, the technical problem to be achieved by the present invention is to reduce the spacing between the conductive layer patterns constituting the inductor, to widen the cross-sectional area of the conductive layer pattern, and to prevent the formation of parasitic capacitors in the periphery. An inductor exhibiting inductance characteristics is provided.

Another object of the present invention is to provide a preferred method of manufacturing the inductor.

1 to 3 are cross-sectional views of inductors according to the prior art, respectively.

4 is a plan view of a passive inductor having a high Q-factor and a self resonant frequency according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view of FIG. 4 taken in a 5-5 'direction.

6 through 9 are cross-sectional views illustrating a method of manufacturing a passive inductor having a high Q-factor and a self resonant frequency according to an embodiment of the present invention.

10 is a plan view of an inductor according to a second embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line 11-11 ′ of FIG. 10.

12 to 17 are diagrams showing step-by-step method of manufacturing the inductor according to the second embodiment of the present invention.

* Description of Signs of Major Parts of Drawings *

40, 60: substrate. 42, 66a: trench.

44, 62: first insulating film. 48, 70: second insulating film.

46a, 46b, 72: First conductive layer pattern.

52, 84a, 84b: second conductive layer pattern. 50, 82: beer hole.

54, 88: contact hall. 56, 90: cavity.

70, 74, 76, 78, 86a: second to sixth insulating films.

In order to achieve the above technical problem, an inductor of a semiconductor device according to the present invention includes a substrate on which a trench is formed, a first insulating film formed on the front surface of the substrate, and a first conductive layer filling the trench formed on the first insulating film. A second pattern formed on the entire surface of the resultant pattern, on which the first and second patterns including a pattern, a second pattern of the first conductive layer formed on the first insulating layer between the first pattern, and a via hole exposing the second pattern are formed An insulating film, a second conductive layer pattern filling the via hole formed on the second insulating film, a contact hole exposing the substrate formed between the first pattern and the second pattern, and a cavity around the trench of the substrate; .

Here, the substrate is any one selected from the group consisting of a silicon substrate, a glass substrate, and a silicon on insulator (SOI) substrate.

The inclination angle of the trench inner wall is about 1 ° to about 90 °.

The first and second insulating layers are silicon oxide films, and the first and second conductive layer patterns are aluminum layer patterns.

In addition, in order to achieve the above technical problem, the present invention is a substrate, a lower insulating film formed on the substrate, a first conductive layer pattern formed on the lower insulating film, the first conductive layer having a via hole on the first conductive layer pattern An insulating film surrounding the pattern, a second conductive layer pattern formed on the first conductive layer pattern and the lower insulating film, and formed on an entire surface of the side surface and the upper surface of the second conductive layer pattern, and a hole is formed between the second conductive layer pattern An inductor of a semiconductor device having an upper insulating film having a cavity and a cavity between the upper insulating film surrounding the second conductive layer pattern and the insulating film is provided.

In the inductor, the substrate is any one selected from the group consisting of a silicon substrate, a glass substrate, and an SOI substrate.

The lower insulating film is formed of a trench oxide film formed on the substrate and a silicon oxide film formed on an entire surface of the substrate and the trench oxide film. The upper insulating film is a silicon oxide film.

In order to achieve the above another technical problem, an inductor manufacturing method according to the present invention is as follows.

(a) A trench is formed in the semiconductor substrate. (b) A first insulating film is formed on the entire surface of the semiconductor substrate on which the trench is formed. (c) A second pattern of a first conductive layer is formed on the first insulating layer between the first pattern of the first conductive layer filling the trench and the first pattern on the first insulating layer. (d) forming a second insulating film on the entire surface of the product of step (c). (e) A via hole for exposing the second pattern is formed in the second insulating layer. (f) A second conductive layer pattern filling the via hole is formed on the second insulating layer pattern. (g) forming a cavity around the trench.

In this process, the trench is formed such that the inclination angle of the inner wall is 1 ° to 90 °.

The substrate uses any one selected from a silicon substrate, a glass substrate, and an SOI substrate.

Step (g) may be further subdivided as follows.

That is, (g1) a contact hole for exposing the substrate is formed between the first pattern and the second pattern. (g2) The exposed substrate is isotropically etched through the contact hole.

In this case, SF ₆ is used as an emitter in the isotropic etching.

In order to achieve the above another technical problem, another inductor manufacturing method according to the present invention is as follows.

(a) A trench type insulating film is formed on the substrate. (b) A lower insulating film is formed over the substrate and the trench insulating film. (c) A first conductive layer pattern is formed on the lower insulating film formed on the trench type insulating film. (d) An intermediate insulating film is formed on the first conductive layer pattern and the lower insulating film. (e) The intermediate insulating layer is patterned to form an intermediate insulating layer pattern on the via hole exposing the first conductive layer pattern and the trench type insulating layer. (f) forming a second conductive layer pattern exposing the intermediate insulating film and filling the via hole on the resultant from which the insulating film formed on the top of the intermediate insulating film is removed. (g) A cavity is formed around the first and second conductive layer patterns.

In this process, step (a) may be subdivided as follows.

That is, (a1) a first insulating film is formed over the entire surface of the substrate. (a2) A photosensitive film pattern defining a plurality of trench formation regions is formed on the first insulating film. (a3) A plurality of trenches are formed in a predetermined region of the substrate by using the photoresist pattern as an etching mask. (a4) After removing the photoresist pattern, the substrate on which the plurality of trenches are formed is oxidized.

In addition, step (d) includes sequentially forming third to fifth insulating layers on the first conductive layer pattern and the lower insulating layer.

The lower insulating film is a planarizing second insulating film formed on the entire surface of the product of step (a4).

Step (g) can be subdivided as follows.

That is, (g1) an upper insulating film having a contact hole is formed on the fifth insulating film on the entire surface of the resultant product on which the second conductive layer pattern is formed. (g2) The fourth insulating film is removed.

The fourth insulating layer is removed by isotropic etching, but uses hydrofluoric acid (HF) having a higher etching rate with respect to the fourth insulating layer than the third insulating layer. Here, the third and fifth insulating layers may be formed of an insulating layer that is not doped with impurities, such as a silicon oxide layer, and the fourth insulating layer may be formed of an insulating layer that is doped with impurities, such as a silicon oxide layer doped with phosphorus (P).

The present invention fills a trench formed in a substrate with a conductive layer to use as an inductor. Therefore, the series resistance of the inductor can be reduced by making the cross-sectional area wider than that of the conductive layer having the same planar layout. Therefore, the queue factor of the inductor can be prevented from lowering. The trenches are formed within the shortest distance within the resolution of the design rule and the exposure apparatus to increase the integration degree of the semiconductor device. Therefore, the distance between the conductive layers filling the trench also becomes the most recent distance, thereby increasing the inductor capacity. Furthermore, since the cavity is formed around the trench, the possibility of forming a parasitic capacitor between the substrate and the inductor conductive layer is extremely low. Even if parasitic capacitors are formed, the air permittivity is very low, so the capacitance of the parasitic capacitors is low. Therefore, it is possible to prevent the capacity of the inductor from being lowered due to dielectric loss and the self-resonance frequency of the inductor from lowering. In addition, when the inductor having the above-described structure is applied to the transmission line, the delay time RC of the transmission line is shortened because the capacitance C of the parasitic capacitor becomes very low.

Hereinafter, an inductor and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited by the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings like reference numerals refer to like elements. In addition, where a layer is described as being "top" of another layer or substrate, the layer may be directly on top of the other layer or substrate, with a third layer intervening therebetween.

4 is a plan view of an inductor having a high cue factor and a self resonant frequency according to a first embodiment of the present invention, and FIG. 5 is a cross-sectional view of FIG. 4 taken along the 5-5 'direction. 6 to 9 are cross-sectional views illustrating a method of manufacturing an inductor according to a first exemplary embodiment of the present invention.

10 is a plan view of an inductor according to a second exemplary embodiment of the present invention, and FIG. 11 is a cross-sectional view of FIG. 10 taken along the 11-11 ′ direction. 12 to 17 are diagrams showing step by step methods of manufacturing an inductor according to a second exemplary embodiment of the present invention.

First, an inductor according to a first embodiment of the present invention will be described with reference to FIG. 4. In FIG. 4, reference numeral 42 denotes a spiral trench. A first pattern 46a of the first conductive layer filling the trench 42 is formed along the helical trench 42. The first conductive layer is an aluminum layer. The contact region C is provided at the outer start point and the inner end point of the spiral trench 42. The second pattern of the first conductive layer is formed in the contact region C. Reference numeral 52 is a second conductive layer pattern connected to the first pattern 46a of the first conductive layer through the contact region C. One of them is the first lead metal layer and the other is the second lead metal layer. The second metal layer pattern 52 is an aluminum layer. Etch holes 54 are formed at the left and right sides of the trench 42. The etch holes 54 are formed along the helix of the trench 42 from the start point to the end point of the helix.

In order to more clearly know the inductor according to the first embodiment of the present invention and to see a portion not shown in plan view of the inductor, Fig. 4 is cut vertically along the 5-5 'direction. The resulting cross section is FIG. 5.

Referring to FIG. 5, the inclination angle θ of the inner wall of the trench 42 is about 10 ° to about 90 °. The first insulating layer 44 is formed between the first pattern 46a of the first conductive layer filled in the trench 42 and the surface of the trench 42. The first insulating film is a silicon oxide film. The etch hole 54 is formed between the first pattern 46a of the first conductive layer. A second pattern 46b of the first conductive layer, which is not seen in FIG. 4, is formed on the first insulating film between the first patterns 46a of the first conductive layer. As described above, the second pattern 46b is an area in which the second conductive layer pattern 52 is in contact with the first pattern 46a. A second insulating film 48 is formed as an interlayer insulating film between the patterns 46a and 46b of the first conductive layer and the second conductive layer pattern 52. The second insulating film 48 is a silicon oxide film.

On the other hand, as a characteristic of the inductor according to the present invention, a cavity 56 is formed between the substrate 40 and the first insulating film 44 to surround the first pattern 46a of the first conductive layer. The substrate 40 is preferably a silicon substrate, but may be another substrate. For example, the substrate 40 is any one selected from a crowd consisting of a silicon substrate, a glass substrate, and an SOI substrate. The substrate 40 is only in contact with the partial region 58a of the second insulating film 44 formed under the trench 42 bottom 58 and the second pattern 46b of the first conductive layer. . If necessary, there may be an inductor with these contacts removed. That is, there may be an inductor floating from the substrate 40 with the first and second patterns 46a and 46b of the first conductive layer fixed to the first and second insulating layers 44 and 48. have.

Next, the inductor manufacturing method according to the first embodiment of the present invention will be described in detail with reference to FIGS. 6 to 9.

6 is a diagram illustrating a step of forming the first insulating film 44 on the entire surface of the substrate 40. Specifically, the trench 42 is formed in the substrate 40 at a predetermined depth. It is preferable to use a silicon substrate as the substrate 40, but a glass substrate or an SOI substrate may be used. When the trench 42 is formed, the inclination angle θ of the inner wall of the trench 42 is about 10 ° to 90 °. Subsequently, a first insulating film 44 is formed on the entire surface of the substrate 40. The first insulating film 44 is formed of a silicon oxide film (SiO ₂ ).

FIG. 7 is a diagram illustrating a step of forming first and second patterns 46a and 46b of a first conductive layer used as an inductor.

Specifically, a first conductive layer (not shown) filling the trench 42 is formed on the entire surface of the first insulating layer 44. The first conductive layer is formed of an aluminum (Al) layer. A photoresist pattern, for example, a photoresist layer is coated on the first conductive layer and then patterned to define an inductor forming region of the first conductive layer, for example, a region including the trench 42 and a predetermined region therebetween. To form. The entire surface of the first conductive layer is anisotropically etched, for example dry etched, using the photoresist pattern as an etch mask. Subsequently, when the photoresist pattern is ashed and removed, the first pattern 46a and the second pattern 46b of the first conductive layer are formed on the first insulating layer 44. The first pattern 46a is a first conductive layer pattern filling the trench 42 and the second pattern 46b is a first formed on the second insulating layer 44 between the first patterns 46a. It is a conductive layer pattern. The second pattern 46b serves as a contact pad conductive layer pattern as an output terminal of the inductor. That is, the second pattern 46b is a region for contacting the first pattern 46a and the second conductive layer pattern formed in a subsequent process.

8 is a diagram illustrating a step of contacting the first pattern 46a and the second conductive layer pattern 52 of the first conductive layer.

In detail, the second insulating layer 48 is formed on the entire surface of the resultant product in which the first and second patterns 46a and 46b of the first conductive layer are formed. The second insulating film 48 is formed of an oxide film. The second insulating film 48 is used as an interlayer insulating film. A photosensitive film (not shown), such as a photoresist film, is applied to the entire surface of the second insulating film 48. The photoresist is patterned to form a photoresist pattern (not shown) that exposes a portion of the second insulating film 48 formed on the second pattern 46b of the first conductive layer. The exposed portion of the second insulating layer 48 is etched using the photoresist pattern as an etching mask. The photosensitive film pattern is removed and a necessary cleaning step is performed. As a result, a via hole 50 exposing the second pattern 46b of the first conductive layer is formed in the second insulating layer 48. Subsequently, a second conductive layer (not shown) filling the via hole 50 is formed on the entire surface of the second insulating film 48. The second conductive layer is preferably formed of an aluminum layer, but may be formed of another conductive material layer. A photoresist pattern (not shown) may be formed on the second conductive layer to define a region where the via hole 50 is formed and cross any one of the first patterns 46a of the first conductive layer. As a result, the second conductive layer formed on the other side of the first pattern is exposed. The exposed entire surface of the second conductive layer is etched using the photoresist pattern as an etching mask. Subsequently, when the photoresist pattern is removed, the second pattern 46b of the first conductive layer is contacted through the via hole 50 and intersects any one selected from the first pattern 46a of the first conductive layer. A second conductive layer pattern 52 is formed on the second insulating film 48. The second conductive layer pattern 52 is used as a lead metal layer of the inductor formed of the first pattern 46a of the first conductive layer.

9 shows the self resonance frequency of the inductor by forming a cavity 56 around the trench 42 to minimize the formation of parasitic capacitors between the substrate 40 and the first pattern 46a of the first conductive layer. Figure showing the steps to maximize.

Specifically, a photosensitive film is coated on the entire surface of the second conductive layer pattern 52 and the second insulating film 48 and then patterned to form the first pattern 46a of the first conductive layer of the second insulating film 48. And a photosensitive film pattern (not shown) exposing a portion formed between the second pattern 46b and the second pattern 46b. Using the photoresist pattern as an etching mask, the exposed portion of the second insulating film 48 and the first insulating film 44 formed thereunder are continuously etched. The etching is performed until the interface of the substrate 40 is exposed. The photosensitive film pattern is removed. As a result, an etch hole 54 exposing the interface of the substrate 40 is formed between the first pattern 46a and the second pattern 46b of the first conductive layer. Wherein the chihol 54 chyeonteo on the results is formed, the material of the substrate 40, such as high selectivity etching to the silicon substrate and the first insulating film 44, the ratio, and an isotropic etch using, e.g., a SF _6. The isotropic etching is preferably performed until a cavity 56 is completely separated between the first pattern 46a of the first conductive layer and the substrate 40. However, as shown in FIG. 9, the bottom 58 of the first pattern 46a of the first conductive layer and the first patterns 46a and 46b of the first conductive layer may be used to support the first and second patterns 46a and 46b of the first conductive layer. The isotropic etching may be performed to such an extent that the contact with the first insulating film 44 formed on the bottom 58a of the second pattern 46b is left. As a result of the isotropic etching, a cavity 56 in which all or part of the substrate 40 is removed is formed around the first and second patterns 46a and 46b of the first conductive layer, and the air is formed in the cavity 56. Is filled. As such, the first and second patterns 46a and 46b and the substrate may be formed by forming a cavity 56 around the first and second patterns 46a and 46b of the first conductive layer used as an inductor. It is possible to minimize the formation of parasitic capacitors between the 40, and to minimize the capacitance even if the parasitic capacitor is formed. Therefore, the resonance frequency in the circuit which consists of an inductor and a capacitor (parasitics) can be maximized.

Next, an inductor and a method of manufacturing the same according to the second embodiment of the present invention will be described. In this process, when the member is the same as the member of the first embodiment, the member is indicated by the reference numeral used in the first embodiment.

First, the inductor according to the second embodiment will be described. The inductor according to the second embodiment is provided below the conductive layer pattern in which the lead metal layer is used as the inductor as opposed to the inductor according to the first embodiment.

Referring to FIG. 10, reference numerals 72 and 72a denote first conductive layer patterns, 72 denotes a first lead metal layer, and 72a denotes a second lead metal layer. The first conductive layer patterns 72 and 72a are aluminum layers. Reference numeral C denotes contact regions of the first and second lead metal layers 72 and 72a. Although not shown in FIG. 10, the contact region C has a first pattern of a second conductive layer. The second conductive layer is an aluminum layer. Reference numeral 84b denotes a second pattern of the second conductive layer formed spirally. Both the outer start point and the inner end point of the second pattern 84b are in contact with the first pattern existing in the contact region C. Reference numeral 86a denotes an insulating film, for example, a silicon oxide film, formed on the entire surface of the second pattern 84b of the second conductive layer. Further, reference numeral 88 is a contact hole formed in the insulating film 86a on both sides of the second pattern 84b of the second conductive layer. The contact hole 88 is formed from the start point to the end point along the helix of the second pattern 84b.

FIG. 11 is a cross-sectional view of a portion of FIG. 10 taken in the 11-11 ′ direction. 11 shows only the second lead metal layer 72 among the first and second lead metal layers 72 and 72a.

Referring to FIG. 11, the entire surface of the second lead metal layer 72 is covered with an insulating layer 74a except for the contact with the second pattern 84b of the second conductive layer. The insulating film 74a covering the second lead metal layer 72 is a silicon oxide film. The second lead metal layer 72 is formed on the lower insulating film 68 formed on the substrate 60. The lower insulating film 68 is a thick insulating film filling a trench (not shown) of the substrate 60, that is, a trench insulating film 68 and a planarizing insulating film formed on the substrate 60 and the trench insulating film 68. It consists of. However, the planarization insulating film is the same insulating material film as the trench insulating film 68. Therefore, it is not distinguished from the trench insulating film 68 in the drawings. The trench insulating film 68 is a silicon oxide film. Preferably, the substrate 60 is a silicon substrate, but another insulating layer may be further provided on the substrate 60. Therefore, the substrate 60 is any one selected from the group consisting of a silicon substrate, a glass substrate, and an SOI substrate.

On the other hand, the second pattern 84a of the second conductive layer is covered with the insulating film 86a on the side surface and the entire upper surface. This insulating film 86a is a silicon oxide film and is an upper insulating film with respect to the lower insulating films 68 and 70. An etch hole 88 is provided between the second patterns 84a. The first pattern 84a of the second conductive layer is in contact with the first and second lead metal layers 72 and 72a, but the second pattern 84b is not in contact with any of the following. not. That is, in FIG. 10, all parts from the start point to the end point of the second pattern 84b are floating in the air. However, the second pattern 84b is fixed to the insulating film 86a formed on the side surfaces and the entire upper surface thereof. In other words, the cavity 90 is formed between the lower region and the remaining region except for the portion in contact with the contact region C of the second conductive layer. When air flows into the cavity 90 through the etch hole 88, an air layer is formed between the second conductive layer and the lower layer. As such, the first and second patterns 84a and 84b of the second conductive layer may be formed by the substrate 90 due to the cavity 90 and the thick insulating layer 86 formed on the substrate 60. The possibility of forming a parasitic capacitor between 60) and the second conductive layer pattern is very low. Although a parasitic capacitor is provided between the second conductive layer pattern and the substrate 60, the capacitance is very small. As a result, the inductor of the above type has an inductor capable of reducing dielectric losses due to a conductive substrate having a very high self-resonant frequency and a short transmission line delay time (RC, R for DC resistance, and C for capacitance). do.

An inductor manufacturing method according to the second embodiment will be described with reference to FIGS. 12 to 17.

12 and 13 illustrate the steps of forming the lower insulating layers 68 and 70. 12 illustrates forming a trench insulating layer 68 among the lower insulating layers 68 and 70, and FIG. 13 illustrates forming a second insulating layer 70 among the lower insulating layers 68 and 70.

Referring to FIG. 12, a first insulating layer 62 is formed on the substrate 60. The first insulating film 62 is a silicon oxide film. Although it is preferable to use a silicon substrate as the substrate 60, any one selected from the group consisting of a glass substrate or a substrate in which a separate insulating film is further formed on the substrate 60 and an SOI substrate may be used. A first photosensitive film (not shown), for example, a first photoresist film is coated on the entire surface of the first insulating film 62. The first photoresist layer is patterned to form a first photoresist layer pattern 64 that exposes a predetermined region of the first insulating layer 62 into a plurality of regions having a predetermined size. Using the first photoresist layer pattern 64 as an etching mask, the exposed portions of the first insulating layer 62 and the substrate 60 below are anisotropically etched. The anisotropic etching is performed until a plurality of trenches 66 having a desired depth are formed in the substrate 60. Thereafter, the first photoresist pattern 64 is removed.

Subsequently, referring to FIG. 13, the resultant from which the first photoresist pattern 64 is removed is oxidized. In this case, a surface of the substrate 60 in which the trench 66 is formed is exposed, but the remaining region is protected by the first insulating layer 62. Accordingly, the exposed region of the substrate 60 is oxidized by the oxidation, so that the trench 66 is filled with an oxide film. At this time, since the area covered with the first insulating layer 62 between the trenches 66 is very small, the area consisting of the plurality of trenches 66 of the substrate 60 is changed into one giant trench 66a. The inside is filled with a thick oxide film 68. When the substrate 60 is a silicon oxide film, the thick oxide film 68 is a silicon oxide film.

In the oxidation process, the growth of the region where the plurality of trenches 66 of the substrate 60 are formed does not occur in a certain direction. Therefore, a step exists in the surface of the thick oxide film 68 in the large trench 66a immediately after the oxidation process. Accordingly, the first insulating film 62 is removed to planarize the surface of the thick oxide film 68 in the large trench 66a, and then the second insulating film 70 is formed on the entire surface of the resultant. The second insulating film 70 is formed of a silicon oxide film. Thus, the thick oxide film 68 formed in the giant trench 66a and the second insulating film 70 become the same material film.

14 illustrates the steps of sequentially forming the intermediate insulating layers 74, 76, and 78. Specifically, a first conductive layer (not shown) is formed on the second insulating film 70. The first conductive layer is formed of an aluminum layer. The use of an aluminum layer as the first conductive layer is not intended to limit the present invention. Therefore, a conductive material layer other than aluminum may be used as the first conductive layer. The first conductive layer is patterned by a conventional photolithography process to form a first conductive layer pattern 72 on the second insulating layer 70 in the large trench 66a. A third insulating layer 74 is formed on the entire surface of the first conductive layer pattern 72 and the second insulating layer 70. The third insulating film 74 is formed of a silicon oxide film. Fourth and fifth insulating layers 76 and 78 are sequentially formed on the third insulating layer 74. The fourth insulating film 76 has a lower etching selectivity than the third insulating film 74 for the etchant used in the subsequent etching process of the fourth insulating film 76, that is, the third with respect to the etchant. An insulating material film having an etching rate higher than that of the insulating film 74 is formed. For example, when a silicon oxide film is used as the third insulating film 74, an oxide film doped with phosphorus may be used as the fourth insulating film 76. The fifth insulating layer 78 is formed of a silicon oxide film.

FIG. 15 is a diagram illustrating a step of forming a via hole 82 on the first conductive layer pattern 72.

Specifically, a second photosensitive film (not shown) is formed on the entire surface of the fifth insulating film 78. By patterning the second photoresist layer, a region corresponding to an upper region of the first conductive layer pattern 72 of the fifth insulating layer 78 and an area outside the region of the huge trench 66a of the fifth insulating layer 78 may be formed. The second photosensitive film pattern 80 to be exposed is formed. Anisotropically etch the exposed entire surface of the fifth insulating layer 78 using the second photoresist layer pattern 80 as an etching mask, and sequentially anisotropically align the fourth insulating layer 76 and the third insulating layer 74 corresponding thereto. Etch it. As a result, third to fifth insulating layer patterns 74a including a via hole 82 exposing an upper surface of the first conductive layer pattern 72 only on the thick oxide layer 68 in the large trench 66a. , 76a, 78a) are formed.

FIG. 16 illustrates forming first and second patterns 84a and 84b of the second conductive layer.

Specifically, in FIG. 15, the second photoresist layer pattern 80 and the fifth insulation layer pattern 78a are removed. A second conductive layer (not shown) filling the via hole 82 is formed on the entire surface of the resultant product. The second conductive layer is formed of an aluminum layer. A photosensitive film pattern (not shown) is formed on the second conductive layer to expose the second conductive layer on the fourth insulating layer pattern 76a. Using this photosensitive film pattern as an etching mask, the exposed surface of the second conductive layer is anisotropically etched until the interface of the fourth insulating film pattern 76a is exposed. When the photosensitive film pattern is removed, the fourth pattern 84a of the second conductive layer contacting the first conductive layer pattern 72 through the via hole 82 and the fourth of both the first pattern 84a. The second pattern 84b of the second conductive layer in contact with the insulating film pattern 74a is formed.

FIG. 17 illustrates a step of forming a cavity 90 around the first and second patterns 84a and 84b of the second conductive layer.

Specifically, a sixth insulating layer (not shown) is formed on the entire surface of the resultant product in which the first and second patterns 84a and 84b are formed. The sixth insulating film is an upper insulating film with respect to the lower and intermediate insulating films. The sixth insulating layer pattern 86a including an etch hole 88 for patterning the sixth insulating layer to expose an interface between the fourth insulating layer pattern 76a formed between the first and second patterns 84a and 84b. ). The fourth insulating layer pattern 76a is isotropically etched, for example, wet etched through the etch hole 88. As a result, all of the fourth insulating film patterns 76a formed between the first and second patterns 84a and 84b are removed, and a cavity 90 is formed therein. In the isotropic etching, an etchant for etching uses an etchant having a higher etching rate with respect to the fourth insulating film pattern 76a than the third insulating film pattern 74a, for example, hydrofluoric acid (HF). Therefore, since the third insulating layer pattern 74a is not etched in the isotropic etching, the first conductive layer pattern 72 is not damaged.

As described above, the present invention is used as an inductor by filling a conductive layer in a trench formed in a substrate. Therefore, the series resistance of the inductor can be reduced by making the cross-sectional area wider than that of the conductive layer having the same planar layout. Therefore, the queue factor of the inductor can be prevented from lowering. The trenches are formed within the shortest distance within the resolution of the design rule and the exposure apparatus to increase the integration degree of the semiconductor device. Therefore, the distance between the conductive layers filling the trench also becomes the most recent distance, thereby increasing the inductor capacity. Furthermore, since the cavity is formed around the trench, the possibility of forming a parasitic capacitor between the substrate and the inductor conductive layer is extremely low. Even if parasitic capacitors are formed, the air permittivity is very low, so the capacitance of the parasitic capacitors is low. Therefore, it is possible to prevent the capacity of the inductor from being lowered due to dielectric loss and the self-resonance frequency of the inductor from lowering. In addition, when the inductor having the above-described structure is applied to the transmission line, the delay time RC of the transmission line is shortened because the capacitance C of the parasitic capacitor becomes very low.

The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical idea of the present invention.

Claims (24)

A trench formed substrate; A first insulating film formed on the entire surface of the substrate; A first pattern of a first conductive layer filling the trench formed on the first insulating film; A second pattern of a first conductive layer formed on the first insulating film between the first patterns; A second insulating layer formed on an entire surface of the resultant product in which the first and second patterns including the via holes exposing the second pattern are formed; A second conductive layer pattern filling the via hole formed on the second insulating layer; A contact hole exposing the substrate formed between the first pattern and the second pattern; And And a cavity provided around the trench of the substrate. The inductor of claim 1, wherein the substrate is any one selected from a group consisting of a silicon substrate, a glass substrate, and an SOI substrate. The inductor of claim 1, wherein the inclination angle of the trench is about 1 ° to about 90 °. 2. The inductor of claim 1, wherein the first and second insulating films are silicon oxide films. The inductor of claim 1, wherein the first and second conductive layer patterns are aluminum layer patterns. Board; A lower insulating film formed on the substrate; A first conductive layer pattern formed on the lower insulating film; An insulating layer having a via hole on the first conductive layer pattern and surrounding the first conductive layer pattern; A second conductive layer pattern formed on the first conductive layer pattern and the lower insulating layer; An upper insulating film formed on an entire surface of the side surface and the upper surface of the second conductive layer pattern and having a hole between the second conductive layer pattern; And a cavity between the upper insulating film and the insulating film surrounding the second conductive layer pattern. 7. The inductor of claim 6, wherein the substrate is any one selected from the group consisting of a silicon substrate, a glass substrate, and an SOI substrate. 7. The inductor of claim 6, wherein the lower insulating film is formed of a trench oxide film formed on the substrate and a silicon oxide film formed on an entire surface of the substrate and the trench oxide film. 7. The inductor of claim 6, wherein the insulating film and the upper insulating film are silicon oxide films. The inductor of claim 6, wherein the first and second conductive layer patterns are aluminum layer patterns. (a) forming a trench in the semiconductor substrate; (b) forming a first insulating film on an entire surface of the semiconductor substrate on which the trench is formed; (c) forming a second pattern of a first conductive layer on the first insulating film between the first pattern and the first pattern of the first conductive layer filling the trench on the first insulating film; (d) forming a second insulating film on the entire surface of the product of step (c); (e) forming a via hole exposing the second pattern in the second insulating film; (f) forming a second conductive layer pattern filling the via hole on the second insulating layer pattern; And (g) forming a cavity around the trench. The method of claim 11, wherein the trench is formed such that the inclination angle of the inner wall is 10 ° to 90 °. 12. The method of claim 11, wherein the substrate is any one selected from the group consisting of a silicon substrate, a glass substrate, and an SOI substrate. The method of claim 11, wherein step (g) (g1) forming an etch hole exposing the substrate between the first pattern and the second pattern; And (g2) isotropically etching the exposed substrate through the etch hole. 15. The method of claim 14, wherein SF ₆ is used as an emitter in the isotropic etching. (a) forming a trench insulating film on the substrate; (b) forming a lower insulating film on the entire surface of the substrate and the trench insulating film; (c) forming a first conductive layer pattern on the lower insulating film formed on the trench type insulating film; (d) forming an intermediate insulating film on the first conductive layer pattern and the lower insulating film; (e) patterning the intermediate insulating layer to form an intermediate insulating layer pattern on the via hole and the trench type insulating layer exposing the first conductive layer pattern; (f) forming a second conductive layer pattern exposing the intermediate insulating film and filling the via hole on the resultant from which the insulating film formed on the top of the intermediate insulating film is removed; And (g) forming a cavity around the first and second conductive layer patterns. The method of claim 16, wherein step (a) (a1) forming a first insulating film on the entire surface of the substrate; (a2) forming a photoresist pattern defining a plurality of trench formation regions on the first insulating layer; (a3) forming a plurality of trenches in a predetermined region of the substrate using the photoresist pattern as an etching mask; And (a4) removing the photoresist pattern, and then oxidizing the substrate on which the plurality of trenches are formed. The method of claim 16, wherein step (d) And sequentially forming third to fifth insulating layers on the first conductive layer pattern and the lower insulating layer. 18. The method of claim 17, wherein the lower insulating film is a planarizing second insulating film formed on the entire surface of the product of step (a4). 19. The method of claim 18, wherein step (g) (g1) forming an upper insulating film having a contact hole on the fifth insulating film on an entire surface of the resultant product on which the second conductive layer pattern is formed; And (g2) further comprising removing the fourth insulating film. 21. The method of claim 20, wherein the fourth insulating film is removed by isotropic etching. 22. The method of claim 21, wherein in the isotropic etching, hydrofluoric acid (HF) having an etching rate higher than that of the third insulating layer is used. 21. The method of claim 20, wherein the third and fifth insulating films are formed of an insulating film doped with impurities, and the fourth insulating film is formed of an insulating film doped with impurities. 24. The inductor of claim 23, wherein the insulating layer doped with impurities is formed of a silicon oxide layer doped with phosphorus (P), and the third and fifth insulating layers are formed of a silicon oxide layer doped with impurities. Way.