JP2000040786A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inductor which can be enhanced in integration level and high in resonance sharpness Q. SOLUTION: An inductor is equipped with trenches 22 that are formed inside a silicon board 21 so as to look like spirals in a plan view, silicon oxide films 23 formed inside the trenches 22, an interlayer insulating film 24 formed on the surfaces of the silicon board 21 and the silicon oxide film 23, and aluminum wirings 26, that are formed on the upside of the interlayer insulating film 24 above the trenches 22 so as to look like spirals in a plan view.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an element structure in an integrated circuit and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the miniaturization and speeding up of semiconductor devices have made it possible to produce high-frequency integrated circuits in the GHz range used for mobile communication and satellite communication in a silicon process that is inexpensive and can be mass-produced. became. In such a high-frequency integrated circuit, elements such as a resistor, a capacitor, and an inductor are required to handle high-frequency analog small signals as well as elements that operate at a high frequency. In particular, an inductor element is required for an impedance matching circuit, and it is particularly important to reduce the loss for high gain and low power consumption of an IC.

In a conventional inductor element of a semiconductor element, as shown in FIG. 1, an aluminum wiring 1 as an electrode material is generally formed on an interlayer insulating film 2 in a spiral shape. FIG. 2 is a sectional view taken along line AA ′ in FIG.
As shown in FIG. 2, the interlayer insulating film 2 is formed on the upper surface of the semiconductor substrate 3. The aluminum wiring 1 is spirally formed on the upper surface of the interlayer insulating film 2.

[0004]

Here, as shown in FIG. 3, the inductor element shown in FIGS. 1 and 2 has a parasitic resistance (Rind) of the aluminum wiring 1 itself and a parasitic resistance of the semiconductor substrate 3. (Rsub) and the parasitic capacitance (Csub) of the aluminum wiring 1 to the semiconductor substrate 3 occur. These parasitic components degrade the resonance sharpness Q, which is the figure of merit of the inductor. In general, the resonance sharpness Q is proportional to the energy delivered to the system divided by the energy consumed by the inductor per cycle. Therefore, when the parasitic capacitance (Csub) occurs, the energy stored in the system decreases by the amount of charge stored in the parasitic capacitance (Csub). Further, due to the parasitic resistance (Rind) of the aluminum wiring 1 and the parasitic resistance (Rsub) of the semiconductor substrate 3, a voltage drop or current loss occurs in the system, and the energy stored in the system is reduced by that much. For these reasons,
The sharpness Q of the resonance, which is the figure of merit of the inductor, deteriorates.

Next, FIG. 4 shows an equivalent circuit of the inductor element. Here, attention is paid to Rind and Csub in order to increase the sharpness Q of resonance of the inductor element. Then, if the width of the aluminum wiring 1 is increased to reduce Rind, the area of the bottom surface of the aluminum wiring 1 increases,
Csub becomes large. Therefore, the following method has been considered to increase the sharpness Q of resonance of the inductor element. That is, (1) a method of increasing the thickness of the interlayer insulating film 2 to reduce Csub, and (2) a method of increasing the thickness of the aluminum wiring to reduce Rind.

However, if the method of (1) increasing the thickness of the interlayer insulating film 2 in order to reduce Csub is adopted, the following defects occur. That is, when the thickness of the interlayer insulating film 2 is increased, the contact hole has a high aspect ratio when the wiring or the like formed on the interlayer insulating film 2 contacts the semiconductor substrate 1. Therefore, it becomes difficult to bury the conductive film in the contact hole, and as a result, there is a disadvantage that it is difficult to make a contact. Next, if the method of (2) increasing the thickness of the aluminum wiring to reduce Rind is adopted, the following defects occur. That is, since the thickness of the aluminum wiring 1 is large, if an interlayer insulating film is further formed on the upper surfaces of the aluminum wiring 1 and the interlayer insulating film 2, there is a disadvantage that the flatness of the interlayer insulating film is deteriorated.

Further, the sharpness Q of resonance of the inductor element
Some attempts have been made to reduce Csub in order to increase Csub. According to a known document (Japanese Patent Application Laid-Open No. 6-18129), a method is disclosed in which a trench is formed in a silicon substrate by the same method as that for forming a trench, and a coil conductor is buried in the trench to increase Q. Further, according to a known document (Japanese Patent Application Laid-Open No. 8-172161), a method of depositing an insulating film having a low dielectric constant under a coil conductor to increase Q has been disclosed.

However, a known document (Japanese Patent Laid-Open No. 6-1812)
According to the method 9), the manufacturing process is complicated, and as a result, the manufacturing process is increased, resulting in a disadvantage that the cost is increased. In addition, a known document (Japanese Unexamined Patent Publication No.
According to the method 1), a step is structurally large, and disadvantageously disadvantageous to miniaturization of the whole semiconductor device. Also,
The use of the resin insulating film has a disadvantage that the moisture resistance is poor and that the characteristics of the other elements are affected by fluctuations in characteristics. Further, the number of manufacturing steps is increased, resulting in a disadvantage of increased cost. The present invention has been made in view of the above-mentioned disadvantages of the related art, and has as its object to provide an inductor element having a high resonance sharpness Q.

[0009]

In order to achieve the above object, the present invention is directed to a semiconductor device having a predetermined depth from a predetermined position on a semiconductor substrate and having a spiral shape when viewed from above. Trench, a first insulating film formed in the trench, a second insulating film formed on the upper surface of the semiconductor substrate and the first insulating film, and the second insulating film A metal wiring layer formed on the upper surface and above the trench so as to be spiral when viewed from the upper surface. According to the present invention, by adopting the above configuration, it is possible to provide an inductor element having a high resonance sharpness Q.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings (FIGS. 5 to 10). First,
As shown in FIG. 5, using a CVD method, a semiconductor substrate,
For example, a silicon oxide film 27 is formed on the upper surface of the silicon substrate 21. Next, a resist (not shown) is formed on the upper surface of the silicon oxide film 27 using a spin coating method. Then, this resist is patterned into a predetermined shape by using a photolithography method. Using the resist patterned in this predetermined shape as a mask, the silicon oxide film 27 is etched by an anisotropic etching method, for example, an RIE method. Further, using the silicon oxide film 27 patterned into the predetermined shape as a mask, the silicon substrate 21 is etched using an anisotropic etching method, for example, an RIE method. Thereby, for example, a trench 22 having a depth of about 1 μm to about 7 μm is formed. The depth of the trench 22 is not particularly limited to about 1 μm to about 7 μm, but may be any depth that is convenient in the manufacturing process. However, the effect of the first embodiment of the present invention becomes more remarkable as the depth of the trench 22 is larger. Here, for example, the trench 22 is formed so as to be spiral when viewed from above.

Next, as shown in FIG. 6, an insulating film, for example, a silicon oxide film 23 is formed on the entire surface by using the CVD method. Then, the silicon oxide film 23 is removed to the upper surface of the silicon substrate 21 by a predetermined flattening process. At this time, the silicon oxide film 27 is also removed. Here, the insulating film may be a silicon nitride film or the like instead of the silicon oxide film 23. However, since the silicon oxide film 23 has a low relative dielectric constant, Csub can be further reduced, and the sharpness Q of resonance is further increased. It becomes possible.

Next, as shown in FIG. 7, an interlayer insulating film 24 is formed to a thickness of about 3 μm on the entire surface by using the CVD method. Here, examples of the interlayer insulating film 24 include a silicon oxide film and a silicon nitride film. However, at this time,
If a silicon oxide film is used as the interlayer insulating film 24, the silicon oxide film 23 and the silicon oxide film 27 are not removed to the upper surface of the silicon substrate 21 in the step shown in FIG. It may be formed so that only about 3 μm remains. In this case, FIG.
Will be omitted.

Next, as shown in FIG. 8, a conductive film, for example, an aluminum film 25 is formed to a thickness of about 1 μm on the upper surface of the interlayer insulating film 24 by using, for example, a sputtering method. Here, instead of the aluminum film 25 as the conductive film, for example, a copper film may be used. In this case, since copper has lower resistance than aluminum, it is possible to obtain an effect of further increasing the Q of the inductor element.

Next, as shown in FIG. 9, a resist (not shown) is formed on the upper surface of the aluminum film 25 using a spin coating method. Then, the resist (not shown) is patterned into a predetermined shape by using a photo etching method. Using the resist patterned in the predetermined shape as a mask, the aluminum film 25 is etched into a predetermined shape by an anisotropic etching method, for example, an RIE method. Thereby, the aluminum wiring 2
6 are formed. Here, the aluminum wiring 26 is formed so as to overlap the trench 22 formed in the silicon substrate 21 when viewed from above. That is, when patterning a resist (not shown), the aluminum film 25 is exposed in the same shape as the trench 22 when viewed from above, that is, in a spiral shape here.

FIG. 10 shows the aluminum wiring 26 thus formed. FIG. 9 shows B-
This corresponds to the cross-sectional view of B ′. The spirally formed aluminum wiring 26 thus forms an inductor element.

As described above, the inductor element is formed. This inductor element is electrically connected to an external electric circuit by a wiring (not shown). here,
As shown in FIG. 9, a trench 22 in which a silicon oxide film 23 is formed is formed below the aluminum wiring 26. Therefore, in the vertical direction where the parasitic capacitance Csub occurs,
The distance between aluminum wiring 26 and silicon substrate 21 increases. Therefore, the parasitic capacitance Csub can be reduced. Further, by using a low-resistance copper wiring instead of the aluminum wiring 26, it is possible to further increase the sharpness Q of the resonance. As described above, according to the first embodiment of the present invention, it is possible to provide an inductor element having a high resonance sharpness Q without increasing the thickness of an interlayer insulating film as compared with the related art and maintaining flatness. Is possible.
In addition, since it is possible to suppress the occurrence of a step in the structure, it is possible to miniaturize the inductor element. Thus, high integration of the circuit and high operation speed of the element can be achieved. Further, since the inductor element can be formed simultaneously with the formation of the aluminum wiring 26, the number of steps is not required to be increased. Thereby, cost increase can be suppressed.

Next, a second embodiment of the present invention will be described with reference to the drawings (FIGS. 11 to 17). In a second embodiment of the present invention, the inductor element according to the present invention is used for a monolithic bipolar CMOS device. Here, a description will be given of a case where the present invention is applied to a monolithic bipolar CMOS device. However, the present invention is also applicable to other monolithic integrated circuits including resistors and capacitors.

First, as shown in FIG. 11, a semiconductor substrate of one conductivity type, for example, a p-type silicon substrate 33 is prepared. Here, the PMOS section 40, the NMOS section 41, the NPN transistor section 42, the PNP transistor section 43, the ground tap section 55, and the inductor element section 44 are considered separately. Here, the ground tap portion is a portion for obtaining a ground potential. On a p-type silicon substrate 33, a p + -type diffusion layer 31 and an n + -type diffusion layer 32 are formed. Further, an n − type silicon layer 45 is formed on the upper surface of the p type silicon substrate 33. This n− type silicon layer 45
It is formed using an epitaxial growth method.
Here, p + indicates that the p-type impurity has a higher concentration than a normal p-type diffusion layer. Further, n + is a normal n
It shows that the n-type impurity has a higher concentration than the n-type diffusion layer.
Further, "n-" indicates that the n-type impurity has a lower concentration than a normal n-type diffusion layer. Further, the n− type silicon layer 4
An n-type impurity, for example, P (phosphorus) is doped in a predetermined position of No. 5 to form an n-type impurity layer. Then, a silicon oxide film 34 serving as an oxide film is formed to a thickness of about 90 nm on the upper surface of the n − -type silicon layer 45 by using, for example, a thermal oxidation method. Further, a polysilicon film 35 not doped with impurities is formed on the entire surface to a thickness of about 100 nm by the CVD method. Further, a silicon nitride film 36 is formed to a thickness of about 200 nm on the entire surface by using the CVD method. further,
A silicon oxide film 37 is formed on the entire surface to a thickness of about several hundred nm by using the CVD method. Here, the silicon oxide film 34, the polysilicon film 35, and the silicon nitride film 36 are used for forming a LOCOS in a later element isolation step (see FIG. 13). Next, a resist (not shown) is formed on the entire surface to a thickness of about several hundred nm using a spin coating method. And
The resist is patterned into a predetermined shape using photolithography. Using the patterned resist as a mask, the silicon oxide film 37, the silicon nitride film 36, the polysilicon film 35, and the silicon oxide film 34 are etched using an anisotropic etching method, for example, an RIE method. Thereby, a part of the upper surface of the p-type silicon substrate 33 is exposed. Then, using the silicon oxide film 37 as a mask, the p-type silicon substrate 33 is etched to a predetermined depth using an anisotropic etching method, for example, an RIE method. This allows
The trench 38 is formed in the inductor element portion 44, and the trench 39 is formed in other portions. The depth of the trench 38 and the trench 39 is, for example, about 5 μm. Here, the trench 38 formed in the inductor element portion 44 is formed, for example, so as to be spiral when viewed from the upper surface of the p-type semiconductor substrate 33. Also, the trench 39
Are formed so as to cross the n-type impurity layers 56, respectively.

Next, as shown in FIG. 12, an insulating film, for example, a silicon oxide film 46 is formed on the entire surface so as to have a thickness of about 1.5 μm from the upper surface of the silicon oxide film 37 by using the CVD method. As a result, the trench 38 is buried with the silicon oxide film 46. Then, the silicon oxide film 46 is flattened to the upper surface of the silicon oxide film 37 by using a flattening process, for example, a CMP method. Further, the silicon oxide film 37 is removed by using a wet etching method. Next, the silicon oxide film 46 is flattened to the upper surface of the silicon nitride film 36 by using a flattening process, for example, a CMP method.

Although the silicon oxide film 46 is used as an insulating film to be buried in the trench 38 here, a polysilicon film or a silicon nitride film not doped with an impurity may be used. However, the silicon oxide film 46 is characterized by having a lower relative dielectric constant than a polysilicon film or a silicon nitride film. Therefore, there is an advantage that the sharpness Q of resonance of the inductor element in the monolithic bipolar CMOS device formed in the present embodiment is further increased.

The following steps may be added between the steps already shown in FIG. 11 and the steps already shown in FIG. That is, a step of implanting a p-type impurity, for example, B (boron) into the bottom of the trench 38 by, for example, an ion implantation method. By this step, the p-type silicon substrate 33
Of these, a p + type diffusion layer (not shown) is formed near the bottom of trench 38. This makes it possible to prevent the occurrence of a parasitic transistor.

Next, as shown in FIG. 13, predetermined n-type well regions 47 and locos oxide films 48 are formed. To this end, first, a resist (not shown) is applied to the entire surface using a spin coating method. Then, this resist is patterned into a predetermined shape by using a photo etching method. Using this resist as a mask, an n-type impurity, for example, P (phosphorus) is doped by ion implantation. Further, the resist is removed by ashing or using a mixed solution of a hydrogen peroxide solution and sulfuric acid. Next, a resist (not shown) is applied to the entire surface using a spin coating method. Then, this resist is patterned into a predetermined shape by using a photo etching method. Using this resist as a mask, the silicon nitride film 36 is etched using an anisotropic etching method, for example, an RIE method. Then, the silicon nitride film 36 is used as a mask to oxidize by a heat treatment at about 1000 ° C. to form the LOCOS oxide film 48.
In this thermal oxidation step, the N-type well region 47 and the n + diffusion layer 49 are simultaneously formed. In this way, the PMO
S part 40, NMOS part 41, NPN transistor part 4
2, PNP transistor section 43, ground tap section 55
In addition, a LOCOS oxide film 48, an N-type well region 47, and an n + diffusion layer 49 for separating the inductor element portion 44 from each other are formed.

Next, as shown in FIG. 14, a first interlayer insulating film, for example, a silicon oxide film 4 is formed on the entire surface by CVD.
9 is formed to a thickness of about several μm. Then, a first contact hole is formed by a predetermined etching step and a film forming step, and the conductive film 50 is embedded in the first contact hole. This conductive film 50 is electrically connected to a predetermined element formed on the n − type silicon layer 45. Further, C
A second interlayer insulating film, for example, a silicon oxide film 51 is formed on the entire surface to a thickness of about several μm by using the VD method. Then, a second contact hole 52 is formed in the silicon oxide film 51 by a predetermined etching process. This second contact hole is formed so as to be connected to the conductive film 50. Here, a silicon oxide film is used as a material of the first interlayer insulating film and the second interlayer insulating film, but a silicon nitride film or the like is used as another material. However, since the silicon oxide film has a low relative dielectric constant, the sharpness Q of resonance of the inductor element formed in the inductor element portion can be further increased.

Next, as shown in FIG. 15, a conductive film, for example, an aluminum film 53 is formed on the entire surface to a thickness of about 1 μm from the upper surface of the silicon oxide film 51 by using, for example, a sputtering method. Here, in addition to the aluminum film, for example, a copper film may be used as the conductive film. In this case, the copper film has an advantage of lower resistance than the aluminum film. Then, there is an advantage that an effect of further increasing the Q of the inductor element can be obtained.

Next, the step shown in FIG. 16 is performed. First,
A resist (not shown) is formed on the upper surface of the aluminum film 53 by using a spin coating method. Then, the resist (not shown) is patterned into a predetermined shape by using a photo etching method. At this time, in the inductor element portion 44, the aluminum film 53 is exposed in the same shape as the trench 38 formed in the inductor element portion 44 of the p-type silicon substrate 33 when viewed from above. Next, using the resist patterned in the predetermined shape as a mask, the aluminum film 53 is etched into a predetermined shape by an anisotropic etching method, for example, an RIE method. Thereby, the aluminum wiring 54 is formed. Here, the aluminum wiring 54 is formed so as to overlap the trench 38 when viewed from above. That is, in the inductor element portion 44, the aluminum wiring 54 is formed above the trench 38 formed in the p-type silicon substrate 33, and has a spiral shape when viewed from above. The aluminum wiring 54 has a width of about 3 μm and a height of about 1 μm.

FIG. 17 shows a view of the inductor element section 44 as viewed from above. The inductor element portion in FIG.
This corresponds to the cross-sectional view taken along the line CC ′ in FIG. Thus, the spirally formed aluminum wiring 5 is formed.
4 forms an inductor element.

Although the aluminum wiring 54 serving as an inductor element is formed on the upper surface of the silicon oxide film 51, it may be formed on the upper surface of the silicon oxide film 49. However,
When formed on the upper surface of the silicon oxide film 51, the distance between the aluminum wiring 54 and the p-type silicon substrate 33 becomes longer, and the parasitic capacitance can be reduced.
Can be made larger.

As described above, a monolithic bipolar CMOS device including an inductor element is formed. Note that the inductor element made of the aluminum wiring 54 is electrically connected to an external electric circuit by a wiring (not shown). Here, as shown in FIG. 16, not only an interlayer insulating film but also a trench 38 in which a silicon oxide film 46 is buried is formed below the aluminum wiring 54. Therefore, in the vertical direction in which the parasitic capacitance Csub occurs, the distance between the aluminum wiring 54 and the p-type silicon substrate 33 increases. Therefore, the parasitic capacitance Csub can be reduced. This makes it possible to increase the sharpness Q of the resonance. If a copper wiring having a lower resistance is used instead of the aluminum wiring 54, the sharpness Q of the resonance can be further increased. As described above, according to the second embodiment of the present invention, the monolithic bipolar device including the inductor element having the high resonance sharpness Q without increasing the thickness of the interlayer insulating film as compared with the related art and maintaining the flatness. It is possible to provide a CMOS device. In addition, since it is possible to suppress the occurrence of a step in the structure, it is possible to miniaturize the inductor element. Thus, high integration of the circuit and high operation speed of the element can be achieved. Further, the inductor element can be formed simultaneously with the formation of the aluminum wiring 54. Since the trench 38 is formed simultaneously with the formation of the trench 39 for element isolation and the inductor element is formed simultaneously with the formation of the aluminum wiring 54, there is an advantage that the number of steps is not required to be increased. This makes it possible to suppress an increase in cost.

Although a monolithic bipolar CMOS device has been described as the second embodiment of the present invention, the device is not limited to this as long as it has a trench. For example, the present invention can be used for a DRAM using a trench capacitor. Even when the present invention is applied to a DRAM, the same effect as that of the second embodiment of the present invention can be obtained.

[0030]

According to the present invention, the sharpness Q of resonance of the inductor element can be increased.

[Brief description of the drawings]

FIG. 1 is a top view of a conventional inductor element.

FIG. 2 is a structural sectional view of a conventional inductor element.

FIG. 3 is a structural sectional view of a conventional inductor element.

FIG. 4 is an equivalent circuit of a conventional inductor element.

FIG. 5 is a sectional view showing the manufacturing process of the inductor element according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing the manufacturing process of the inductor element according to the first embodiment of the present invention.

FIG. 7 is a sectional view showing the manufacturing process of the inductor element according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing the manufacturing process of the inductor element according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of the inductor element according to the first embodiment of the present invention.

FIG. 10 is a top view of the inductor element according to the first embodiment of the present invention.

FIG. 11 is a sectional view showing a manufacturing process of the monolithic bipolar CMOS device according to the second embodiment of the present invention;

FIG. 12 is a sectional view showing a manufacturing process of the monolithic bipolar CMOS device according to the second embodiment of the present invention;

FIG. 13 is a sectional view showing a manufacturing process of the monolithic bipolar CMOS device according to the second embodiment of the present invention.

FIG. 14 is a sectional view showing a manufacturing process of the monolithic bipolar CMOS device according to the second embodiment of the present invention;

FIG. 15 is a sectional view showing the manufacturing process of the monolithic bipolar CMOS device according to the second embodiment of the present invention.

FIG. 16 is a sectional view showing the manufacturing process of the monolithic bipolar CMOS device according to the second embodiment of the present invention;

FIG. 17 is a top view of an inductor element of a monolithic bipolar CMOS device according to a second embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Aluminum wiring 2 ... Interlayer insulating film 3 ... Semiconductor substrate 21 ... Silicon substrate 22 ... Trench 23 ... Silicon oxide film 24 ... Interlayer insulation Film 25: Aluminum film 26: Aluminum wiring 27: Silicon oxide film 31: P + type diffusion layer 32: N + type diffusion layer 33: P type silicon substrate 34 silicon oxide film 35 polysilicon film 36 silicon nitride film 37 silicon oxide film 38 trench 39 trench 40 PMOS Unit 41 NMOS unit 42 NPN transistor unit 43 PNP transistor unit 44 Inductor element unit 45 n-type silicon layer 46 silicon oxide film 47 ... N-type c LOCOS oxide film 49 n + diffusion layer 50 conductive film 51 silicon oxide film 52 second contact hole 53 aluminum film 54 ····· Aluminum wiring 55 ····· Ground tap part 56 ····· N-type impurity layer 57 ··· P-type well region

Claims (14)

[Claims] A trench having a predetermined depth from a predetermined position on the semiconductor substrate; a first insulating film formed in the trench; and a top surface formed on the semiconductor substrate and the first insulating film. A semiconductor device, comprising: a second insulating film formed; and a metal wiring formed on the upper surface of the second insulating film and overlapping the trench when viewed from the upper surface. 2. A trench having a predetermined depth from a predetermined position on the semiconductor substrate and spirally formed when viewed from above the semiconductor substrate, and a first trench formed in the trench. An insulating film; a second insulating film formed on the upper surfaces of the semiconductor substrate and the first insulating film; and an upper surface of the second insulating film, formed so as to overlap the trench when viewed from the upper surface. A semiconductor device comprising: 3. The semiconductor device according to claim 1, wherein said first insulating film comprises a silicon oxide film. A step of forming a trench having a predetermined depth from a predetermined position on an upper surface of the semiconductor substrate; a step of forming a first insulating film in the trench; and forming a second insulating film on the entire surface. Forming a metal wiring on the upper surface of the second insulating film so as to overlap the trench when viewed from above. 5. A step of forming a trench having a predetermined depth from a predetermined position on an upper surface of the semiconductor substrate and spirally viewed from the upper surface of the semiconductor substrate, and forming a first insulating film in the trench. Forming, forming a second insulating film on the entire surface, and forming a metal wiring on the upper surface of the second insulating film so as to overlap the trench when viewed from above. A method for manufacturing a semiconductor device. 6. The method according to claim 4, wherein the first insulating film is made of a silicon oxide film. 7. A trench having a predetermined depth from a predetermined position on a semiconductor substrate, a first insulating film formed in the trench, and formed on upper surfaces of the semiconductor substrate and the first insulating film. A second insulating film, a metal wiring formed on the upper surface of the second insulating film so as to overlap the trench when viewed from above, and a predetermined element. . 8. A trench having a predetermined depth from a predetermined position on the semiconductor substrate and formed in a spiral shape when viewed from above the semiconductor substrate; and a trench formed in the trench. A first insulating film, a second insulating film formed on an upper surface of the semiconductor substrate and the first insulating film, and an upper surface of the second insulating film so as to overlap the trench when viewed from above. A semiconductor device comprising: a formed metal wiring; and a predetermined element. 9. The semiconductor device according to claim 7, wherein said first insulating film is made of a silicon oxide film. 10. The semiconductor device according to claim 7, wherein the predetermined element is a DRAM having a trench capacitor and an information transfer transistor. 11. A step of forming a first trench having a predetermined depth at a predetermined position on the upper surface of the semiconductor substrate and a second trench having a predetermined depth from a predetermined position on the upper surface of the semiconductor substrate. Forming a first insulating film in the first trench and the second trench; forming a predetermined element in the semiconductor substrate and on the semiconductor substrate; Manufacturing a semiconductor device, comprising: forming an insulating film; and forming a metal wiring on an upper surface of the second insulating film so as to overlap the second trench when viewed from above. Method. 12. A first trench having a predetermined depth at a predetermined position on the upper surface of the semiconductor substrate, and a first trench having a predetermined depth from a predetermined position on the upper surface of the semiconductor substrate as viewed from the upper surface of the semiconductor substrate. Forming a second trench spirally; forming a first insulating film in the first trench and in the second trench; and forming a first insulating film in the semiconductor substrate and on the semiconductor substrate. Forming an element; forming a second insulating film on the entire surface; forming a metal wiring on the upper surface of the second insulating film so as to overlap the second trench when viewed from above. A method for manufacturing a semiconductor device, comprising: 13. The method according to claim 11, wherein the first insulating film is made of a silicon oxide film. 14. The semiconductor device according to claim 11, wherein said predetermined element is a DRAM including a trench capacitor and an information transfer transistor.