KR19990074719A - Semiconductor Memory Manufacturing Method - Google Patents

Abstract

The present invention relates to a method of manufacturing a semiconductor memory, and the conventional method of manufacturing a semiconductor memory has a problem in that the pads are formed by a photolithography process, so that a margin is insufficient to form an accurate pattern. In view of the above problems, the present invention includes a source and drain exposing step of depositing an insulating film on the MOS transistor formed on the substrate, forming a contact hole to expose the source and drain of the MOS transistor; A pad forming step of forming a capacitor pad and a bit line pad respectively connected to the exposed source and drain; In the semiconductor memory manufacturing method comprising a bit line and a capacitor forming step of manufacturing a bit line and a capacitor to be insulated with an insulating film on top of each of the capacitor pad and the bit line pad, wherein the pad forming step is a contact formed on the insulating film and the insulating film By depositing a conductive film on top of the source and drain exposed through the hole, and forming a planarized self-aligning method, process margins are easier to secure than the conventional technology manufactured by the photolithography process, and thus accurate patterns are obtained. It is effective to form.

Description

Semiconductor Memory Manufacturing Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory, and more particularly, to a semiconductor memory in which a pad to which a bit line is to be connected and a pad to which a capacitor is to be connected at the same time are formed to be suitable for securing a process margin by reducing a step. .

In general, a cell of a semiconductor memory fabricates an NMOS transistor having a common drain on an upper portion of a substrate, forms a pad to which a bit line is connected to a common drain of the NMOS transistor, and connects a capacitor to each source. Form pads for. Each pad formed as described above is formed by depositing an insulating layer, forming a contact hole in the insulating layer, depositing a conductive material, and then patterning the formed pad, which is complicated in the manufacturing process and has a limited resolution. Since it is difficult to secure a margin of the process, an accurate process is not made, and this will be described in detail with reference to the accompanying drawings.

1A to 1D are cross-sectional views of a process of manufacturing a conventional semiconductor memory. As shown in FIG. 1A to 1D, a first insulating film 2 is formed on an entire upper surface of a substrate 1 on which MOS transistors NM1 and NM2 having a common drain are manufactured. E) deposition (FIG. 1A); Forming a contact hole in the first insulating layer 2 to expose the common drain and each source of the MOS transistors NM1 and NM2, and each of the capacitor pad 3 and a bit line pad at the common drain. (4) forming (Fig. 1B); The second insulating layer 5 is deposited on the capacitor pad 3, the bit line pad 4, and the upper surface of the first insulating layer 2, and a contact hole is formed in the second insulating layer 5 to form the bit line. After the pad 4 is exposed, a bit line 6 connected to the bit line pad 4 is formed, and the third insulating film 7 is formed on the upper surface of the bit line 6 and the second insulating film 5. Evaporation) (FIG. 1C); Contact holes are formed in the third insulating layer 7 and the second insulating layer 5 through the photolithography process to expose the capacitor pad 3, and then the capacitor lower electrode 8 connected to the capacitor pad 3. ) Is formed (FIG. 1D).

Hereinafter, a conventional semiconductor memory manufacturing method configured as described above will be described in more detail.

First, as shown in FIG. 1A, a first insulating film 2 is deposited on the semiconductor substrate 1 on which the MOS transistors NM1 and NM2 are manufactured. At this time, the upper portion of the first insulating film 2 to be deposited is deposited to be flat.

Next, as shown in FIG. 1B, a contact hole is formed on the first insulating layer 2 through a photolithography process to expose a common drain and each source of the MOS transistors NM1 and NM2. A bit line pad connected to the common drain by depositing a conductive material on the exposed common drain, the source and the upper surface of the first insulating layer 2, and patterning the deposited conductive material through a photolithography process. (4) and capacitor pads 3 connected to the respective sources are formed.

By forming the bit line pad 4 and the capacitor pad 3 using the photolithography process as described above, the upper portion of the bit line pad 4 and the capacitor pad 3 is formed on the upper portion of the first insulating layer 2. It will have a more protruding shape.

Next, as shown in FIG. 1C, a second insulating film 5 is deposited on the capacitor pad 3, the bit line pad 4, and the first insulating film 2, and a photolithography process is performed thereon. A contact hole is formed through which the bit line pad 4 is exposed.

Next, a conductive material is deposited on the formed contact hole and the upper surface of the second insulating layer 5, and then the bit line 6 is formed through a photolithography process.

At this time, the upper part of the bit line 6 is formed to protrude more than the upper part of the second insulating film 5, and the third insulating film 7 is formed on the bit line 6 and the second insulating film 5. Deposit.

Next, as shown in FIG. 1D, a contact hole is formed in the third insulating layer 7 and the second insulating layer 5 by a photolithography process to expose the capacitor pad 3, and the capacitor pad 3. Capacitor lower electrode 8 is formed. In the subsequent process, a capacitor is manufactured by sequentially depositing a dielectric material and an upper electrode on the capacitor lower electrode 8.

Another embodiment of the conventional semiconductor memory manufacturing method is to form a contact hole in the first to third insulating layers after forming the bit line pad and the bit line without forming a capacitor pad at the time of forming the first pad to form the source of each MOS transistor. The method of manufacturing a capacitor after exposure is also used.

As described above, in the conventional semiconductor memory manufacturing method, each pad and bit line are manufactured through a photolithography process, so that 0.18 at the time of manufacturing a large capacity DRAM (1GB). μ We follow the design rule of m and the resolution limit is 0.25 μ m KrF and 0.18 μ An exposure apparatus using ArF of m as a beam source has a problem in that pad formation is insufficient and thus an accurate pattern cannot be formed. The method of forming the capacitor lower electrode directly on the upper part has a problem in that it is not possible to form an almost accurate pattern using current etching techniques.

In view of the above problems, an object of the present invention is to provide a method of manufacturing a semiconductor memory capable of forming a pad having an accurate pattern by using a self-aligning method without using a mask.

1A to 1D are cross-sectional views of a manufacturing process of a conventional semiconductor memory.

2A to 2E are cross-sectional views of a manufacturing process of the semiconductor memory of the present invention.

*** Description of the symbols for the main parts of the drawings ***

1: Substrate 2: First insulating film

3: conductive film 4: bit line pad

5: Capacitor pad 6: Second insulating film

7: bit line 8: third insulating film

9: capacitor lower electrode

The above object is a source and drain exposure step of depositing an insulating film on top of the MOS transistor formed on the substrate, and forming a contact hole to expose the source and drain of the MOS transistor; A pad forming step of forming a capacitor pad and a bit line pad respectively connected to the exposed source and drain; In the semiconductor memory manufacturing method comprising a bit line and a capacitor forming step of manufacturing a bit line and a capacitor to be insulated with an insulating film on top of each of the capacitor pad and the bit line pad, wherein the pad forming step is a contact formed on the insulating film and the insulating film It is achieved by depositing and planarizing a conductive film on top of a source and a drain exposed through the hole. The present invention will be described in detail with reference to the accompanying drawings.

2A to 2E are schematic cross-sectional views of a semiconductor memory fabrication process of the present invention, in which a first insulating film 2 is formed on an upper surface of a substrate 1 on which MOS transistors NM1 and NM2 having a common drain are manufactured. Thick) (FIG. 2A); The first insulating layer 2 is planarized through chemical mechanical polishing (CMP) to expose upper gates of the MOS transistors NM1 and NM2, and a photoresist PR is applied to form a pattern. Exposing a first insulating film 2 deposited over the source and common drain of the MOS transistors NM1 and NM2 (FIG. 2B); In the etching process using the photoresist PR as an etching mask, the exposed first insulating layer 2 is etched to expose the source and the common drain of the MOS transistors NM1 and NM2, and the first insulating layer is exposed. (2) and depositing a thick conductive film 3 on top of the exposed source and common drain (FIG. 2C); Forming the bit line pad 4 and the capacitor pad 5 by planarizing the deposited conductive film 3 using a chemical mechanical polishing method (FIG. 2D); A second insulating layer 6 is deposited on the first insulating layer 2, the bit line pad 4, and the capacitor pad 5, and a contact hole is formed in the second insulating layer 6 through a photolithography process. After exposing the bit line pad 4 and depositing a conductive film on the bit line pad 4 and the second insulating film 6, the bit line 7 is removed using a chemical mechanical polishing method. After the formation, a third insulating film 8 is deposited on the bit lines 7 and the upper surface of the second insulating film 6, and then, on the third and second insulating films 8 and 6 through a photolithography process. And forming a contact hole to expose the capacitor pad 5, and then forming a capacitor lower electrode 9 connected to the capacitor pad 5 (FIG. 2E).

Hereinafter, the present invention configured as described above will be described in more detail.

First, as shown in FIG. 2A, the first insulating film 2 is thickly deposited on the semiconductor substrate 1 on which the MOS transistors NM1 and NM2 having the common drain are fabricated.

Then, as shown in Fig. 2B, the deposited first insulating film 2 is planarized using a chemical mechanical polishing method. In this case, the end point of planarization is when the insulating film deposited on the gate of each of the MOS transistors NM1 and NM2 is exposed.

Next, a photoresist PR is coated on the upper surface of the planarized first insulating layer 2, and the photoresist PR is exposed, developed, and deposited on the common drain and source of the MOS transistors NM1 and NM2. One insulating film 2 and a pattern exposing the gate thereof are formed.

Next, as shown in FIG. 2C, the exposed first insulating layer 2 is selectively etched by an etching process using the photoresist PR having the pattern as an etching mask. At this time, the gates of the MOS transistors NM1 and NM2 are protected by insulating materials formed on the side and top surfaces thereof.

Then, the common drain and each source of the MOS transistors NM1 and NM2 are exposed by the etching process as described above, the photoresist PR is removed, the exposed common drain and source and the first insulating layer 2 are exposed. The conductive film 3 is thickly deposited on the entire upper surface of the substrate.

Next, as shown in FIG. 2D, the thick deposited conductive film 3 is planarized by using a chemical mechanical polishing method, whereby the bit line pad 4 having the same height as the first insulating film 2 and its upper surface is formed. ) And the capacitor pad 5. As such, the bit line pads 4 and the capacitor pads 5 are manufactured in a self-aligning method without using a mask, thereby making it easier to secure a margin than when formed by a photolithography process.

Next, as shown in FIG. 2E, a second insulating layer 6 is deposited on the first insulating layer 2, the bit line pad 4, and the capacitor pad 5, and the photo-etching process is performed. A contact hole is formed in the second insulating film 6, the bit line pad 4 is exposed, and a conductive film is deposited on the bit line pad 4 and the second insulating film 6, followed by chemical mechanical polishing. After forming the bit line 7 using the method, a third insulating film 8 is deposited on the upper surface of the bit line 7 and the second insulating film 6, and the third etching film is formed by a photolithography process. And forming a contact hole in the second insulating layers 8 and 6 to expose the capacitor pad 5, and then forming a capacitor lower electrode 9 connected to the capacitor pad 5. A capacitor is manufactured by sequentially depositing an insulating material and an upper electrode on the capacitor lower electrode 9, Depositing a protective material on top of the capacitor is complete the manufacturing process.

As described above, the semiconductor memory manufacturing method of the present invention forms a pad formed at a position where the bit line and the capacitor are to be connected to the MOS transistor in a self-aligned manner, thereby securing process margins as compared with the conventional technology manufactured by the photolithography process. It is easy and thus has the effect of forming an accurate pattern.

Claims (1)

A source and drain exposing step of depositing an insulating film over the MOS transistor formed on the substrate and forming a contact hole to expose the source and the drain of the MOS transistor; A pad forming step of forming a capacitor pad and a bit line pad respectively connected to the exposed source and drain; In the semiconductor memory manufacturing method comprising a bit line and a capacitor forming step of manufacturing a bit line and a capacitor to be insulated with an insulating film on top of each of the capacitor pad and the bit line pad, wherein the pad forming step is a contact formed on the insulating film and the insulating film A method of manufacturing a semiconductor memory, comprising depositing and planarizing a conductive film on top of a source and a drain exposed through a hole.