KR100871369B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR100871369B1
KR100871369B1 KR1020020040793A KR20020040793A KR100871369B1 KR 100871369 B1 KR100871369 B1 KR 100871369B1 KR 1020020040793 A KR1020020040793 A KR 1020020040793A KR 20020040793 A KR20020040793 A KR 20020040793A KR 100871369 B1 KR100871369 B1 KR 100871369B1
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interlayer oxide
bit line
forming
film
oxide film
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KR1020020040793A
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Korean (ko)
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KR20040006500A (en
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임영수
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

본 발명은 반도체소자의 제조방법에 관한 것으로, 본 발명에 따른 반도체 소자의 제조방법은, 반도체기판 상에 제1층간산화막을 형성하고, 이를 선택적으로 패터닝한후 패터닝한 부분에 콘택플러그를 형성하는 단계; 상기 콘택플러그를 포함한 제1층간산화막 상에 제2층간산화막과 제1질화막 및 제3층간산화막을 적층하는 단계; 상기 제3층간산화막과 제1질화막 및 제2층간산화막을 선택적으로 제거하여 비트라인콘택홀을 형성하는 단계; 상기 비트라인콘택홀 측벽에 스페이서를 형성하는 단계; 상기 비트라인콘택홀내에 도전막패턴과 제2질화막을 매립하는 단계; 및 상기 전체 구조의 상면에 제4층간절연막을 형성하는 단계를 포함하여 구성되며, 라인형태의 홀내에 비트라인을 형성하여 보이드가 없는 구조를 만듦 으로써 스토리지노드 증착공정에서의 브릿지 불량을 해결할 수 있고, 기존 공정대비 자기정렬콘택 마진확보가 가능한 것이다. The present invention relates to a method for manufacturing a semiconductor device, the method for manufacturing a semiconductor device according to the present invention, forming a first interlayer oxide film on a semiconductor substrate, and selectively patterning it and then forming a contact plug on the patterned portion step; Stacking a second interlayer oxide film, a first nitride film, and a third interlayer oxide film on the first interlayer oxide film including the contact plug; Selectively removing the third interlayer oxide layer, the first nitride layer, and the second interlayer oxide layer to form a bit line contact hole; Forming spacers on sidewalls of the bit line contact holes; Embedding a conductive layer pattern and a second nitride layer in the bit line contact hole; And forming a fourth interlayer insulating film on the upper surface of the entire structure, and forming a bit line without forming a bit line in a line-shaped hole to solve a bridge failure in a storage node deposition process. As a result, margins for self-aligned contacts can be secured compared to existing processes.

Description

반도체소자의 제조방법{Method for fabricating semiconductor device} Method for fabricating semiconductor device

도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

도 2는 본 발명에 따른 반도체소자의 제조방법에 있어서, 비트라인과 비트라인 콘택을 도시한 레이아웃도.2 is a layout showing bit lines and bit line contacts in the method of manufacturing a semiconductor device according to the present invention;

도 3a 내지 도 3f는 본 발명에 따른 반도체소자의 제조방법에 있어서, 도 2의 Ⅲ-Ⅲ 선에 따른 공정단면도.3A to 3F are cross-sectional views taken along line III-III of FIG. 2 in the method of manufacturing a semiconductor device according to the present invention.

도 4는 본 발명에 따른 반도체소자의 제조방법에 있어서, 도 2의 Ⅳ-Ⅳ 선에 따른 단면도. 4 is a cross-sectional view taken along line IV-IV of FIG. 2 in the method of manufacturing a semiconductor device according to the present invention.

[도면부호의설명][Description of Drawing Reference]

31 : 반도체기판 33 : 제1층간산화막31 semiconductor substrate 33 first interlayer oxide film

35 : 콘택플러그 37 : 제2층간산화막35 contact plug 37 second interlayer oxide film

39 : 질화막 41 : 제3층간산화막39: nitride film 41: third interlayer oxide film

43 : 제1감광막패턴 45 : 제2감광막패턴43: first photosensitive film pattern 45: second photosensitive film pattern

47 : 비트라인콘택홀 49 : 질화막스페이서47: bit line contact hole 49: nitride spacer

51 : 도전막패턴 53 : 질화막패턴51 conductive film pattern 53 nitride film pattern

55 : 제4층간산화막55: fourth interlayer oxide film

본 발명은 반도체소자의 제조방법에 관한 것으로서, 보다 상세하게는 비트라인 포토공정을 생략하고 비트라인 텅스텐 에치백 및 CMP를 이용하여 비트라인으 안정적으로 형성할 수 있는 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of stably forming a bit line using a bit line tungsten etch back and CMP without the bit line photo process. .

종래기술에 따른 반도체소자의 제조방법을 도 1a 내지 1d를 참조하여 설명하면 다음과 같다.A method of manufacturing a semiconductor device according to the prior art will now be described with reference to FIGS. 1A to 1D.

도 1a 내지 도 1d는 종래기술에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

종래기술에 따른 반도체소자의 제조방법은, 도 1a에 도시된 바와같이, 반도체기판(11)상에 제1층간산화막(13)을 증착한후 이를 선택적으로 패터닝하여 플러그 콘택홀(미도시)을 형성한다.In the method of manufacturing a semiconductor device according to the related art, as shown in FIG. 1A, a plug contact hole (not shown) is formed by depositing a first interlayer oxide layer 13 on a semiconductor substrate 11 and then selectively patterning the first interlayer oxide layer 13. Form.

그다음, 상기 플러그콘택홀(미도시)내에 폴리실리콘을 증착하여 콘택플러그(15)을 형성한후 전체 구조의 상면에 제2층간산화막(17)을 증착한다.Next, polysilicon is deposited in the plug contact hole (not shown) to form the contact plug 15, and then the second interlayer oxide layer 17 is deposited on the upper surface of the entire structure.

이어서, 상기 제2층간산화막(17)을 패터닝하여 상기 콘택플러그(15) 상면을 노출시킨후 전체 구조의 상면에 도전막(19)을 증착하고 이어 그 위에 질화막(21)과 감광막패턴(23)을 차례로 형성한다. 이때, 상기 감광막패턴(23)은 먼저 질화막(21)상에 감광물질을 도포한후 이를 포토리소그라피 공정기술에 의한 노광 및 현상공정을 거쳐 선택적으로 패터닝하여 형성한 것이다. Subsequently, the second interlayer oxide layer 17 is patterned to expose the upper surface of the contact plug 15, and then a conductive layer 19 is deposited on the upper surface of the entire structure. Then, the nitride layer 21 and the photoresist layer pattern 23 are formed thereon. Form in turn. At this time, the photosensitive film pattern 23 is formed by first applying a photosensitive material on the nitride film 21 and then selectively patterning the photosensitive material through an exposure and development process using a photolithography process technology.                         

그다음, 도 1b에 도시된 바와같이, 상기 감광막패턴(23)을 마스크로 상기 질화막(21)과 도전막(19)을 선택적으로 제거한후 상기 감광막패턴(23)을 제거한다.1B, the nitride film 21 and the conductive film 19 are selectively removed using the photosensitive film pattern 23 as a mask, and then the photosensitive film pattern 23 is removed.

이어서, 도 1c에 도시된 바와같이, 상기 패터닝된 질화막(23a)과 도전막패턴(19a)의 측면에 절연막스페이서(25)을 형성한다.Subsequently, as shown in FIG. 1C, an insulating film spacer 25 is formed on side surfaces of the patterned nitride film 23a and the conductive film pattern 19a.

그다음, 도 1d에 도시된 바와같이, 전체 구조의 상면에 제3층간산화막(27)을 이용한 갭매립을 위한 증착공정을 수행한다.Next, as illustrated in FIG. 1D, a deposition process for filling gaps using the third interlayer oxide film 27 is performed on the upper surface of the entire structure.

그러나, 상기와 같은 종래기술에 의하면, 최종 비트라인 형성시에 높이가 약 3600 Å(하드마스크 포함) 정도로 스페이스와의 에스펙트비가 4:1 이상으로 갭 매립시에, 도 1d에서와 같이, 보이드(void)(29)가 발생하여 후속 스토리지노드용 폴리실리콘 증착공정에서의 브릿지를 유발하고, 비트라인과 스토리지노드와의 자기정렬콘택 마진 확보가 매우 취약하게 된다.However, according to the prior art as described above, when the final bit line is formed, the aspect ratio with the space is about 3600 Hz (including a hard mask) of 4: 1 or more, and when the gap is filled, as shown in FIG. (void) 29 is generated to cause a bridge in a subsequent polysilicon deposition process for the storage node, and the margin of self-aligned contact between the bit line and the storage node is very weak.

이에 본 발명은 상기 종래기술의 제반 문제점을 해결하기 위하여 안출한 것으로서, 라인형태의 홀내에 비트라인을 형성하여 보이드가 없는 구조를 만듦 으로써 스토리지노드 증착공정에서의 브릿지 불량을 해결할 수 있고, 기존 공정대비 자기정렬콘택 마진확보가 가능한 반도체소자의 제조방법을 제공함에 그 목적이 있다.Therefore, the present invention has been made to solve the above problems of the prior art, by forming a bit line in a line-shaped hole to create a void-free structure to solve the bridge failure in the storage node deposition process, the existing process It is an object of the present invention to provide a method of manufacturing a semiconductor device capable of securing a contrast self-aligning contact margin.

상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은, 반도체기판 상에 제1층간산화막을 형성하고, 이를 선택적으로 패터닝한후 패터닝한 부분에 콘택플러그를 형성하는 단계; 상기 콘택플러그를 포함한 제1층간산화막 상에 제2층간산화막과 제1질화막 및 제3층간산화막을 적층하는 단계; 상기 제3층간산화막과 제1질화막 및 제2층간산화막을 선택적으로 제거하여 비트라인콘택홀을 형성하는 단계; 상기 비트라인콘택홀 측벽에 스페이서를 형성하는 단계; 상기 비트라인콘택홀내에 도전막패턴과 제2질화막을 매립하는 단계; 및 상기 전체 구조의 상면에 제4층간절연막을 형성하는 단계를 포함하여 구성되는 것을 특징으로한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a first interlayer oxide film on a semiconductor substrate, selectively patterning the contact layer and forming a contact plug on the patterned portion; Stacking a second interlayer oxide film, a first nitride film, and a third interlayer oxide film on the first interlayer oxide film including the contact plug; Selectively removing the third interlayer oxide layer, the first nitride layer, and the second interlayer oxide layer to form a bit line contact hole; Forming spacers on sidewalls of the bit line contact holes; Embedding a conductive layer pattern and a second nitride layer in the bit line contact hole; And forming a fourth interlayer insulating film on the upper surface of the entire structure.

(실시예)(Example)

이하, 본 발명에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 2는 본 발명에 따른 반도체소자의 제조방법에 있어서, 비트라인과 비트 라인 콘택을 도시한 레이아웃도이다.2 is a layout diagram illustrating a bit line and a bit line contact in the method of manufacturing a semiconductor device according to the present invention.

도 3a 내지 도 3f는 본 발명에 따른 반도체소자의 제조방법에 있어서, 도 2의 Ⅲ-Ⅲ 선에 따른 공정단면도이다.3A through 3F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention, taken along line III-III of FIG. 2.

도 4는 본 발명에 따른 반도체소자의 제조방법에 있어서, 도 2의 Ⅳ-Ⅳ 선에 따른 단면도이다. 4 is a cross-sectional view taken along line IV-IV of FIG. 2 in the method of manufacturing a semiconductor device according to the present invention.

본 발명에 따른 반도체소자의 레이아웃도는, 도 2의 Ⅲ-Ⅲ 선에 따른 단면도를 참조하여 설명하면, 일정간격을 두고 다수의 비트라인(40)이 배열되어 있고, 비트라인(40)사이에 콘택플러그(35)가 배열되며, 콘택프러그(35)의 중앙부분이 비트라인(40)과 오버랩되어 상호 접속되어 있다.Referring to the layout of the semiconductor device according to the present invention with reference to the cross-sectional view taken along the line III-III of Fig. 2, a plurality of bit lines 40 are arranged with a predetermined interval, between the bit lines 40 The contact plugs 35 are arranged, and the center portions of the contact plugs 35 are overlapped with the bit lines 40 to be interconnected.

또한, 상기 도 2의 레이아웃도를 참조하여 본 발명에 따른 반도체소자의 제조방법을 설명하면, 먼저 도 3a에 도시된 바와같이, 먼저 반도체기판 (31)상에 제1 층간산화막(33)을 증착한후 이를 선택적으로 패터닝하여 플러그 콘택홀(미도시) 을 형성한다.In addition, referring to the layout of FIG. 2, a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention will be described. First, as shown in FIG. 3A, a first interlayer oxide film 33 is first deposited on a semiconductor substrate 31. This is then selectively patterned to form a plug contact hole (not shown).

그다음, 상기 플러그콘택홀(미도시)내에 폴리실리콘을 증착하여 콘택플러그(35)을 형성한후 전체 구조의 상면에 제2층간산화막(37)과 제1질화막(39) 및 제3층간산화막(41)을 순차적으로 증착한다. 이때, 상기 제1질화막(39)은 약 100 내지 1000 Å 두께로 증착한다.Next, after forming the contact plug 35 by depositing polysilicon in the plug contact hole (not shown), the second interlayer oxide film 37, the first nitride film 39, and the third interlayer oxide film ( 41) is deposited sequentially. In this case, the first nitride film 39 is deposited to a thickness of about 100 to 1000 mm 3.

이어서, 상기 절연막(41)상에 감광물질을 도포한후 이를 포토리소그라피 공정기술에 의한 노광 및 현상공정을 거쳐 선택적으로 제거하여 비트라인영역을 한정하는 제1감광막패턴(43)을 형성한다.Subsequently, after the photosensitive material is coated on the insulating layer 41, the photosensitive material is selectively removed through an exposure and development process using a photolithography process technology to form a first photoresist pattern 43 defining a bit line region.

그다음, 도 3b에 도시된 바와같이, 상기 제1감광막패턴(43)을 마스크로 상기 제3층간산화막(41)을 선택적으로 제거한후 상기 제1감광막패턴(43)을 제거한다.3B, the third interlayer oxide film 41 is selectively removed using the first photoresist pattern 43 as a mask, and then the first photoresist pattern 43 is removed.

이어서, 도 3c에 도시된 바와같이, 전체 구조의 상면에 상기 셀부의 콘택플러그(35) 영역만을 노출시키는 제2감광막패(45)을 형성한후 이를 마스크로 상기 콘택플러그(35)상측에 있는 제1질화막(39) 및 제2층간산화막(37)만 선택적으로 제거하여 비트라인 콘택홀(47)을 형성한후 제2감광막패턴(45)을 제거한다. 즉, 셀부의 콘택플러그 및 페리부의 활성영역과 비트라인간의 접촉을 위한 비트라인콘택을 위한 포토/식각공정을 실시한다. 이때, 상기 제1질화막(39)은 비트라인용 라인 형태의 홀 식각시에 식각정지막 역할을 한다.Subsequently, as shown in FIG. 3C, the second photoresist layer 45 exposing only the contact plug 35 region of the cell portion is formed on the upper surface of the entire structure, and then the mask is disposed on the contact plug 35 with the mask. Only the first nitride layer 39 and the second interlayer oxide layer 37 are selectively removed to form the bit line contact hole 47, and then the second photoresist layer pattern 45 is removed. That is, a photo plug / etch process is performed for the contact plug of the cell portion and the bit line contact for contact between the active region and the bit line of the ferry portion. In this case, the first nitride layer 39 serves as an etch stop layer at the time of etching the bit line.

그다음, 도 3d에 도시된 바와같이, 상기 전체 구조의 상면에 자기정렬 콘택 공정을 위한 질화막을 증착한후 에치백하여 상기 비트라인콘택홀(47)측벽에 스페이 서(49)를 형성한후 비트라인콘택홀(47)을 포함한 전체 구조의 상면에 도전막을 증착하여 비트라인콘택홀(47)을 매립하고 이어 도전막을 에치백하여 상기 비트라인콘택홀(47)내에 도전막패턴(51)을 형성한다. Next, as shown in FIG. 3D, a nitride film for a self-aligned contact process is deposited on the upper surface of the entire structure and then etched back to form a spacer 49 on the sidewall of the bit line contact hole 47. A conductive film is deposited on the upper surface of the entire structure including the line contact hole 47 to fill the bit line contact hole 47, and then etch back the conductive film to form a conductive film pattern 51 in the bit line contact hole 47. do.

이어서, 도 3e에 도시된 바와같이, 상기 도전막패턴(51)을 포함한 전체 구조의 상면에 비트라인 하드마스크용 제2질화막(53)을 증착한다. 이때, 상기 제2질화막(53)은 약 300 내지 600 Å의 두께를 사용한다. Subsequently, as illustrated in FIG. 3E, a second nitride film 53 for bit line hard mask is deposited on the upper surface of the entire structure including the conductive film pattern 51. In this case, the second nitride film 53 uses a thickness of about 300 to 600 mm 3.

그다음, 도 3f에 도시된 바와같이, 상기 제2질화막(53)을 CMP공정을 통해 평탄화시켜 상기 비트라인콘택홀(47)내에만 남도록 한다.3F, the second nitride film 53 is planarized through the CMP process so as to remain only in the bit line contact hole 47.

이어서, 메모리 콘택 형성을 위해 전체 구조의 상면에 제4층간산화막(55)을 증착한후 도면에는 도시하지 않았지만 이를 선택적으로 패터닝하여 스토리지노드 콘택플러그(미도시)를 노출시키는 메모리콘택(미도시)을 형성한다.Subsequently, after depositing the fourth interlayer oxide film 55 on the upper surface of the entire structure to form a memory contact, the memory contact (not shown) which selectively exposes the storage node contact plug (not shown) by selectively patterning the interlayer oxide film 55 is not shown in the figure. To form.

한편, 도 4는 도 2의 Ⅳ-Ⅳ선에 따른 반도체소자의 단면도로서, 일정간격을 두고 형성된 비트라인과 이들사이에 배열된 콘택플러그를 도시한 단면도이다.4 is a cross-sectional view of a semiconductor device taken along a line IV-IV of FIG. 2 and illustrates a bit line formed at a predetermined interval and contact plugs arranged therebetween.

상기에서 설명한 바와같이, 본 발명에 따른 반도체소자의 제조방법에 의하면, 산화막을 이용하여 갭매립을 먼저 진행한후 라인 형태의 홀내에 비트라인을 형성하므로써 보이드가 없는 구조를 통해 스토리지노드 폴리 증착공정에서의 브릿지 불량을 해결할 수 있으며, 메모리 콘택 자기정렬콘택 공정 적용시에 기존 공정과 대비하여 자기정렬콘택 마진 확보가 가능하다.As described above, according to the method of fabricating a semiconductor device according to the present invention, a process of depositing a storage node through a void-free structure by forming a bit line in a hole in a line shape after first filling a gap using an oxide film It is possible to solve the bridge failure in the process and to secure the self-aligned contact margin compared to the existing process when applying the memory contact self-aligned contact process.

또한, 스페이서 질화막 두께를 조절하므로써 비트라인 CD를 자유롭게 조절가 능하다.In addition, the bit line CD can be freely adjusted by adjusting the thickness of the spacer nitride film.

한편, 본 발명은 상술한 특정의 바람직한 실시예에 한정되지 아니하며, 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진 자라면 누구든지 다양한 변경 실시가 가능할 것이다.On the other hand, the present invention is not limited to the above-described specific preferred embodiments, and various changes can be made by those skilled in the art without departing from the gist of the invention claimed in the claims. will be.

Claims (6)

반도체기판 상에 제1층간산화막을 형성하고, 이를 선택적으로 패터닝한후 패터닝한 부분에 콘택플러그를 형성하는 단계;Forming a first interlayer oxide film on the semiconductor substrate, selectively patterning the first interlayer oxide film, and forming a contact plug on the patterned portion; 상기 콘택플러그를 포함한 제1층간산화막 상에 제2층간산화막과 제1질화막 및 제3층간산화막을 적층하는 단계;Stacking a second interlayer oxide film, a first nitride film, and a third interlayer oxide film on the first interlayer oxide film including the contact plug; 상기 제3층간산화막과 제1질화막 및 제2층간산화막을 선택적으로 제거하여 비트라인콘택홀을 형성하는 단계;Selectively removing the third interlayer oxide layer, the first nitride layer, and the second interlayer oxide layer to form a bit line contact hole; 상기 비트라인콘택홀 측벽에 스페이서를 형성하는 단계;Forming spacers on sidewalls of the bit line contact holes; 상기 비트라인콘택홀내에 도전막패턴과 제2질화막을 매립하는 단계; 및Embedding a conductive layer pattern and a second nitride layer in the bit line contact hole; And 상기 전체 구조의 상면에 제4층간절연막을 형성하는 단계를 포함하여 구성되는 것을 특징으로하는 반도체소자의 제조방법.And forming a fourth interlayer insulating film on the upper surface of the entire structure. 제1항에 있어서, 상기 도전막패턴은 에치백공정에 통해 형성하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the conductive film pattern is formed through an etch back process. 제1항에 있어서, 상기 제2질화막은 CMP공정을 통해 형성하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the second nitride film is formed through a CMP process. 제1항에 있어서, 제1질화막은 100 내지 1000 Å 두께로 형성하는 것을 특징 으로하는 반도체소자의 제조방법.The method of claim 1, wherein the first nitride film is formed to a thickness of 100 to 1000 GPa. 제1항에 있어서, 상기 제2질화막은 300 내지 600 Å 두께로 형성하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the second nitride film is formed to a thickness of 300 to 600 kHz. 제1항에 있어서, 상기 스페이서는 질화막으로 형성하는 것을 특징으로하는 반도체소자의 제조방법.The method of claim 1, wherein the spacer is formed of a nitride film.
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