KR19990072967A - Manufacture of flip-chip devices - Google Patents

Abstract

The present invention discloses a process for application to lower bump metallization (UBM) for solder bump interconnection on interconnected substrates. This process uses a lift-off technique to define the UBM, which has improved edge resolution as a result of photocuring of the photoresist after lithographic patterning.

Description

Manufacture of flip-chip devices

The present invention relates to a method of manufacturing a multi-chip module (MCM) flip-chip device and to a technique for forming solder wettable metal contacts for flip chip bonding.

Typical states of conventional semiconductor device packaging typically include high density interconnects in which unpackaged integrated circuit (IC) chips or exposed die are both mechanically and electrically connected onto a single substrate of silicon, ceramic, or epoxy-glass laminate. Use connected structures. The choice of interconnect technology, substrate material, and bonding process steps, such as cleaning, all play an important role in defining the overall assembly technology, affecting MCM cost and reliability. Various interconnect technologies have been used in the microelectronics industry to assemble exposed dies on MCM substrates. These substrates act as "fabrics" and as structural supports for electrical interconnections between ICs. Typically MCMs are assembled using one of several known techniques, namely wire bonding, tape automated bonding (TAB), and flip-chip soldering.

In general, the design of an MCM package depends on the manufacturer's specific capabilities, the MCM structure, the relative cost of the material, and the required I / O structure and density. In other words, the choice of interconnect technology and cleaning process plays an important role in defining the assembly process required for high yield and product reliability.

The most common and nominally lowest cost interconnect technology is wire bonding. However, wire bonding connections have the disadvantage of having many large footprints, which results in large substrates and inevitably a dense MCM. As is well known in electronics manufacturing, the increased size of any feature in the assembly results in a directly increased cost. Moreover, in an MCM module, increasing the size of the module increases the mutual coupling length, leading to increased lead inductance and resistance, and a decrease in electronic performance. Moreover, typical wire bonding devices, such as stitch couplers, make the bonds one at a time and even time-consuming operations are used today even with improved high speed couplers.

TAB binding has the advantage of smaller footprint and partial batch processing. However, TAB assemblies generally require different pores for each IC design and add significant cost to this bonding technique. Moreover, TAB assemblies are limited to the interconnection of peripheral I / O arrays that limit IC design flexibility. Peripheral I / O pads typically have a larger pitch and therefore lower overall I / O density than the area I / O arrangements that can be used with flip-chip solder bonding. In addition, TAB coupled interconnects typically exhibit greater capacitance and larger parasitic inductance than flip-chip coupled interconnects.

Flip-chip bonding is now recognized to provide the best performance at the largest I / O densities in both peripheral or regional I / O arrays. Moreover, flip-chip bonding is a batch assembly process that inherently promotes high speed, high throughput manufacturing methods. However, for various reasons, flip-chip MCM assemblies are typically considered the most expensive of the known assembly techniques. This is particularly true for high performance MCM designs that often use multilayer co-fired ceramic (MCM-C), or deposited thin film ceramic or silicon substrates (MCM-D) as interconnect substrates. Lower cost substitutes are typically printed wiring boards, ie epoxy-glass fiber laminates. However, as I / O counts and densities increase in conventional assembly conditions, silicon becomes cost competitive and represents an interconnect substrate of choice for high performance applications.

Assembly of electronic packages using flip-chip technology is particularly dominant in the manufacture of computers and computer peripherals. The technology is also widely used in the assembly of electronic and photonics packages for communication network products. The essence of flip-chip assemblies is to "upside-down" a semiconductor substrate onto an interconnect substrate, such as a silicon wafer, a ceramic substrate, or a printed circuit board. The attachment means is typically solder in the form of balls, pads, or bumps (hereinafter collectively referred to as bump primers). Solder bumps can be applied to semiconductor chips or interconnect substrates, or both. In the bonding operation, the chip is placed in contact with the substrate and the solder is heated to reflux the solder and attach the chip on the substrate. For successful bonding, the area where the solder is bonded needs to be wetted by the solder.

The metal interconnect pattern typically used for integrated circuit boards or cards is aluminum. Techniques for soldering directly to aluminum have been tried, but it is well known that aluminum is not a desirable material for soldering. As a result, industry practice is to apply a metal coating on aluminum contact pads and apply solder bumps or pads to the coating. Metal coatings are typically referred to as lower bump metallization (UBM).

The metal or metals used in the UBM technique should adhere well to aluminum, be wettable by typical tin solder compositions, and be highly conductive. Structures meeting these requirements are complexes of chromium and copper. Chromium is first deposited and attached to aluminum, and copper is applied over chromium to provide a solder wettable surface. Chromium is known to adhere well to various materials such as organic materials as well as inorganic materials. Thus, chromium adheres well to metals such as copper and aluminum, as well as to dielectric materials such as SiO ₂ , SINCAPS, polyimide, and the like commonly used in IC processing. However, solder alloys dissolve copper and remove moisture from chromium. Thus, a thin layer of copper just above the chromium will dissolve in the molten solder, and the solder will then be dehydrated from the chromium layer. In order to ensure the integrity of the interface between the solder and the UBM, a complex or alloy layer of chromium and copper is typically used between the chromium layer and the copper layer.

Since the layers are sputtered as in the prior art, several options for depositing them are conveniently available. This layer can be sputtered from the alloy target. It can be sputtered using a chromium target and then converted to a copper target. Or it can be sputtered using separate chromium and copper targets and transitions between these two targets. The latter choice produces a layer with a sorted composition, which is the preferred technique.

In forming such a structure, the accepted practice described is to use an additional process for selective deposition of the complex layer. Additional processes are known and are typically implemented using lift-off techniques. However, the lift-off process is inherently incompatible with the desired technique for depositing UBM, such as sputtering. In sputtering, the substrate UBM reaches temperatures in excess of 100 ° C. At these temperatures, the photoresist used in the lift-off process is dimensionally deformed and the edge acuity of the photoresist pattern is deteriorated. Moreover, in order to improve the adhesion of the UBM to the underlying substrate, it is customary to back sputter the surface to make it rough. In this process, the substrate and photoresist are also heated to temperatures above 100 ° C., adding an incompatibility to the process.

In accordance with the present invention, improvements are made in processes employing sub-bump ionization which allows for the use of relatively high temperatures associated with conventional processing steps such as sputtering, back sputtering and ion milling. This is accomplished by treating the photoresist used for lift-off to dimensional stabilize the pattern before the high temperature treatment. This treatment includes actinic crosslinking after the photoresist is patterned by lithography.

1 is a schematic representation of an interconnected substrate and a portion of a solder bumped flip chip just prior to assembling the chip on the substrate.

2 is a schematic representation of a flip-chip with solder bump bond sites provided in lower bump metallization.

3-7 are schematic diagrams of exemplary processing steps used to produce the lower bump metallization pattern of FIG. 2 in accordance with the present invention.

* Explanation of symbols for the main parts of the drawings

11: interconnected substrate 12: contact pad

13: flip chip 14: I / O contact pad

15, 32: solder bumps 21, 31: UBM layer

22: polyimide protective layer 24: contact pad

26 photoresist layer 27 window

According to the manufacturing method of the semiconductor device of the present invention,

The metal layer on the substrate,

a. Applying a photoresist layer on the substrate,

b. Patterning the photoresist to form windows in the photoresist,

c. Depositing a metallization layer on the patterned photoresist, and

d. A method of manufacturing a semiconductor device, wherein the metallization layer is patterned by lift-off by removing the photoresist layer from the substrate and patterned by leaving portions of the metallization in the windows. Exposing the patterned photoresist to a flux of UV radiation prior to depositing the layer.

Referring to FIG. 1, a cutout of a silicon interconnected substrate 11 is shown with contact pads 12 interconnected with runners (not shown) on the interconnected substrates. Flip chips 13 are shown with an array of I / O contact pads 14 each having solder bumps 15. The overall interconnect substrate may comprise several flip-chip portions or may be an intermediate interconnect substrate supporting the illustrated chip. The techniques generally described herein and the present invention cover a wide range of solder installation devices and apply to ceramic substrates and other interconnect substrates such as epoxy printed wiring boards. Those skilled in the art will appreciate that solder bumps may be applied to contact contact pads on flip-chips or pads on interconnected substrates or both. In the following description of the invention, solder bumps are applied to flip-chips.

As mentioned above, the contact pads on the two elements to be solder bonded have UBMs. UBM layers are thinner than solder bumps and contact pads and are not shown in FIG. 1. UBM is shown in FIG. 2 in FIG. 2 shows a typical polyimide protective layer 22 and contact pad 24 portion covering an aluminum runner (not shown). The contact pads may be aluminum, copper or other suitable metallization material. These pads are typically formed on the field oxide of an IC (not shown), and a protective final polyimide coating 22 is deposited over the contact pads. Contact windows are preferably formed in the polyimide layer by a photodefinition process. Lower bump metallization layer 21 is formed in the polyimide window. These aspects of IC processing are well known. The UBM layer 21, shown as a single layer but described above, is preferably a complex layer of Cr and Cu. Alternatively, this layer may be Ti-Pd-Au, Ti-Ni-Au, or other suitable material.

The process steps used to produce the structure of FIG. 2 according to the invention are shown as FIGS. 3-7.

3 shows a flip chip 13 before formation of the UBM. Referring to FIG. 3, photoresist layer 26 is spin coated onto flip-chip substrate 13 using conventional means. The photoresist is patterned by lithography and the windows 27 are opened over the contact pad array as shown in FIG. 4. The photoresist process used is one of several conventional processes known for lift-off. The windows in the photoresist pattern are preferably reintroduced at opposite angles to provide good edge resolution after lift-off. To create opposite angle windows, double-level or triple-level resists are often used to form undercuts after development. Another option requiring only a single photoresist level is to mix the photoresist with additives to reverse the tone of the resist. Windows with opposite angles are formed. For a description of this photoresist technique, see H. Klose, R. Sigush, W. Arden, "Image Reversal of Positive Photoresist: Characterization and Modeling", IEEE Transactions on Electron Devices, Vol. 32nd Edition, 9, September 1985].

After patterning the windows, the remaining photoresist material is excessively exposed to light. This ray is shown in FIG. 4 by arrow 28. The light source can be any source of UV rays. This ray may be the same light source used to expose the pattern. However, the dose is substantially greater by a factor of at least 5, and preferably as high as at least 20 factors. This dose is measured in terms of total accumulated flux and is typically in the range of 10-200 joules / cm ² . This light causes the formation of free radicals in a manner similar to pattern exposure, but due to the high dose the number of free radicals is much larger, resulting in significantly more crosslinks.

As a result of excessive crosslinking from large UV doses, the pattern cures and becomes strong enough to withstand subsequent high temperature treatments without significant dimensional deformation. In this context, the "hot" regime exceeds 100 ° C. A detailed description of the curing process and its associated chemical properties is described in Mohondro et al., “Photostabilization: The Process of Improvement”, Future Fab International, pp. 235-247. It is incorporated herein by reference.

The post lithographic light treated wafer is then placed in a sputtering apparatus and UBM is deposited. As noted above, preferred UBMs are multilayer complexes of Cr and Cu. However, it will be appreciated that this is just one of several suitable UBM materials, and that any of these may be applied in accordance with the teachings of the present invention.

Multiple layers for UBM are deposited sequentially to form Cr-Cr / Cu-Cu structures of the composite layers. The composite UBM is shown in FIG. 5 as a single layer 31. The UBM layer is deposited on top of the contact pads 24 exposed to the windows and the photoresist layer 26 as shown.

In a preferred embodiment, the individual layers are sputtered in a sputtering apparatus containing both a chromium target and a copper target. Sputtering techniques are well known and need not be described in detail.

The first layer is chromium having a thickness of 500-5000 mm 3, preferably 1000-3000 mm 3. Chromium not only adheres well to aluminum contacts 24 but also to dielectric layers present in the structure. Chromium is also a refractory material and forms an aluminum contact and wear resistance interface. The second layer is a thin transition layer of Cr / Cu that provides a solder wettability and metallurgically safe interface between the chromium layer and the sequentially formed copper layer. As noted above, the layer 31 is preferably formed by sputtering and transition between targets in the apparatus, with both chromium and copper targets. This results in a co-sputtered layer having a varying composition between pure chromium and pure copper. The thickness of the transition layer is in the range of 1000-5000 mm 3, preferably 2000-3000 mm 3.

The next layer is a copper layer with a thickness of 1000-10000 mm 3, preferably 2000-6000 mm 3. The copper layer can be wetted with the solder material conventionally used for solder bumps. The melting point of most copper eutectic mixtures with tin solder is relatively low, and at soldering temperatures the surface of the copper layer dissolves in solder bumps that form a physically and electrically safe bond. Even if all the copper is dissolved in the solder layer, the solder will still adhere and wet the Cr / Cu layer.

Any gold layer can be applied to the surface of the copper layer to inhibit oxidation of the copper surface. Any gold layer has a thickness of 500-3000 mm 3, preferably 1000-2000 mm 3.

After deposition of the UBM layer 31, unwanted portions of the layer are removed using lift-off by dissolving the photoresist layer in a photoresist solvent such as acetone. The resulting structure after lift-off is shown in FIG. 6.

Solder bumps 32 are then deposited over the UBM layer by appropriate techniques such as deposition. Examples of solder compositions that can be used successfully in the process are as follows:

I II III

Sn 5 63 95

Pb 95 37 0

Sb 0 0 5

In order to represent the dimensional stabilization process of the present invention, the following processes were followed.

1 g of imidazole was mixed with Hoechst AZP-4620 positive photoresist. The mixture was heated to 40 ° C., removed from the hot plate and stirred without heating for 45 minutes. The solution was spin-coated on a silicon interconnect substrate at 5000 RPM for 40 seconds at room temperature. The resulting photoresist thickness was 5.5 μm. Since the UBM layer is typically 0.5-1.0 μm, the photoresist layer should be substantially thicker than the UBM layer to ensure proper lift-off, eg thicker than 0.2 μm.

The wafer is then baked for 2 minutes on a hot plate at 90 ° C. The resulting wafer was placed in a lithographic apparatus and exposed to the pattern by actinic radiation at 465 nm with a total light energy of 400 mj / cm ² . The exposed wafer was then baked at 105 ° C. for 30 minutes and then the entire wafer surface was overexposed to 465 nm light with a total energy of 1500 mj / cm ² . The lithographic pattern was then dissolved in a 400K developer (3: 1) for 4.5 minutes, rinsed in DI water and dried. Post lithographic light treatment is overexposing the wafer to 365 nm light with an overall accumulated energy of 75 j / cm ² . The resulting pattern was found to be solid and was not essentially affected by subsequent heat treatment.

The additive used in the positive photoresist in this example was imidazole, an organic base. However, other bases may be used.

In the above description of the method of the invention, solder bumps have been proposed as specific means for attaching flip chips to interconnect substrates. Other forms of solder such as solder paste may be used. Two bonded substrates typically have a UBM, but some substrates, such as copper printed circuit boards, have a bonding area that may not require UBM if the method of the present invention can be applied only to one bonded substrate. .

As described above, the lift-off technique of the present invention is described in the making of solder bump patterns for flip chip bonding. However, those skilled in the art will understand that the improved dimensional safety produced by treating lift-off resists using the techniques of the present invention applies to other lift-off metallization processes.

Many further modifications of the invention will occur to those skilled in the art. Any deviation from the specific subject matter of the present invention, which basically depends on the principles of the invention and the equivalents made through advances in the art, is deemed to be within the scope of the invention as described herein and claimed. proper.

Claims (23)

The metal layer on the substrate, a. Applying a photoresist layer on the substrate, b. Patterning the photoresist to form windows in the photoresist, c. Depositing a metallization layer on the patterned photoresist, and d. 10. A method of fabricating a semiconductor device, the method comprising patterning the metallization layer by lift-off by removing the photoresist layer from the substrate and leaving portions of the metallization in the windows. Exposing the patterned photoresist to a flux of UV radiation prior to depositing the metallization layer. The method of claim 1, wherein the metallization layer is deposited by sputtering. The method of claim 2, wherein the photoresist is heated to a temperature of at least 100 ° C. during processing. The metallization layer on the substrate, a. Spin coating a photoresist layer having a first thickness t ₁ on the substrate, b. Exposing the photoresist layer to a pattern of actinic radiation having a first flux level f ₁ , c. Developing an exposed layer of photoresist to form an opening in the photoresist layer exposing portions of the substrate, d. exposing the patterned photoresist layer to a flux of actinic radiation having a flux level f ₂ substantially greater than f ₁ , e. Sputtering a metallization layer having a second thickness t ₂ substantially less than t ₁ over the photoresist layer, at regular intervals between the metal layers on the substrate and the metal layer on the photoresist layer, the The metallization layer sputtering to form metal layers on the photoresist layer and metal layers on a substrate, f. Removing the photoresist layer and the metal layer on the photoresist layer, and patterning the semiconductor device using a lift-off. The method of claim 4, wherein the substrate is a silicon interconnect substrate. The method of claim 4, wherein f ₂ is at least 5 times larger than f ₁ . 5. The method of claim 4, wherein the actinic radiation in step (d) is UV radiation. A method of fabricating a flip-chip bonded semiconductor device package, wherein the substrate is bonded to another substrate using solder, the substrate having lower bump metallization. a. Applying a photoresist layer on the substrate, b. Patterning the photoresist to form windows in the photoresist, c. Exposing the patterned photoresist to a flux of UV rays, d. Depositing a lower bump metallization layer on the patterned photoresist, e. Patterning the lower bump metallization layer by lift-off, leaving the lower bump metallization layer portions in the windows, and f. Solder-bonding the substrate to another substrate. A method of manufacturing a flip-chip bonded semiconductor device package, wherein a solder bumped substrate is bonded to another substrate, and the solder bumps on the solder bumped substrate have lower bump metallization. a. Applying a photoresist layer on the solder bumped substrate, b. Patterning the photoresist to form windows in the photoresist, c. Exposing the patterned photoresist to a flux of UV rays, d. Depositing a lower bump metallization layer on the patterned photoresist, e. Patterning the lower bump metallization layer by lift-off, leaving the lower bump metallization layer portions in the windows, and f. Depositing the solder bumps on the remaining portion of the lower bump metallization layer. 10. The method of claim 9, wherein the lower bump metallization is deposited by sputtering. 12. The method of claim 10, wherein the lower bump metallization is preceded by back sputtering a solder bumped substrate. 10. The method of claim 9, wherein the flux of UV radiation is in the range of 10-200 J / cm ² . a. Forming a plurality of I / O contact pads on the substrate, bi-spinning a photoresist layer having a first thickness t ₁ on the substrate covering the I / O contact, ii. Exposing the photoresist layer to a pattern of actinic radiation having a first flux level f ₁ , iii. Developing the exposed photoresist layer to form an opening in the photoresist layer that exposes the I / O contact, iv. exposing the patterned photoresist layer to a flux of actinic radiation having a flux level f ₂ substantially greater than f ₁ , v. Sputtering a lower bump metallization layer having a second thickness t ₂ less than t ₁ over the photoresist layer, at regular intervals between the metal layers on the I / O contact and the metal layer on the photoresist layer; A lower bump metallization layer sputtering to form metal layers on the I / O contact and the metal layer on the photoresist layer, vi. Depositing a lower bump metallization layer on the I / O contact by removing the photoresist layer and the metal layer on the photoresist layer, c. Depositing solder on the lower bump metallization layer, and d attaching the substrate to another substrate by heating the solder to bond the substrates together. 14. The method of claim 13, wherein the solder bumped substrate is a silicon interconnect substrate. 14. The method of claim 13, wherein the solder on the lower bump metallization layer comprises solder bumps. The method of claim 13, wherein f ₂ is at least 5 times larger than f ₁ . 14. The method of claim 13, wherein the actinic radiation in step (ii) is UV radiation. 18. The method of claim 17 wherein the actinic rays in step (iv) are UV rays and f ₂ is in the range of 10-200 J. The method of claim 13, wherein the openings are opposite angle openings. 20. The method of claim 19, wherein the photoresist is a positive resist mixed with a base. 14. The method of claim 13, wherein the lower bump metallized sputtering is preceded by back sputtering a solder bumped substrate. The method of claim 13, wherein the photoresist layer is heated to a temperature of at least 100 ° C. during processing. 21. The method of claim 20, wherein said base is imidazole.