KR19990071999A - Multilayer Microwave and Microwave Hybrid Integrated Circuits - Google Patents
Multilayer Microwave and Microwave Hybrid Integrated Circuits Download PDFInfo
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- KR19990071999A KR19990071999A KR1019980704291A KR19980704291A KR19990071999A KR 19990071999 A KR19990071999 A KR 19990071999A KR 1019980704291 A KR1019980704291 A KR 1019980704291A KR 19980704291 A KR19980704291 A KR 19980704291A KR 19990071999 A KR19990071999 A KR 19990071999A
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
본 발명에 따른 다층 마이크로웨이브 및 극고주파(EFH) 하이브리드 집적회로는 적어도 한쪽면상에 위상 금속화 패턴층(2)을 갖는 고정식 고체 유전체판(1)의 다발을 포함하고, 상기 유전체판(1)의 리세스(6)속에 배치되어 고착제(7)에 의해 고착되는 후크-업 와이어드방식의 순수 반도체칩(3)을 구비한다. 상기 칩(3)의 접합 패드(4)는 상기 위상 금속화 패턴층(2)에 전기적으로 연결된다. 상기 칩(3)을 위한 리세스(6)는 상기 칩(3)이 장착되는 유전체판(1)의 적어도 한쪽면상에 형성된다. 상기 리세스(6)의 깊이는 상기 칩(3)의 표면이 상기 리세스(6)가 형성되는 상기 유전체판(1)의 표면과 동일평면상에 위치하도록 선택되고, 상기 리세스(6)의 측벽과 상기 칩(3)의 측벽사이의 간격은 1-180㎛이고, 상기 반도체칩의 표면과 상기 칩(3)이 장착되는 상기 유전체판(1)과 관련한 인접 유전체판(1)의 표면사이의 간격은 1-100㎛이다.A multilayer microwave and microwave high frequency (EFH) hybrid integrated circuit according to the present invention comprises a bundle of stationary solid dielectric plates 1 having a phase metallization pattern layer 2 on at least one side, wherein the dielectric plate 1 It is provided with a pure semiconductor chip (3) of the hook-up wire is arranged in the recess (6) of the hook is fixed by the fixing agent (7). The bonding pads 4 of the chip 3 are electrically connected to the phase metallization pattern layer 2. A recess 6 for the chip 3 is formed on at least one side of the dielectric plate 1 on which the chip 3 is mounted. The depth of the recess 6 is selected such that the surface of the chip 3 is coplanar with the surface of the dielectric plate 1 on which the recess 6 is formed, and the recess 6 The distance between the sidewalls of and the sidewalls of the chip 3 is 1-180 μm, the surface of the semiconductor chip and the surface of the adjacent dielectric plate 1 with respect to the dielectric plate 1 on which the chip 3 is mounted. The interval between them is 1-100 μm.
Description
이미 기술적으로 공지된 고주파 3D 집적회로 모듈(SU,A,1,679664)은 사실상 10개의 강성 유전체 마이크로 스트립판 다발을 포함하는 3D 하이브리드 집적회로이다. 상기 회로의 구조는, 상기 3D 하이브리드 집적회로의 강성 유전체판사이에 삽입되는 폼 유전체(foam dielectric)로 이루어진 공간속에 관통구멍을 형성하고, 상기 관통구멍속에 반도체 장치를 배치하기 때문에, 순수 반도체칩을 포함하도록 설계된다.The already known high frequency 3D integrated circuit module (SU, A, 1, 679 664) is actually a 3D hybrid integrated circuit comprising 10 rigid dielectric microstrip plate bundles. The circuit structure includes a pure semiconductor chip because the through hole is formed in a space made of a foam dielectric inserted between the rigid dielectric plates of the 3D hybrid integrated circuit, and the semiconductor device is disposed in the through hole. It is designed to.
전술한 형태의 구조는 폼-유전체 공간의 필요성으로 인하여, 불필요하게 높은 전기 및 중량-크기 특성을 갖는다.Structures of the type described above have unnecessarily high electrical and weight-size properties due to the need for foam-dielectric space.
공지된 또다른 형태의 고주파 3D 집적회로(SU,A,1,700,789)는 금속 프레임에 고정된 강성 유전체판 다발을 포함하는 다층 3D 집적회로이다. 순수 반도체칩은, 상기 유전체판 다발의 두 번째 유전체판의 길이가 더 길어짐에 따라 칩타입의 반도체 장치가 장착될 수 있는 매 두 개의 긴 유전체판사이에 자유 공간이 확립되기 때문에, 상기 모듈속에 포함된다.Another known type of high frequency 3D integrated circuit (SU, A, 1,700, 789) is a multilayer 3D integrated circuit comprising a rigid dielectric plate bundle secured to a metal frame. A pure semiconductor chip is included in the module because as the length of the second dielectric plate of the dielectric plate bundle becomes longer, a free space is established between every two long dielectric plates on which the chip type semiconductor device can be mounted. .
전술한 형태의 구조에서는, 상기 순수 반도체칩의 접합 패드를 상호연결하는 긴 와이어 도체가 사용됨은 물론, 긴 연결 와이어 리드가 사용된다. 그러한 긴 도체의 사용은 상기 칩이 상기 유전체판상의 어떤 위치에도 장착될 수 없다는 사실에 의해 결정됨으로써, 상기 집적회로의 전기적 특성이 저하된다.In the above-described structure, a long wire conductor is used as well as a long connection wire lead for interconnecting the bonding pads of the pure semiconductor chip. The use of such long conductors is determined by the fact that the chip cannot be mounted anywhere on the dielectric plate, thereby degrading the electrical characteristics of the integrated circuit.
일부 유전체판을 다른 유전체판에 비해 긴 것을 배치함으로써, 중량-크기 특성에 악영향이 미치고, 상기 칩주위에 큰 기적(氣積)이 존재함으로써, 상기 반도체칩으로 부터 열 확산의 조건이 악화된다.By disposing some dielectric plates longer than other dielectric plates, the weight-size characteristics are adversely affected, and a large miracle exists around the chip, thereby deteriorating the condition of heat diffusion from the semiconductor chip.
본 발명은 전자 공학, 특히 다층 마이크로웨이브 및 극고주파 하이브리드 집적회로(multilayer microwave and extremely high frequency hybrid integrated circuit)에 관한 것이다.FIELD OF THE INVENTION The present invention relates to electronics, in particular multilayer microwave and extremely high frequency hybrid integrated circuits.
도 1은 본 발명에 따른 다층 마이크로웨이브 및 극고주파(EFH) 하이브리드 집적회로를 나타낸 종단면도이다.1 is a longitudinal cross-sectional view illustrating a multilayer microwave and extremely high frequency (EFH) hybrid integrated circuit according to the present invention.
따라서, 본 발명의 목적은 상기 종래기술에 따른 문제점을 극복하고, 전기 및 중량-크기 특성을 향상시키고 상기 칩으로 부터 열확산 조건을 향상시킬수 있는 후크-업 와이어드(hook-up wired)방식의 순수 반도체칩을 구비하는 다층 마이크로웨이브 및 극고주파(EHF) 하이브리드 집적회로를 제공하는데 있다.Therefore, an object of the present invention is to overcome the problems according to the prior art, a hook-up wired pure semiconductor capable of improving electrical and weight-size characteristics and improving thermal diffusion conditions from the chip. To provide a multilayer microwave and extremely high frequency (EHF) hybrid integrated circuit having a chip.
상기 목적을 달성하기 위해, 본원 발명의 일면에 따라, 적어도 한쪽면상에 위상 금속화 패턴층을 갖는 고정식 고체 유전체판의 다발을 포함하고, 상기 위상 금속화 패턴층에 전기적으로 연결되는 접합 패드를 갖고 상기 유전체판의 리세스속에 배치되어 고착제에 의해 고착되는 후크-업 와이어드방식의 순수 반도체칩을 구비하는 다층 마이크로웨이브 및 극고주파(EFH) 하이브리드 집적회로가 제공되는데, 상기 다층 마이크로웨이브 및 극고주파(EFH) 하이브리드 집적회로에 있어서, 상기 순수 반도체칩용의 상기 리세스는 상기 칩이 장착되는 상기 유전체판의 적어도 한쪽면상에 형성되고, 상기 리세스의 깊이는 상기 반도체칩의 표면이 상기 리세스가 형성되는 상기 유전체판의 표면과 동일평면상에 위치하도록 선택되고, 상기 리세스의 측벽과 상기 순수 반도체칩의 측벽사이의 간격은 1-180μm이고, 상기 반도체칩의 표면과 상기 순수 반도체칩이 장착되는 상기 유전체판과 관련한 인접 유전체판의 표면사이의 간격은 1-100μm인 것을 특징으로 한다.In order to achieve the above object, according to one aspect of the present invention, it comprises a bundle of a stationary solid dielectric plate having a phase metallization pattern layer on at least one side, having a bonding pad electrically connected to the phase metallization pattern layer A multilayer microwave and ultra high frequency (EFH) hybrid integrated circuit having a pure semiconductor chip of a hook-up wired type disposed in a recess of the dielectric plate and fixed by a fixing agent is provided. The multilayer microwave and ultra high frequency ( EFH) In the hybrid integrated circuit, the recess for the pure semiconductor chip is formed on at least one side of the dielectric plate on which the chip is mounted, and the depth of the recess is formed by the surface of the semiconductor chip. Selected to be coplanar with the surface of the dielectric plate, the sidewalls of the recess and the net The spacing between the side walls of the semiconductor chip is 1-180μm, and the distance between the adjacent surfaces of the dielectric plate with respect to said dielectric plate on which the semiconductor chip and the pure surface of the semiconductor chip mounted is characterized in that 1-100μm.
상기 유전체판의 리세스는 금속화되고, 상기 리세스의 저부는 상기 유전체판의 대향면상에 형성된 위상 금속화 패턴층에 전기적으로 연결되는 금속화 구멍을 구비하는 한편, 상기 리세스내의 상기 순수 반도체칩을 접합하기 위한 고착제는 전기 및 열 전도물질로 이루어진다.The recess of the dielectric plate is metallized, and the bottom of the recess has a metallization hole electrically connected to a phase metallization pattern layer formed on an opposite surface of the dielectric plate, while the pure semiconductor in the recess is provided. Fixing agents for bonding chips consist of electrical and thermally conductive materials.
상기 유전체판의 대향면상의 상기 칩 아래에서 상기 리세스가 상기 순수 반도체칩을 수용하는 상기 유전체판에 인접한 유전체판의 표면상에는, 열전도 물질로 채워지고 히이트 싱크와 연결되며 5-950μm의 깊이와 상기 순수 반도체칩의 치수보다 큰 길이 및 폭을 갖는 추가 리세스가 형성된다.Under the chip on the opposite side of the dielectric plate, on the surface of the dielectric plate adjacent to the dielectric plate that receives the pure semiconductor chip, the recess is filled with a thermally conductive material and connected to the heat sink and has a depth of 5-950 μm. Additional recesses are formed with lengths and widths larger than the dimensions of the pure semiconductor chip.
상기 유전체판의 표면에 형성된 리세스를 특허청구범위에 기술된 것과 같은 일정한 방법으로 구성하고, 상기 리세스내에 상기 후크-업 와이어드방식의 순수 반도체칩을 배치함으로써, 도체의 길이가 줄어들어, 상기 집적회로의 전기적 특성 및 그 중량-크기 특성이 향상된다.By constructing the recess formed on the surface of the dielectric plate in a constant manner as described in the claims, and placing the hook-up wired pure semiconductor chip in the recess, the length of the conductor is reduced and the integration The electrical characteristics of the circuit and its weight-size characteristics are improved.
전기 및 열 전도물질로 채워진 상기 리세스를 금속화하고, 그 저부에 금속화 구멍을 형성함으로써, 열확산 조건이 향상된다.Thermal diffusion conditions are improved by metallizing the recesses filled with electrical and thermal conductive materials and forming metallization holes in the bottom thereof.
첨부도면을 참조하여, 실시예를 통해 본 발명이 이하에 상세히 설명된다.With reference to the accompanying drawings, the present invention will be described in detail by way of examples.
첨부 도면에서, 동일한 참조 번호는 동일한 구성요소를 나타낸다.In the accompanying drawings, like reference numerals refer to like elements.
도 1에 도시된 바와같이, 본 발명에 따른 다층 마이크로웨이브 및 극고주파(EFH) 하이브리드 집적회로는, 예컨대, Ti(0.04μm)-Pd(0.2μm)-Au(3μm),또는 Cr(0.04μm)-Cu(1μm,증발-석출됨)-Cu(3μm)-Ni(0.6μm)-Au(3μm,전기화학적으로 석출됨)의 구조로 된 위상 금속화 패턴층 2을 구비하고 Polycor 또는 사파이어로 제조되는 0.5또는 1.0 mm 두께의 고정식 고체 유전체판 1의 다발을 포함한다. 상기 다층 마이크로웨이브 및 극고주파(EFH) 하이브리드 집적회로는 예컨대, 15μm직경의 금제 와이어로 이루어진 전기 접속부 5를 통해 상기 위상 금속화 패턴층 2에 전기적으로 연결되는 접합 패드 4를 갖는, 트랜지스터와 같은 후크-업 와이어드 방식의 순수 반도체칩 3을 구비한다. 트랜지스터 3П325A-5용으로서 0.6×0.6×0.17mm의 크기와 다이오드용으로서 0.5×0.5×0.17mm의 크기를 갖는 상기 유전체판 1의 표면상에는 리세스 6이 형성되고, 상기 후크-업 와이어드 방식의 순수 반도체칩 3은 상기 리세스 6속에 장착되어 예컨대, ЭЧЭ-C 타입의 접착제(Std.Spec.ЬIУO, 028,052TУ)인 고착제 7에 의해 고착된다. 상기 유전체판 1의 리세스 8은 금속화될 수도 있고, 상기 리세스의 저부는 상기 유전체판 1의 대향면상의 금속화 패턴층 10(예컨대, Pd-Ni(0.2μm)-Cu(3μm)-Ni(0.5μm)-Au(2μm)으로 조성됨)에 전기적으로 연결하기 위한 금속 구멍 9를 구비한다. 상기 구멍 9의 직경은 100μm(50μm-1mm)이다. 상기 유전체판 다발의 각 유전체판간의 간격은 10μm이다.As shown in Fig. 1, the multilayer microwave and ultra high frequency (EFH) hybrid integrated circuit according to the present invention is, for example, Ti (0.04 μm) -Pd (0.2 μm) -Au (3 μm), or Cr (0.04 μm). Polycor or sapphire with a phase metallization pattern layer 2 having the structure of) -Cu (1μm, evaporated-precipitated) -Cu (3μm) -Ni (0.6μm) -Au (3μm, electrochemically precipitated) A bundle of 0.5 or 1.0 mm thick fixed solid dielectric plates 1 produced. The multilayer microwave and extremely high frequency (EFH) hybrid integrated circuit has a transistor-like hook having, for example, a junction pad 4 electrically connected to the phase metallization pattern layer 2 via an electrical connection 5 made of a gold wire of 15 μm diameter. An up-wired pure semiconductor chip 3 is provided. A recess 6 is formed on the surface of the dielectric plate 1 having a size of 0.6 × 0.6 × 0.17mm for the transistor 3П325A-5 and 0.5 × 0.5 × 0.17mm for the diode, and the hook-up wired pure The semiconductor chip 3 is mounted in the recess 6 and is fixed by a fixing agent 7, which is, for example, an adhesive of the type Ч-C type C (Std.Spec.ЬIУO, 028,052TУ). The recess 8 of the dielectric plate 1 may be metallized, and the bottom of the recess may be a metallization pattern layer 10 (for example, Pd-Ni (0.2 μm) -Cu (3 μm) — on the opposite surface of the dielectric plate 1. Metal holes 9 for electrical connection to Ni (0.5 μm) -Au (2 μm)). The diameter of the hole 9 is 100 μm (50 μm−1 mm). The interval between each dielectric plate of the dielectric plate bundle is 10 μm.
상기 반도체칩 3은 예컨대,ЭЧЭ-C 타입의 접착제(Std.Spec.ЬIУO, 028,052TУ)또는 공정(共晶) Au-Si 경질 땜납과 같은 전기 및 열 전도물질 11으로 접합된다. 상기 리세스 8의 저부에 형성된 상기 금속화 구멍 9는 Au-Si 경질 땜납또는 65 중량 ％의 Zn, 15 중량 ％의 Cu, 20 중량 ％의 Al을 함유하는 경질 땜납과 같은 전기 및 열 전도물질로 채워진다. 300μm 깊이의 리세스 12는 상기 인접 유전체판 1의 표면에 장착된 반도체칩 3 아래에 형성될 수도 있고, 예컨대, ПMП-B1 구리-함유 풀(paste)(Std.Spec.BTO, 035,243TУ)타입의 열 전도물질 13으로 채워진다. 상기 열 전도물질 13으로 채워진 상기 리세스 12는 상기 다층 유전체판의 전체크기를 통해 연장되는 냉각 패키지또는 열 튜브와 같은 히이트 싱크(heat sink)에 (기계적 및 열적으로)연결된다.The semiconductor chip 3 is bonded with an electric and thermally conductive material 11 such as, for example, an electrolytic adhesive of the type Ч-C. Type. The metallization holes 9 formed in the bottom of the recess 8 are electrically and thermally conductive materials such as Au-Si hard solder or hard solder containing 65% by weight Zn, 15% by weight Cu and 20% by weight Al. Is filled. A recess 12 having a depth of 300 μm may be formed below the semiconductor chip 3 mounted on the surface of the adjacent dielectric plate 1, for example, a ПMП-B1 copper-containing paste (Std.Spec.BTO, 035,243TУ) type. Filled with heat conducting material 13 The recess 12 filled with the heat conducting material 13 is (mechanically and thermally) connected to a heat sink such as a cooling tube or a heat tube extending through the entire size of the multilayer dielectric plate.
본 발명에 따른 다층 마이크로웨이브 및 극고주파(EFH) 하이브리드 집적회로는 다음과 같이 작용한다.Multilayer microwave and microwave (EFH) hybrid integrated circuits according to the present invention work as follows.
상기 마이크로웨이브 하이브리드 집적회로의 기능목적에 따라, 입력 및 출력 채널의 수에 관한 큰 MxN 인덱스를 갖고 필터와 연장되는 다이어그램-형성 매트릭스, 증폭기, 자체내장 유닛또는 송수신기 모듈에 이르는 신호 감시 요소와 같은 다기능 장치를 주로 실현하는 회로의 입력에 신호가 인가된다. 고주파 신호는 다층 유전체판과 부분적으로 배열된 막 및, 유전체층을 구비한채 층별로 분리되는 후크-업 와이어드방식의 요소에 의해 확립된 3 차원 구조로 처리된다. 즉, 상기 신호는 증폭, 발생, 변환, 필터링 및 검출된다. 신호처리와 한 공간에서 또다른 공간으로의 수직 전송이 결합된다. 따라서, 전송(transfering) 및 매칭(matching) 기능은 금속화 구멍을 통해 3 차원 분포 용량 접합부또는 유전체판내의 연결부에 의해 수행될 수 있고, 그 처리된 마이크로웨이브 신호는 상기 회로로 부터 출력된다. 상기 반도체칩에 의해 방출된 열은 상기 전체 다층 3D 유전체판상에서 확산되고, 열 전도물질로 채워진 상기 리세스사이의 열 접촉 및, 상기 다층 유전체판의 단부면과 예컨대, 상기 유전체판속에 내장된 열 튜브또는 냉각 패키지와 같은 냉각 시스템으로 인하여 방출된다.Depending on the functional purpose of the microwave hybrid integrated circuit, it has a large MxN index on the number of input and output channels and multifunctions such as signal-monitoring elements ranging from filters to diagram-forming matrices, amplifiers, self-contained units or transceiver modules. A signal is applied to the input of the circuit which mainly implements the device. The high frequency signal is processed into a three-dimensional structure established by a multilayer dielectric plate, a film partially arranged, and a hook-up wired element separated by layers with a dielectric layer. That is, the signal is amplified, generated, transformed, filtered and detected. Signal processing is combined with vertical transmission from one space to another. Thus, the transferring and matching function can be performed by a three-dimensional distributed capacitive junction or a connection in the dielectric plate through the metallization hole, and the processed microwave signal is output from the circuit. Heat emitted by the semiconductor chip is diffused on the entire multi-layer 3D dielectric plate, and thermal contact between the recesses filled with a heat conducting material, and heat embedded in the end face of the multi-layer dielectric plate and, for example, the dielectric plate. Emissions are due to cooling systems such as tubes or cooling packages.
따라서, 본 발명의 다층 하이브리드 집적회로에 의하면 다음과 효과를 얻을수 있다.Therefore, according to the multilayer hybrid integrated circuit of the present invention, the following effects can be obtained.
첫째, 회로의 전기적 특성이 향상되는 동시에, 상기 접합 패드를 상호연결하는 와이어 도체의 보다 짧아진 길이로 인하여 스퓨리어스 인덕턴스가 감소하고, 상기 유전체판의 연결 와이어 리드의 길이가 줄어든다.First, the electrical characteristics of the circuit are improved, while the shorter length of the wire conductors interconnecting the bond pads reduces the spurious inductance and reduces the length of the connecting wire leads of the dielectric plate.
둘째, 상기 유전체판의 기판에서의 칩의 배치로 인하여 상기 회로의 중량-크기 특성이 동시에 향상된다.Secondly, due to the placement of the chip on the substrate of the dielectric plate, the weight-size characteristics of the circuit are simultaneously improved.
셋째, 상기 유전체판(즉, 고체 유전체판의 기판)에 형성된 리세스속에 상기 칩을 장착함으로써 하이브리드 집적회로의 다층 유전체판의 각 층에 후크-업 와이어드방식의 순수 반도체칩을 배치할 수 있는 가능성에 의해, 열 전도물질로 채워진 리세스를 상기 칩 아래에 형성함으로써, 상기 칩으로 부터의 열확산 조건이 향상된다.Third, the possibility of disposing a hook-up wired pure semiconductor chip in each layer of a multilayer dielectric plate of a hybrid integrated circuit by mounting the chip in a recess formed in the dielectric plate (ie, a substrate of a solid dielectric plate). Thereby, by forming a recess filled with a thermally conductive material under the chip, the thermal diffusion condition from the chip is improved.
또한, 상기 상호연결 및 결합 도체의 길이가 감소함으로써, 귀금속의 소모를 줄일수 있다.In addition, by reducing the length of the interconnect and coupling conductors, it is possible to reduce the consumption of precious metals.
본 발명에 따른 전술한 실시예들을 기술함에 있어서, 협의의 특정용어는 명료성 차원에서 사용된다. 그러나, 본 발명은 선택된 특정용어에 한정되는 것은 아니며, 그러한 각 용어들은 유사한 방식으로 작동하고 동일한 기술적 문제점의 해결을 위해 사용되는 모든 등가의 요소들을 포함한다는 것을 명심해야 한다.In describing the above-described embodiments according to the present invention, specific terms of consultation are used for clarity. However, it is to be noted that the invention is not limited to the specific terminology selected, and that each such term includes all equivalent elements that operate in a similar manner and that are used to solve the same technical problem.
지금까지, 특정의 바람직한 실시예및 그 대체 실시예와 관련하여 본 발명이 상세히 개시되고 설명되었지만, 상기 본 발명에 대한 개시는 단지 본 발명의 적용예에 불과한 것이고, 본 발명을 수행하기 위한 최상 모드로서 본 명세서에 개시된 특정 실시예에 국한되는 것은 아니다.So far, the present invention has been disclosed and described in detail with reference to certain preferred embodiments and alternative embodiments thereof, but the above disclosure is merely an application of the present invention, and best mode for carrying out the present invention. It is not intended to be limited to the particular embodiments disclosed herein.
또한, 하기 특허청구의 범위에 의해 마련되는 본 발명의 사상이나 분야를 일탈하지 않는 범위내에서 본 발명이 다양하게 개조및 변경될 수 있다는 것을 당업계에서 통상의 지식을 가진자라면 용이하게 이해할 수 있을 것이다.In addition, one of ordinary skill in the art can easily understand that the present invention can be variously modified and changed without departing from the spirit or the scope of the present invention provided by the following claims. There will be.
본 발명은 반도체 미소 전자공학(semiconductor microelectronics)분야에 사용될 수 있다.The present invention can be used in the field of semiconductor microelectronics.
Claims (3)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/RU1996/000290 WO1998015979A1 (en) | 1996-10-10 | 1996-10-10 | Ehf and microwave-frequency multilayered hybrid and integrated circuit |
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| Publication Number | Publication Date |
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| KR19990071999A true KR19990071999A (en) | 1999-09-27 |
| KR100420794B1 KR100420794B1 (en) | 2004-05-06 |
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| KR10-1998-0704291A KR100420794B1 (en) | 1996-10-10 | 1996-10-10 | Multi-Layer Microwave and Ultra-Frequency Hybrid Integrated Circuits |
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| Country | Link |
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| KR (1) | KR100420794B1 (en) |
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| WO (1) | WO1998015979A1 (en) |
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| US5869894A (en) * | 1997-07-18 | 1999-02-09 | Lucent Technologies Inc. | RF IC package |
| RU2659752C1 (en) * | 2017-05-22 | 2018-07-03 | Андрей Александрович Григорьев | Power hybrid microwave integrated circuit |
| RU2750860C1 (en) * | 2020-09-21 | 2021-07-05 | Акционерное общество "Научно-производственное предприятие "Исток" имени А.И. Шокина" (АО "НПП "Исток" им. Шокина") | Microwave hybrid integrated circuit |
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| SU1598238A1 (en) * | 1987-01-04 | 1990-10-07 | Предприятие П/Я А-3646 | High-frequency integrated module |
| SU1753961A3 (en) * | 1989-07-20 | 1992-08-07 | Юрий Дмитриевич Сасов | Hybrid multilevel electronic module |
| CA2049979A1 (en) * | 1990-01-24 | 1991-07-25 | Jury D. Sasov | Three-dimensional electronic unit and method of fabricating same |
| FR2694840B1 (en) * | 1992-08-13 | 1994-09-09 | Commissariat Energie Atomique | Three-dimensional multi-chip module. |
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1996
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| WO1998015979A1 (en) | 1998-04-16 |
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