KR19990069753A - Timing-checkable chip (CHIP) - Google Patents

Abstract

The present invention is to provide a chip capable of timing check that can be more accurately chip test by adjusting the output timing of the test data during the chip test, in the semiconductor chip consisting of a plurality of combination circuit and sequential circuit, A first flip-flop group configured on an input side of the combination circuit, a second flip-flop group configured on an output side of the combination circuit and having a serial input / output terminal separate from a serial input / output terminal of the first flip-flop group, and the serial input terminal. A control circuit unit for selectively applying serial data inputted through the first flip-flop group and the second flip-flop group, and outputting a control signal for adjusting a timing of a clock signal of the second flip-flop group; And a clock generation timing controller configured to adjust the clock signal generation timing of the second flip-flop group according to the signal. Characterized in that the open configuration.

Description

Timing-checkable chip (CHIP)

The present invention relates to a semiconductor chip, and more particularly, to a chip (CHIP) capable of proper timing check in order to enable a more accurate test by enabling not only functional check but also timing check during chip testing.

Hereinafter, a conventional semiconductor chip will be described with reference to the accompanying drawings.

1 is a structure of a chip according to the prior art and is composed of a plurality of flip-flops and a plurality of combination circuits.

In general, one chip is composed of a plurality of combination circuits and a plurality of sequential circuits.

The flip-flops are divided into an input side flip-flop 11 and an output side flip-flop 13 of the combination circuit, and the combination circuit receives data from the input side flip-flop 11 and applies it to the output side flip-flop 13.

Conventionally, in order to test such a chip, a plurality of flip-flops (F / F) are serially connected to input data serially and output data serially.

In other words, if the chip designer compares the desired data with the output data, the chip is irrelevant. If the chip designer is not identical, the chip is irrelevant.

This will be described in more detail as follows.

As shown in FIG. 1, in a sequential circuit, a plurality of flip-flops (F / F) 11a, 11b, 11c, and 13a, 13b, 13c are serially connected to each other to serially input and output data.

Each flip-flop includes a clock signal clk, a test enable signal test en, an input terminal D for inputting data applied from another flip-flop in the chip although not shown in the drawing, and data for testing in the chip test mode. The serial in and serial out ends are configured.

Here, the data for the chip test is input from the outside of the chip.

The serial out of the flip-flop, which first receives the serial data, is connected to the serial in of the next flip-flop.

Many of these flip-flops are serially connected to each other and to a combination circuit.

Referring to the test process of the chip having the above configuration is as follows.

First, before normal chip test, the test enable signal test en is 0.

Then, when the test mode, the test enable signal is "1", the data is serially input to the flip-flop in the chip.

That is, whenever the test enable signal becomes " 1 " and the clock signal is applied, the serial data is sequentially set to the input flip-flop 11 and the output flip-flop 13, respectively.

At this time, if the number of flip-flops is N, the clock signal is also triggered N times.

In this manner, after setting the respective flip-flops according to the clock signal, the chip is normally operated for one cycle with the test enable signal test en set to "0".

As the chip operates, the combination circuit receives data from the input flip-flop 11 and applies the result to the output flip-flop 13.

Therefore, the output value of the combination circuit is latched by the output side flip-flop 13.

After normal operation of the chip for 1 cycle, the test enable signal is set to "1" and serial data is input through the serial input terminal, and the data is serially set to each flip-flop.

At this time, the data previously set on each flip-flop 11a, 11b, 11c, 13a, 13b, 13c is sequentially output through the serial output stage. The chip designer compares the serially output data with the desired data and matches the current. The chip is determined to be normal, and if the serially output data and the desired data do not match, the chip is determined to be abnormal.

That is, since the output value of the combination circuit is initially set on the output flip-flop 13 and serially output due to the input of the serial data, the data output serially is output to the corresponding flip-flop in case of abnormality. The data set will not match the data desired by the chip designer.

Therefore, the chip designer detects whether the chip is normal by comparing the serially output data with the desired data.

However, in the conventional chip as described above, if the serially output data does not match with the desired data, it is possible to determine that the chip state is abnormal. There was a problem that can not be determined whether or not due to delay.

The present invention has been made to solve the above problems, and if the chip is abnormal by adjusting the timing of the serially output data to determine whether the cause is due to a delay of the circuit or an error inside the chip. The aim is to provide a chip capable of timing checks that enables more accurate chip testing.

1 is a block diagram of a conventional semiconductor chip

2 is a block diagram illustrating a chip capable of timing checking according to the present invention.

Figure 3a is a detailed configuration diagram of the control circuit unit according to the present invention

3b is a detailed configuration diagram of a clock generation timing controller according to the present invention;

4 is a timing diagram illustrating clock generation timing according to the present invention.

Explanation of symbols for main parts of the drawings

21: control circuit 21a: register

21b: decoder section 21c: multiplexing section

22: clock generation timing control section 22a: delay control section

22b, 22c: 1st, 2nd delay part 23: 1st flip-flop group

25: second flip-flop group

A chip capable of timing checking according to the present invention for achieving the above object comprises: a semiconductor chip composed of a plurality of combination circuits and a sequential circuit, the first flip-flop group having a serial input / output terminal and configured on an input side of the combination circuit; A second flip-flop group configured on an output side of the combination circuit and having a serial input / output terminal separate from a serial input / output terminal of a first flip-flop group; and serial data coming through the serial input terminal; A control circuit unit for selectively applying to the group and outputting a control signal for adjusting the timing of the clock signal of the second flip-flop group; and a clock for adjusting the clock signal generation timing of the second flip-flop group according to the control signal And a generation timing controller.

Hereinafter, a chip capable of timing checking according to the present invention will be described with reference to the accompanying drawings.

2 is an internal configuration diagram of a chip capable of timing checking according to the present invention.

As shown in FIG. 2, the chip capable of timing checking according to the present invention is largely composed of a plurality of flip-flops (F / F), combination circuits, a control circuit 21, and a clock generation timing controller 22. do.

The flip-flops F / F are conventionally composed of an input flip flop and an output flip flop, and the input side and the output side are serially connected. However, the present invention provides an input flip-flop (in the present invention, the first flip-flop 23). "" And the output flip-flop (referred to as "second flip-flop 25" in the present invention) were separated.

That is, both the first flip-flop group 23 and the second flip-flop group 25 have separate serial input terminals and serial output terminals.

The first flip-flop group 23 operates by the first clock signal clk1, and the second flip-flop group 25 operates by the second clock signal clk2.

The generation of the different first and second clock signals clk1 and clk2 is performed by the clock generation timing controller 22.

Here, the clock generation timing controller 22 will be described below. First, the control circuit unit 21 will be described.

The control circuit unit 21 receives the control data serially from the outside and decodes the control data to selectively input the control data to the first flip-flop group 23 and the second flip-flop group 25 sequentially, and further, the clock generation timing controller. The control signal is output to (22).

Such a control circuit unit 21 will be described in more detail.

3A is a detailed configuration diagram of a control circuit unit according to the present invention.

As shown in Fig. 3A, a register section 21a for storing control data input from the outside, a decoder section 21b for decoding data stored in the register section 21a, and the control data and chip test are performed. And a multiplexing unit 21c for selectively applying scan data to the first flip-flop group 23 and the second flip-flop group 25.

Here, the control data input from the outside includes data for determining how fast or slow the second clock signal clk2 of the second flip-flop group 25 is.

Therefore, the control circuit unit 21 outputs a control signal to the clock generation timing controller 22 according to the control data.

3B is a detailed configuration diagram of a clock generation timing controller according to the present invention.

As shown in Fig. 3B, the delay control unit 22a receives the control signal from the control circuit unit 21 and controls the timing of the first and second clock signals clk1 and clk2, and the first clock signal clk1. The first delay unit 22b and the first clock signal clk1 are longer or shorter than the delay time of the first delay unit 22b and output as a second clock signal clk2. It consists of the 2nd delay part 22c.

Here, the first clock signal clk1 input to the first and second delay units 22b and 22c is commonly applied, and the first delay unit 22b of the first delay unit 22b according to the control signal of the first delay unit 22b is used. Since the delay time and the delay time of the second delay unit 22c are different from each other, it is possible to generate another second clock signal clk2 different from the first clock signal clkl input.

Referring to the operation of the timing check chip of the present invention configured as described above is as follows.

First, when control data is set in the control register section 21a of the control circuit section 21, the decoder 21b decodes the data set in the control register section 21a to control the multiplexing section 21c.

Here, the control data set in the register section 21a includes data for determining whether to make the second clock signal clk2 faster or slower than the first clock signal clk1.

The multiplexing unit 21c divides the control data into the first flip-flop group 23 and the second flip-flop group 25 and sequentially sets the control data through the serial input terminal.

At this time, the decoder 21b outputs a test enable signal as "1".

That is, in the present invention, it is assumed that the number of the first and second flip-flop groups 23 and 25 is three, respectively, and data is input to the first flip-flop group 23 and subsequent data is the second flip-flop group Assuming that it is input to 25, control data is sequentially set to three flip-flops 23a, 23b, and 23c constituting the first flip-flop group 23 in accordance with the first clock signal clk1.

Thereafter, the data input terminal is changed into the second flip-flop group 25 by the multiplexing unit 21c, and the control data received thereafter is three flip-flops 25a, 25b, and 25c constituting the second flip-flop group 25. Are set sequentially.

As such, after data is set in all the flip-flops of the first and second flip-flop groups 23 and 25, the chip is operated normally for one cycle.

At this time, the data set in each of the flip-flops 23a, 23b, and 23c of the first flip-flop group 23 is latched into the second flip-flop group 25 through a combination circuit.

Since the second flip-flop group 25 is operated by the second clock signal clk2, the second flip-flop group 25 is latched into the second flip-flop group 25 in accordance with the second clock signal clk2.

For example, when timing is adjusted so that the second clock signal clk2 is generated 2 nsec later than the first clock signal clk1 (adjusted by an engineer), the clock generation timing controller of FIG. 3B operates as follows.

The delay control unit 22a, which has received a control signal from the control circuit unit 21 to cause the second clock signal clk2 to be generated 2 nsec later than the first clock signal clk1, receives the first delay unit 22b and the second delay unit. Control 22c.

As shown in the figure, the first delay unit 22b and the second delay unit 22c input the first clock signal clk1 in common.

Therefore, the delay control unit 22a keeps the delay time of the second delay unit 22c about 2nsec longer than the delay time of the first delay unit 22b.

That is, by lengthening the delay time of the second delay unit 22c, the second clock signal is transmitted through the second delay unit 22c 2nsec after 2nsec compared to the first clock signal clk1 output through the first delay unit 22b. (clk2) is output.

An output of each second delay unit 22c is connected to each flip flop of the second flip-flop group 25, and an output of the first delay unit 22b is connected to each flip flop of the first flip-flop group 23. Connected.

In this way, the output of the combination circuit is latched to each flip flop 25a, 25b, 25c of the second flip-flop group 25 by the second clock signal clk2.

Here, the first and second delay units 22b and 22c connect the inverters in series to adjust the delay time.

As a result, the timing of generation of the second clock signal clk2 may be adjusted based on the timing delay value included in the control data to latch the data at a desired timing.

This is illustrated in FIG. 4.

As shown in FIG. 4, the present invention adjusts the generation timing so that the second clock signal clk2 can occur before and after the first clock signal clk1, thereby outputting chip test data at an engineer's desired timing. There is a number.

Then, the engineer can compare the data latched in the second flip-flop group 25 with the desired data to determine whether the current chip state is bad or not, and if it is bad, it is due to an internal cause of the chip or Can be determined by the delay.

As described above, in the timing checkable chip of the present invention, a control circuit unit and a clock generation timing controller may be added to separately control clock signals of an input flip-flop and an output flip-flop of a combination circuit to output data at a desired timing. If the chip is abnormal, it is possible to determine whether it is caused by the internal chip or the delay of the circuit, so that more accurate chip testing is possible.

Claims (4)

In a semiconductor chip composed of a plurality of combination circuits and sequential circuits, A first flip-flop group having a serial input / output terminal configured on the input side of the combination circuit, a second flip-flop group configured on the output side of the combination circuit having a serial input / output terminal separate from the serial input / output terminal of the first flip-flop group; A control circuit unit for selectively applying serial data received through the serial input terminal to the first flip-flop group and the second flip-flop group, and outputting a control signal for adjusting a timing of a clock signal of the second flip-flop group; , And a clock generation timing controller configured to adjust the clock signal generation timing of the second flip-flop group according to the control signal. The method of claim 1, And the first clock signal and the second clock signal have different timings of clock generation. The method of claim 1, The control circuit unit flips the register to store control data coming from the outside of the chip, the decoder unit to decode the control data stored in the register, and the scan data for the control data or the chip test by the control signal of the decoder unit. And a multiplexing unit selectively applying to the flop group and the second flip-flop group. The method of claim 1, The clock generation timing control unit may receive a control signal output from the control circuit unit, and a delay control unit to control generation timing of the first clock signal and the second clock signal, and delay the first clock signal under the control of the delay control unit. And a second delay unit for outputting a first clock signal as a second clock signal by a delay time different from the delay time of the first delay unit under the control of the delay control unit. Timing check chip.