KR19990066545A - Asymmetric Input Buffer Circuit for Semiconductor Devices - Google Patents

Abstract

An asymmetric input buffer of the present invention comprises: a first input terminal for receiving a first external signal; A second input terminal receiving a second external signal; A phase of the second external signal having first and second transistors received through the first and second input terminals and controlled to the first and second external signals; A first differential amplifier for generating a first signal inverting the signal; A phase of the second external signal having third and fourth input transistors provided with the first and second external signals and controlled to the first and second signals via the first and second input terminals; A second differential amplifier for generating a second signal inverted; A third differential amplifier receiving the first and second signals output from the first and second differential amplifiers and generating a third signal inverting the phase of the second signal; And a pulse generator for generating a pulse signal when the third signal transitions to a low level, wherein the size of the first and second input transistors includes a different size than the size of the third and fourth input transistors.

Description

ASYMMETRIC INPUT BUFFER CIRCUIT OF SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor device, and more particularly to an asymmetric input buffer.

The clock signal input buffer currently used is configured using a symmetrical amplifier, so that a time delay due to an input path from an input of an external clock signal to an internal clock signal for driving an internal circuit is generated. In general, symmetrical amplifiers are composed of MOS transistors having the same channel size, so that a time delay occurs according to the size of the channel. As a result, the driving of the internal circuits receiving the internal clock signal may also be delayed by a delay time according to the size of the channel.

It is therefore an object of the present invention to provide an input buffer circuit which improves the speed from the external clock signal input to the generation of the internal clock signal.

1 is a block diagram showing a configuration of an asymmetric input buffer according to a first embodiment of the present invention;

2A is a circuit diagram showing a circuit configuration of an A-type amplifier of an asymmetric input buffer according to the present invention;

2B is a circuit diagram showing a circuit configuration of a B-type amplifier of an asymmetric input buffer according to the present invention;

3 is a block diagram showing a configuration of an asymmetric input buffer according to a second embodiment of the present invention; and

4 is an operation timing diagram of an asymmetric input buffer according to an embodiment of the present invention.

* Explanation of symbols on the main parts of the drawings

11: first external signal input terminal 12: second external signal input terminal

21: first differential amplifier 22: second differential amplifier

23: fourth differential amplifier 24: fifth differential amplifier

30: third differential amplifier 40: pulse generator

50: internal circuit input terminal 60: A-type amplifier

70: B type amplifier 80, 90: output terminal

(Configuration)

According to one aspect of the present invention for achieving the above object, an asymmetric input buffer includes a first input terminal for receiving a first external signal; A second input terminal receiving a second external signal; A phase of the second external signal having first and second transistors received through the first and second input terminals and controlled to the first and second external signals; A first differential amplifier for generating a first signal inverting the signal; A phase of the second external signal having third and fourth input transistors provided with the first and second external signals and controlled to the first and second signals via the first and second input terminals; A second differential amplifier for generating a second signal inverted; A third differential amplifier receiving the first and second signals output from the first and second differential amplifiers and generating a third signal inverting the phase of the second signal; And a pulse generator for generating a pulse signal when the third signal transitions to a low level, wherein the size of the first and second input transistors is different from the size of the third and fourth input transistors.

In this embodiment, the signal of the reference voltage level is supplied to one of the first and second input terminals.

(Action)

Such a device can improve the drive speed of the internal circuit by reducing the time delay occurring in the input buffer circuit.

(Example)

Hereinafter, the present invention will be described in detail with reference to FIGS. 1 through 4 according to embodiments of the present invention.

1 is a block diagram illustrating a configuration of an asymmetric input buffer according to a first embodiment of the present invention.

Referring to FIG. 1, the asymmetric input buffer according to the first embodiment of the present invention includes a first external signal input terminal 11, a second external signal input terminal 12, a first differential amplifier 21, and a second differential. An amplifier 22, a third differential amplifier 30, a pulse generator 40, and an internal circuit signal input terminal 50 are included.

The first external signal input terminal 11 is connected to first input terminals of the first differential amplifier 21 and the second differential amplifier 22. The second external signal input terminal 12 is connected to the second input terminals of the first differential amplifier 21 and the second differential amplifier 22. The first input terminal of the first differential amplifier 21 is connected to the first external signal input terminal 11, the second input terminal is connected to the second external signal input terminal 12, and the output terminal is the first input terminal. 3 is connected to the first input terminal of the differential amplifier 30. A first input terminal of the second differential amplifier 22 is connected to the first external signal input terminal 11, a second input terminal is connected to the second external signal input terminal 12, and the output terminal is connected to the It is connected to the second input terminal of the third differential amplifier 30.

The first input terminal of the third differential amplifier 30 is connected to the output terminal of the first differential amplifier 21 and the second input terminal is connected to the output terminal of the second differential amplifier 22 and the The output terminal is connected to the input terminal of the pulse generator 40. The input terminal of the pulse generator 40 is connected with the output terminal of the third differential amplifier 30 and the output terminal is connected with the internal circuit input terminal 50.

2A is a circuit diagram showing the configuration of an A-type amplifier of an asymmetric input buffer according to the present invention.

Referring again to FIG. 2A, the A-type amplifier 60 of the asymmetric input buffer of the present invention includes PMOS transistors M1, M2, M3 and NMOS transistors M3, M4 having different channel sizes. . The PMOS transistor M1 has a source, a gate and a drain, the source is connected to the drain of the second PMOS transistor M2 and the gate is connected to the second external signal input terminal 12 and the MOS transistors ( The gates of M2, M3 and M4 are connected to the connected point and the drain is connected to an external voltage power supply. The PMOS transistor M2 has a source, a gate and a drain, and the source is connected to a connection point of the drain and the output terminal 80 of the NMOS transistor M3 and the gate is connected to the second external signal input terminal 12. And the gates of the MOS transistors M1, M3, and M4 are connected, and the drain is connected to the source of the PMOS transistor M1.

The PMOS transistor M3 has a source, a gate and a drain, the source is connected to a first ground power source and the gate is connected to the second external signal input terminal 12 and the MOS transistors M1, M2, and M4. Are connected to the point at which the gates of the gate are connected and the drain is connected to the source of the PMOS transistor M2. The NMOS transistor M4 has a source, a gate and a drain, the source is connected to a second ground power source and the gate is connected to the second external signal input terminal 12 and the MOS transistors M1, M2, M3. Are connected to the point where the gates of the gates are connected and the drain is connected to the source of the PMOS transistor M10. The PMOS transistor M10 has a source, a gate and a drain, the source is connected to the drain of the NMOS transistor M9, the gate is connected to the first external signal input terminal 11, and the drain is the PMOS. It is connected to the connection point of the transistors M1 and M2.

Figure 2b is a circuit diagram showing the configuration of the B-type amplifier of the asymmetric input buffer according to the present invention.

Referring again to FIG. 2B, the B-type amplifier 60 of the asymmetric input buffer of the present invention includes PMOS transistors M6, M7 and M10 and NMOS transistors M8 and M9 having the same channel size. . The PMOS transistor M6 has a source, a gate and a drain, the source is connected to the drain of the second PMOS transistor M7 and the gate is connected to the second external signal input terminal 12 and the MOS transistors ( The gates of M7, M8 and M9 are connected to the connected point and the drain is connected to an external voltage power supply. The PMOS transistor M7 has a source, a gate and a drain, the source being connected to a connection point of the drain and the output terminal 80 of the NMOS transistor M8 and the gate is connected to the second external signal input terminal 12. And the gates of the MOS transistors M6, M8, and M9 are connected, and the drain is connected to the source of the PMOS transistor M6.

The PMOS transistor M8 has a source, a gate and a drain, the source is connected to a first ground power source and the gate is connected to the second external signal input terminal 12 and the MOS transistors M6, M7, and M9. Are connected to the point at which the gates of the gate are connected and the drain is connected to the source of the PMOS transistor M7. The NMOS transistor M9 has a source, a gate and a drain, the source is connected to a second ground power source and the gate is connected to the second external signal input terminal 12 and the MOS transistors M6, M7, M8. Are connected to the point where the gates of the gates are connected and the drain is connected to the source of the PMOS transistor M10. The PMOS transistor M10 has a source, a gate and a drain, the source is connected to the drain of the NMOS transistor M9, the gate is connected to the first external signal input terminal 11, and the drain is the PMOS. It is connected to the connection point of the transistors M6 and M7.

3 is a block diagram illustrating a configuration of an asymmetric input buffer according to a second embodiment of the present invention.

Referring again to FIG. 3, an asymmetric input buffer according to the second embodiment of the present invention additionally adds a fourth differential amplifier 23 and a fifth differential amplifier 24 to the asymmetric input buffer according to the first embodiment. Include as. The first input terminal of the fourth differential amplifier 23 is connected with the output terminal of the first differential amplifier 21, the second input terminal is connected with the output terminal of the second differential amplifier 22, and the output terminal is It is connected to the first input terminal of the third differential amplifier 30. The first input terminal of the fifth differential amplifier 24 is connected to the output terminal of the first differential amplifier 21, the second input terminal is connected to the output terminal of the second differential amplifier 22, and the output terminal is It is connected to the second input terminal of the third differential amplifier 30.

4 is an operation timing diagram of an asymmetric input buffer according to the present invention.

Referring back to Figures 1-4, the operation of the asymmetric buffer of the present invention is described.

The first differential amplifier 21 includes the A-type amplifier 60. The first differential amplifier 21 outputs the first and second external signals EXTS1 and EXTS2 supplied to the first and second input terminals as first output signals of which phase and level are switched.

For example, when the voltage level of the first external signal EXTS1 is low and the voltage level of the second external signal EXTS2 is high, the MOS transistors M3 and M4 of the first differential amplifier 21. Channels are turned on and the channels of the MOS transistors M1, M2, and M5 are blocked. As a result, charges are discharged more slowly through the channels of the MOS transistors M3 and M4 than the type B differential amplifier 70 through the first and second ground power supplies. Therefore, the voltage level of the first output signal of the output terminal 80 is switched to the low level slower than the output signal of the B-type differential amplifier 70.

When the voltage level of the first external signal EXTS1 is high and the voltage level of the second external signal EXTS2 is low, the MOS transistors M3 and M4 of the first differential amplifier 21 are turned on. Channels are blocked and the channels of the MOS transistors M1, M2, M5 are conductive. As a result, charges are supplied to the output terminal 80 through the channels of the MOS transistors M1, M2, and M5 and the output signal voltage level of the output terminal 80 is switched to a high level. In this case, since the size of the channel of the MOS transistor M5 is larger than that of the channel of the MOS transistor M6 of the B-type amplifier 22, the level of the first output signal of the first differential amplifier 21 is increased. It rises faster than the level of the output signal of the second differential amplifier 22.

The second differential amplifier 22 includes the B type amplifier 70. The second differential amplifier 21 outputs a second output signal in which phases and levels are switched from the first and second external signals EXTS1 and EXTS2 supplied to the first and second input terminals.

For example, when the voltage level of the first external signal EXTS1 is low and the voltage level of the second external signal EXTS2 is high, the MOS transistors M3 and M4 of the second differential amplifier 21. Channels are turned on and the channels of the MOS transistors M6, M7, and M10 are blocked. As a result, charges supplied from the external voltage power supply are discharged faster than the A-type differential amplifier 60 through the channels of the MOS transistors M8 and M9. Therefore, the voltage level of the second output signal of the output terminal 90 is switched to the low level faster than the type A differential amplifier 60.

When the voltage level of the first external signal EXTS1 is high and the voltage level of the second external signal EXTS2 is low, the MOS transistors M8 and M9 of the second differential amplifier 22 are disposed. Channels are blocked and the channels of the MOS transistors M6, M7, M10 are conductive. This causes charges to be supplied to the output terminal 90 through the channels of the MOS transistors M6, M7, M10. The second output signal voltage level of the output terminal 90 is switched to the high level slower than the first differential amplifier 21. In this case, since the channel sizes of the MOS transistors M6, M7, and M10 are the same, the charges transferred between the connection point of the MOS transistors M6, M7, and M10 and the connection points of the MOS transistors M9 and M10 are the same. Will cause a time delay.

The first output signal output from the first differential amplifier 21 is input to the first input terminal of the second differential amplifier 30, and the second differential amplifier 22 is output to the second input terminal. The second output signal is input. Phases and levels of the first and second output signals are switched to the output terminals of the third differential amplifier 30 to output a third output signal.

For example, when the phases of the first and second output signals are at a high level at the same time, the voltage level of the third output signal of the third differential amplifier 30 drops rapidly. When the phase of the first output signal is low level and the phase of the second output signal is high level, the output level of the third output signal rises slowly. The pulse generator 40 generates a low level activation pulse whose time is shorter than the output signal of the symmetrical input buffer according to the conventional embodiment by the rapidly falling voltage level of the third output signal.

As mentioned above, the use of asymmetrical amplifiers can reduce the time delay from the input of the external signal to the generation of the internal activation signal. As a result, the operation speed of the internal circuit can be improved.

Claims (2)

A first input terminal receiving a first external signal; A second input terminal receiving a second external signal; A phase of the second external signal having first and second transistors received through the first and second input terminals and controlled to the first and second external signals; A first differential amplifier for generating a first signal inverting the signal; A phase of the second external signal having third and fourth input transistors provided with the first and second external signals and controlled to the first and second signals via the first and second input terminals; A second differential amplifier for generating a second signal inverted; A third differential amplifier receiving the first and second signals output from the first and second differential amplifiers and generating a third signal inverting the phase of the second signal; And a pulse generator for generating a pulse signal when the third signal transitions to a low level, wherein the size of the first and second input transistors is different from the size of the third and fourth input transistors. Circuit. The method of claim 1, And an input buffer circuit of a semiconductor device, wherein a signal having a reference voltage level is supplied to one of the first and second input terminals.