KR100483052B1 - Phase delay circuit - Google Patents

Abstract

The present invention relates to a phase delay circuit for generating a plurality of phase delay signals having different phases (specifically, satisfying a desired phase relationship) from one reference signal, and in particular, by delaying a signal using a MOS transistor. A phase delay circuit for reducing area and minimizing power consumption, comprising: a phase delay circuit for outputting a plurality of phase delay signals different in phase with respect to a reference signal to achieve the above object; In order to reduce the design area of the phase delay circuit and reduce the power consumption, an input dry unit for receiving the reference signal, a rising delay unit for transmitting the input dry unit output signal, and the output unit for transmitting the rising delay unit output signal are provided. A plurality of phase delay units comprising a polling delay unit and an output driver for receiving the output signal of the polling delay unit and outputting a phase delay signal are connected in parallel, thereby reducing power consumption and design area. There is.

Description

Phase delay circuit

The present invention relates to a phase delay circuit for generating a plurality of phase delay signals having different phases (specifically, satisfying a desired phase relationship) from one reference signal, and in particular, by delaying a signal using a single switching transistor. The present invention relates to a phase delay circuit for reducing layout area and minimizing power consumption.

In general, the phase delay circuit is used in a voltage generating circuit that generates a voltage required inside the device, such as a charge pump circuit.

FIG. 1 shows a block diagram of a phase delay circuit 20 for outputting four phase delay signals for driving the charge pump circuit 10 from one reference signal inputted therein. A detailed circuit diagram of the delay circuit 20 is shown in FIGS. 2 and 4.

As shown in FIG. 1, the phase delay circuit 20 generates four phase delay signals having different phases by using one reference signal as an input to drive the charge pump circuit 10.

Referring to the operation of the charge pump circuit 10 that generates the high voltage VPP using the four phase delay signals, as shown in FIG. 2, the first node N1 and the second node N2 are the first. It exists in the VDD-Vt state.

When the potential difference is generated between the power supply voltage terminal and the first or second node N2 and the first and second NMOS diodes DN1 and DN2 are conducted, the first and second NMOS diodes DN1 and DN2 are connected to each other. This is because the voltage drop as much as the threshold voltage occurs.

For convenience of description, taking the phase delay signals aa and dd as an example, the second node N2 having the potential of VDD-Vt is subsequently caused by the coupling effect when the phase delay signal dd transitions from "low" to "high". It rises to the electric potential above VDD + Vt.

Accordingly, the fourth NMOS transistor MN4 is completely turned on and the VDD potential is transferred to the fourth node N4.

Thereafter, the phase delay signal dd should drop to "low" before the phase delay signal aa transitions to "high" in order to prevent the charge loss of the VDD potential transferred on the fourth node N4.

When the phase delay signal dd falls back to "low", the second node N2 goes down to the VDD-Vt potential, so the fourth NMOS transistor MN4 is turned off.

As a result, the VDD potential on the fourth node N4 becomes isolated to maintain the charge.

Subsequently, when the phase delay signal aa transitions to "high", a coupling effect occurs in the fourth NMOS capacitor CN4, and the fourth node N4 rises from VDD to VPP.

Subsequently, the second PMOS transistor is turned on by the VPP potential of the fourth node N4 to output the high voltage VPP.

Since the charge pumping operation is in progress while the phase delay signal aa remains "high", the phase delay signal dd should be kept "low" at this time.

That is, after the phase delay signal aa falls to "low", the phase delay signal dd must shift to "high."

On the other hand, when the phase delay signal aa exists in the "low" state, the phase delay signals bb and dd are operated to drive the charge pump circuit 10.

The operation for this is the same as aa and dd described above, where bb plays the role of aa and cc plays the role of dd.

In summary, the phase delay signals aa and bb operate as pumping signals and cc and dd operate as control signals for controlling the switch element third and fourth NMOS transistors MN4. Before transitioning to high, dd and cc first transition to "low" to prevent charge loss, and bb must transition to "high" before aa transitions to "low" to continue pumping. .

Next, since the relationship between the four phase delay signals should be made as described above, the phase delay circuit 20 is different from each other as shown in (a), (b), (c), and (d) of FIG. It must be configured to output a signal having a phase.

The present invention relates to a phase delay circuit 20 for generating a phase delay signal for driving the charge pump circuit 10 as described above. Hereinafter, the conventional phase delay circuit 20 shown in FIG. In addition, the problems of the existing phase delay circuits are examined.

4 shows a conventional phase delay circuit 20. As a reference signal, the output signal produced by the ring oscillator is used.

For convenience, one reference signal will be referred to as a "ring oscillator output signal osc".

Looking at the configuration briefly, the first, second, third, fourth, fifth, and sixth delay units 22, 24, 26, 28 which receive the ring oscillator output signal osc and output six delay signals. First and second NAND gates ND1 and ND2 and first and second NOR gates respectively outputting four phase delay signals by combining the inverter chains of the first and second inverters 30 and 32 and the output signals of the delay units. (NR1, NR2) and a plurality of inverters.

The phase delay signals cc and dd are logically combined with n12 and n2, which are outputs of the sixth delay unit and the first delay unit, and the phase delay signals aa are logically combined with n4 and n10, which are outputs of the second delay unit and the fifth delay unit. And n6 and n8, which are outputs of the third delay section and the fourth delay section, are logically combined to form a phase delay signal bb.

Each of the pulse waveforms is illustrated in FIGS. 5A and 5B, and FIGS. 5A, 5B, 5C, 5D, 8E, and 5G show the respective delay units. The waveform of the output signal is shown.

5B shows the phase delay signals aa, bb, cc, and dd produced by combining the waveforms of FIG. 5A.

Looking at the number of transistors constituting the existing phase delay circuit 20 for outputting such a phase delay signal, the total number of transistors is 21, NAND gate and Noah gate are two, respectively, the total number of transistors is 58.

In addition, an inverter chain is used to obtain the desired delay from the first delay section to the sixth delay section.

Therefore, in the conventional phase delay circuit 20, the number of transistors is 58, and the area consumption is very large in terms of layout, and in terms of electrical, power consumption is increased because an inverter chain is used for the high frequency ring oscillator output signal. In view of the current trend of low power supply voltage and low power consumption, the circuit configuration becomes very undesirable.

Accordingly, the present invention has been made to solve the above-mentioned problems of the prior art, and provides a phase delay circuit for reducing layout area and minimizing power consumption by delaying a signal using a MOS transistor. There is this.

The phase delay circuit of the present invention for achieving the above object includes a phase delay circuit for outputting a plurality of phase delay signals different in phase with respect to a reference signal;

The phase delay circuit includes: an input driver for receiving the reference signal; a rising delay unit for delaying and transmitting a rising edge of an output signal of the input driver; and a delaying edge of an output signal of the rising delay unit for transmission. And a plurality of phase delay units including parallel delay means and an output driver for outputting the phase delay signal by driving the output signal of the polling delay means to reduce the design area and reduce power consumption. do.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

6 is a conceptual diagram for phase delay of an input signal according to the present invention.

The ring oscillator output signal osc is input to the rising delay unit 25 via the input driver 21. The rising delay unit 25 serves to delay the rising edge of the input signal.

Subsequently, the output signal of the rising delay unit 25 is inverted by the inverter and input to the falling delay unit 27.

The polling delay unit 27 delays the polling edge portion of the inverter output signal.

Subsequently, the output signal of the polling delay unit 27 outputs the phase delay signal through the output driver.

7 is a block diagram of a phase delay circuit 20 according to an embodiment of the present invention. The configuration of the phase delay circuit 20 includes an input driver 21 receiving a ring oscillator output signal osc; A rising delay unit 25 connected to an output terminal of the input driver 21, an inverter connected to an output terminal of the rising delay unit 25, a polling delay unit 27 connected to the inverter output terminal, and the falling delay unit ( 27) an inverter connected to an output terminal, an output driver 23 connected to the inverter output terminal to output a phase delay signal aa, an inverter connected to an output terminal of the input driver 21, and a polling delay unit connected to the inverter output terminal (27), an inverter connected to an output terminal of the polling delay unit 27, a rising delay unit 25 connected to the inverter output terminal, an inverter connected to an output terminal of the rising delay unit 25, and an inverter output terminal An output driver 23 for outputting a phase delay signal bb, an inverter connected to an output terminal of the input driver 21, a polling delay unit 27 connected to the inverter output terminal, and an output terminal of the polling delay unit 27. An inverter connected to the inverter, a rising delay unit 25 connected to the inverter output terminal, an output driver 23 connected to an output terminal of the rising delay unit 25 to output a phase delay signal cc, and the input driver 21 A phase delay connected to a rising delay unit 25 connected to an output terminal, an inverter connected to an output terminal of the rising delay unit 25, a polling delay unit 27 connected to the inverter output terminal, and a phase delay connected to an output terminal of the polling delay unit 27. The output driver 23 outputs a signal dd.

Inserting a rising edge delay circuit with respect to the input ring oscillator output signal osc, delaying the rising edge T1 by a desired time as shown in FIG. 9 (T1 '), and inserting a polling edge delay circuit in the same manner to poll. Delay edge T2 by the desired time (T2 ').

7 shows four phase delay signals by connecting four circuits of FIG. 6 to one signal source in parallel and adjusting the rising edge delay time and the falling edge delay time, respectively.

FIG. 8 is a detailed circuit diagram of FIG. 7, and the configuration thereof is the same as that of FIG. 7.

Therefore, the configuration relationship thereof is omitted and only the configuration relationship for each part is mentioned.

The input driver 21 and the output driver 23 are connected in series by two inverters.

The rising delay unit 25 and the falling delay unit 27 are formed of NMOS transistors whose gates are connected to power supply voltage terminals.

In addition, the inverters are connected to the output terminal of the input driver 21 in the bb and cc signals according to the phase relationship opposite to the aa and dd signals.

In the aa and bb signals, an inverter is connected to an output terminal of the polling delay unit 27 and the rising delay unit 25 according to an antiphase relationship between the dd signal and the cc signal.

In the present invention, the NMOS transistor is used as the signal delay means, and the NMOS transistor has a weak ability to transmit a "high" signal and an excellent ability to transmit a "low" signal.

Therefore, the time delay is large for the "high" input signal and the time delay is relatively short for the "low" input signal.

Taking the phase delay signal aa as an example, the ring oscillator output signal osc input to the rising delay unit 25 via the input driver 21 is delayed at the rising edge as shown in FIG. This happens.

Subsequently, the signal of (b) passes through the inverter as shown in (c), and when passing through the polling delay unit 27, a waveform as shown in (d) is output.

Subsequently, the waveform of (d) is inverted by an inverter and outputs a waveform as shown in (e). When comparing the ring oscillator output signal (osc) of (a) and the output signal of (e), T1 is It can be seen that the output is delayed by T1 '.

According to the present invention, a plurality of phase delay signals having different phases can be obtained by controlling a channel width and a channel length of a MOS transistor so as to connect a plurality of such circuits in parallel to satisfy a desired phase relationship. (FIG. 10).

In the example of the present invention, the NMOS transistor is used as the signal delay means, but the same function can be performed through any PMOS transistor, a junction transistor (FET transistor), or any circuit or element capable of delaying a signal. .

The NMOS and PMOS transistors may be divided into rising delay units and falling delay units, respectively, thereby eliminating an inverter between the rising delay unit and the falling delay unit.

For reference, referring to the number of transistors used in FIG. 8, a total of 44 transistors can be used to reduce 14 transistors compared to 58 of conventional phase delay circuits, thereby reducing the design area and using a MOS transistor instead of an inverter chain. Power consumption can be reduced for the signal.

As described above, when the phase delay circuit according to the present invention is used in all applicable circuits of a semiconductor device using a phase delay circuit such as a voltage generator, the design area and power consumption can be reduced.

Preferred embodiments of the present invention are for the purpose of illustration and various modifications, changes, substitutions and additions are possible to those skilled in the art through the spirit and scope of the present invention as set forth in the appended claims.

1 is a block diagram showing a driving relationship between a charge pump circuit and a phase delay circuit.

FIG. 2 is a detailed circuit diagram of the charge pump circuit shown in FIG.

3 is an output waveform diagram of a phase delay circuit for outputting four charge pump circuit driving signals having different phases.

4 is a circuit diagram showing an example of a phase delay circuit according to the prior art.

5A is a waveform diagram of each delay unit output stage forming the inverter chain of FIG. 4.

5B is a waveform diagram of a charge pump circuit driving signal generated by FIG. 4;

6 is a conceptual diagram for phase delay of an input signal according to the present invention.

7 is a block diagram of a phase delay circuit according to an embodiment of the present invention.

8 is a detailed circuit diagram of a phase delay circuit according to an embodiment of the present invention.

FIG. 9 is a waveform diagram showing an output relationship of a charge pump circuit driving signal aa of the phase delay circuit shown in FIG.

FIG. 10 is a waveform diagram of four charge pump circuit driving signals generated by the phase delay circuit of FIG. 8; FIG.

<Description of the symbols on the main parts of the drawings>

10: charge pump circuit 20: phase delay circuit

22: first delay unit 24: second delay unit

26: third delay unit 28: fourth delay unit

30: fifth delay unit 32: sixth delay unit

21: input driver 23: output driver

25: rising delay unit 27: polling delay unit

osc: Ring oscillator output signal DN: Enmos type diode

CN: NMOS type capacitor

Claims (7)

A phase delay circuit for outputting a plurality of phase delay signals different in phase with respect to a reference signal; In order to reduce the design area of the phase delay circuit and reduce the power consumption, An input driver for receiving the reference signal; Rising delay means for delaying and transmitting the rising edge of the output signal of the input dry portion; A polling delay means for delaying and transmitting a polling edge of the output signal of the rising delay means; And a plurality of phase delay units including an output driver for outputting the phase delay signal by driving the output signal of the polling delay means in parallel. The method of claim 1, And said rising delay means and said falling delay means comprise a MOSFET. The method according to claim 1 or 2, And said rising delay means and said falling delay means using one element. The method of claim 1, And reversing means for inverting an output signal of the rising delay means. The method of claim 1, And a buffer means for driving the output signal of the rising delay means. A phase delay circuit for outputting a plurality of phase delay signals different in phase with respect to a reference signal; In order to reduce the design area of the phase delay circuit and reduce the power consumption, An input driver for receiving the reference signal; A single switching delay element for selectively delaying and outputting the output signal of the input drive; And And an output driver for outputting the phase delay signal by including the output signal of the single switching delay element. The method of claim 6, And said single switching delay element comprises a MOSFET.

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