KR19990065308A - Reference voltage generator - Google Patents

Abstract

A reference voltage generator is disclosed. The device includes a first transistor having a source and a drain connected between the first supply and the first reference voltage, a gate connected to the drain, a gate connected to the gate of the first transistor, a first supply and a second supply. A second transistor having a source and a drain connected between the reference voltage, a gate connected to the second reference voltage, a third transistor having a source and a drain connected between the second reference voltage and the third reference voltage, and a third A fourth transistor having a gate connected to the reference voltage, a drain and a source connected between the fourth reference voltage and the first node, a gate connected to the fourth reference voltage, connected between the first reference voltage and the second node A fifth transistor having a drain and a source, a gate connected with the second reference voltage, a sixth transistor and a third group having a drain and a source connected between the second node and the first node It is connected in series between the voltage and a fourth reference voltage, and configured to one another in the first and the second resistor has a different temperature coefficient, the first node is preferably connected to the second power supply.

Description

Reference voltage generator

The present invention relates to the generation of reference voltages independent of the input voltage, and in particular, to perform a temperature compensation function, a start-up function, a standby function and / or a disable function. It relates to a reference voltage generator that can be.

In general, a reference voltage generator generates a reference voltage for biasing a current source used in a differential amplifier, or a reference voltage used as a constant voltage source of a complementary MOS analog operational amplifier.

A conventional reference voltage generator (hereinafter referred to as a conventional reference voltage generator) is disclosed in P96-51368 filed by the present applicant on October 31, 1996, entitled 'Reference voltage generator circuit independent of input voltage'. It is. The level of the reference voltages generated in the conventional reference voltage generator has a problem that changes sensitively with temperature change. In addition, when the supply power is supplied, all the transistors constituting the reference voltage generating circuit may be turned off to have an unwanted operating point.

An object of the present invention is to provide a reference voltage generator having a temperature compensation function, a startup function, a standby function, or a disable function, and capable of generating reference voltages independently of an input voltage.

1 is a circuit diagram of a preferred embodiment of a reference voltage generator according to the present invention.

FIG. 2 is a diagram for describing respective reference voltages shown in FIG. 1.

3 is a graph showing changes in temperature and resistance values according to different K's.

4 is a view for explaining an application example of the reference voltage generator according to the present invention shown in FIG.

FIG. 5 is a graph for explaining changes in currents i1, i2, and i3 according to a change in temperature of the circuit shown in FIG. 4.

In accordance with an aspect of the present invention, a reference voltage generator includes a first transistor having a source and a drain connected between a first supply power source and a first reference voltage, a gate connected to the drain, and a first transistor of the first transistor. A second transistor having a gate connected to the gate, a source and a drain connected between the first supply power supply and a second reference voltage, a gate connected to the second reference voltage, the second reference voltage and a third reference A third transistor having a source and a drain connected between the voltage, a gate connected to the third reference voltage, a fourth transistor having a drain and a source connected between the fourth reference voltage and the first node, and the fourth A fifth transistor having a gate connected to a reference voltage, a drain and a source connected between the first reference voltage and a second node, and the second reference voltage A sixth transistor having a gate connected thereto, a drain and a source connected between the second node and the first node, and a series connected in series between the third reference voltage and the fourth reference voltage and having different temperature coefficients. It is preferably composed of first and second resistors, and the first node is connected to a second supply power source.

Hereinafter, the configuration and operation of the reference voltage generator according to the present invention will be described with reference to the accompanying drawings.

1 is a circuit diagram of a preferred embodiment of a reference voltage generator according to the present invention, wherein the first, second and third PMOS transistors MP1, MP2 and MP3, the first, second, third, fourth and The fifth NMOS transistors MN1, MN2, MN3, MN4, and MN5 and first and second resistors R1 and R2 are formed.

Referring to FIG. 1, the reference voltage generator includes a first PMOS transistor MP1 having a source and a drain connected between a first supply power supply VDD and a first reference voltage REF_HIGH, and a gate connected to the drain. The second PMOS transistor MP2 and the second reference voltage having a gate connected to the gate of the first PMOS transistor MP1, a source and a drain connected between the first supply power supply VDD and the second reference voltage REF_LOW_3. A gate connected to the REF_LOW_3, a first NMOS transistor MN1 having a source and a drain connected between the second reference voltage REF_LOW_3 and the third reference voltage REF_LOW_2, and a gate connected to the third reference voltage REF_LOW_2. , A second NMOS transistor MN2 having a drain and a source connected between the fourth reference voltage REF_LOW_1 and the first node N1, a gate connected to the fourth reference voltage REF_LOW_1, and a first reference voltage REF_HIGH ) And the drain and the source connected between the second node (N2) A fourth NMOS transistor MN4 having a third NMOS transistor MN3 and a gate connected to the second reference voltage REF_LOW_3, a drain and a source connected between the second node N2 and the first node N1, First and second resistors R1 and R2 connected in series between the third reference voltage REF_LOW_2 and the fourth reference voltage REF_LOW_1 and having different temperature coefficients, and an enable signal applied from the outside. A gate connected to the third PMOS transistor MP3 and an enable signal ENABLE having a gate connected to the gate, a source and a drain connected between the first supply voltage VDD and the second reference voltage REF_LOW_3, and a first gate connected to the enable signal ENABLE. The fifth NMOS transistor MN5 has a drain and a source connected between the node N1 and the second supply power supply VSS.

FIG. 2 is a diagram for describing respective reference voltages shown in FIG. 1.

In the above-described configuration, the reference voltage generator shown in FIG. 1 has the first and second supply power sources VDD and VSS regardless of the magnitudes of the first and second supply power sources VDD and VSS as input power voltages. First, second, third and fourth reference voltages REF_HIGH, REF_LOW_3, REF_LOW_2 and REF_LOW_1 shown in FIG.

As illustrated in FIG. 2, the fourth, third, and second reference voltages REF_LOW_1, REF_LOW_2, and REF_LOW_3 maintain a constant potential difference a, b, and c from the second supply power source VSS, and It can be seen that the reference voltage REF_HIGH maintains a constant potential difference d with the first power supply VDD.

The temperature compensation function of the reference voltage generator shown in FIG. 1 will be described below.

First, referring to the change characteristics of the resistors R1 and R2 according to the temperature coefficient, assuming that the values of the resistors R1 and R2 change linearly with respect to temperature, the resistors R1 and R2 are represented by the following equation. As in Equations 1 and 2, it may be expressed by equations R1 (T) and R2 (T) depending on temperature.

R1 (T) = R1_25 × [1 + K1 * (T-25 ° C)]

R2 (T) = R2_25 × [1 + K2 * (T-25 ° C)]

Here, R1_25 and R2_25 represent resistance values of the resistors R1 and R2 at the reference temperature (25 ° C.), respectively, and K1 and K2 represent temperature coefficients of the first and second resistors R1 and R2, respectively. , T represents temperature and the unit is ° C.

When the sum of the resistance values of the resistors R1 and R2 is R, the temperature expression [R (T)] of the resistor R is expressed by Equation 3 below.

R (T) = (R1_25 + R2_25) × [1 + (K1 × R1_25 + K2 × R2_25) × (T-25 ° C) ÷ (R1_25 + R2_25)]

Equation 3 is an expression similar to Equations 1 and 2 and may be expressed as Equation 4 below.

R (T) = R_25 × [1 + K12 * (T-25 ° C)]

Here, R_25 = R1_25 + R2_25, K12 = (K1 x R1_25 + K2 x R2_25) ÷ (R1_25 + R2_25), R_25 represents the resistance value of R (T) at the reference temperature (25 ° C), K12 Represents the temperature coefficient of R (T), respectively.

If K1 is larger than K2, K12 changes within the range of K1≥K12≥K2 according to the ratio (K = R1_25 / R2_25) of the resistor R1 and the resistor R2.

3 is a graph showing changes in temperature and resistance values R (T) according to different K's, with the horizontal axis representing temperature and the vertical axis representing resistance value R (T), respectively.

At reference temperature (25 ° C), the ratio K when the sum R_25 of the resistors R1_25 and R2_25 is constant and the temperature coefficient K1 of the resistor R1 is greater than the temperature coefficient K2 of the resistor R2. The change in the resistance value R (T) according to) is as shown in FIG. 3. That is, when K is infinity, the slope is steep, and when K is 0, the slope is gentle.

4 is a view for explaining an application example of the reference voltages generated in the reference voltage generator according to the present invention shown in FIG. 1, the reference voltage generator 10 according to the present invention, the current source of the differential amplifier 4 PMOS transistor MP4, sixth NMOS transistor MN6 and seventh NMOS transistor MN7.

FIG. 5 is a graph illustrating changes in currents i1, i2 and i3 according to a change in temperature of the circuit of FIG. 4, where the horizontal axis represents temperature and the vertical axis represents currents i1, i2 and i3. Indicates the size of each.

As shown in FIG. 4, the first, third and fourth reference voltages REF_HIGH, REF_LOW_2 and REF_LOW_1 generated in the apparatus shown in FIG. 1 constitute current sources MP4, MN7 and MN6 of the differential amplifier. The second reference voltage REF_LOW_3 may be usefully used as a constant voltage in a complementary MOS analog operational amplifier. The rate of change of the magnitudes of the currents i1, i2 and i3 can be adjusted through the magnitude change of the resistors R1 and R2. Here, the magnitudes of the currents i1, i2 and i3 decrease as the sum of the resistors R1 and R2 increases, and increases as the sum decreases. That is, even if the sum of the resistors R1 and R2 shown in FIG. 1 is kept constant at the reference temperature (25 ° C), if the ratio K of R2 to R1 changes, the temperatures of the resistors R1 and R2 are changed. It can be seen that the rate of change of the sum of the resistors R1 and R2 according to the temperature change due to the different coefficients causes the currents i1, i2 and i3 to remain constant at a certain ratio of K as shown in FIG. 5. have. To this end, the reference voltage generator having a temperature compensation function according to the present invention shown in FIG. 1 may allow a current of a current source used in a differential amplifier, etc. shown in FIG. 4 to have a specific slope with respect to a temperature change.

A startup function of the apparatus shown in FIG. 1 will be described as follows.

When the first and second supply power supplies VDD and VSS are applied to the apparatus shown in FIG. 1, all the transistors shown in FIG. 1 are turned off, so that the reference voltage generator shown in FIG. 1 is undesirably operated. Can have a point. To prevent this, the reference voltage generator shown in FIG. 1 uses a third PMOS transistor MP3 and a fifth NMOS transistor MN5. If the enable signal ENABLE is transitioned from the low logic level VSS to the high logic level VDD when the first and second supply power supplies VDD and VSS are applied, the floating first floating power source may be floated. The first node N1 is at the level of the second supply power supply VSS, the transistors MN1 and MN2 in the turned off state are turned on, and the second reference voltage REF_LOW_3 is at the level of the first supply power supply VDD. Finds its own operating point.

In addition, the reference voltage generator according to the present invention shown in FIG. 1 maintains the enable signal ENABLE at a low logic level, thereby blocking a path between the first node N1 and the second supply power supply VSS. It can also perform standby or disable functions. That is, generation of reference voltages is disabled when the device shown in FIG. 1 supplies an enable signal of a low logic level at a particular point in time during operation.

As described above, the reference voltage generator according to the present invention may not only generate reference voltages independently of the input voltage, but also may perform a temperature compensation function, a start function, a standby function, and / or a disable function. It works.

Claims (5)

A first transistor having a source and a drain connected between a first supply power supply and a first reference voltage, and a gate connected to the drain; A second transistor having a gate connected to the gate of the first transistor, a source and a drain connected between the first supply power supply and a second reference voltage; A third transistor having a gate connected to the second reference voltage, a source and a drain connected between the second reference voltage and a third reference voltage; A fourth transistor having a gate connected to the third reference voltage, a drain and a source connected between a fourth reference voltage and a first node; A fifth transistor having a gate connected to the fourth reference voltage, a drain and a source connected between the first reference voltage and a second node; A sixth transistor having a gate connected to the second reference voltage, a drain and a source connected between the second node and the first node; And First and second resistors connected in series between the third reference voltage and the fourth reference voltage and having different temperature coefficients; And the first node is connected to a second supply power. The apparatus of claim 1, wherein the reference voltage generator is A seventh transistor having a gate connected to an enable signal applied from an external source, a source and a drain connected between the first supply power supply and the second reference voltage; And And an eighth transistor having a gate connected to the enable signal, a drain and a source connected between the first node and the second supply power source. The semiconductor device of claim 1, wherein each of the first and second transistors is a PMOS transistor, and each of the third, fourth, fifth, and sixth transistors is an NMOS. (NMOS) A reference voltage generator, characterized in that the transistor. A reference voltage generator according to claim 1 or 2, wherein the reference voltage generator is used in a differential amplifier having first, second and third current sources biased in response to the first, second and third bias voltages. And each of the first, third, and fourth reference voltages is the first, second, and third bias voltages. The reference voltage generator according to claim 1 or 2, wherein the reference voltage generator is used as a complementary MOS analog operational amplifier using a constant voltage, wherein the second reference voltage is used as the constant voltage.