KR19990065226A - Semiconductor memory device with redundancy decoder circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundancy decoder circuit. More particularly, the present invention relates to a semiconductor memory device for improving the speed of a redundancy decoder circuit. The present invention relates to a first control circuit that receives a chip select signal to activate a redundancy decoder circuit. And a second control circuit for receiving a first signal and a second signal deactivating the redundancy decoder circuit and generating a non-selection signal for entering the redundancy decoder circuit into a non-selection mode; And a latch circuit for storing and a driving circuit for receiving and driving the first control signal or the non-select signal, wherein the redundancy decoder circuit is deactivated when the first and second signals are activated.

Description

Semiconductor memory device with redundancy decoder circuit (SEMICONDUCTOR MEMORY DEVICE HAVING REDUNDANCY DECODER CIRCUIT)

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a redundancy decoder circuit.

When manufacturing semiconductor memory devices, it is very important to devise to obtain a better yield. Generally, even if a semiconductor memory device has only a few defective memory cells and even only one defective cell, the memory device cannot be shipped as a product. The probability of generating defective cells in the manufacture of highly integrated semiconductor memory devices is higher than that in the manufacture of devices with relatively low integration rates. In other words, the higher the density of the memory device, the more difficult it is in its manufacturing process and the lower the yield since the device is more adversely affected by debris or the like. As such, various attempts have been made to improve the yield decrease due to the high integration of the memory device.

As the structural improvement technique, a well-known redundancy technique is known. According to this technique, a memory device is provided with a main memory cell array for storing binary data, as well as an array of redundant memory cells for replacing defective cells on each of its rows and columns. Each redundant cell is connected to each redundant word and bit line. During the inspection of the main memory cell array, if several or thousands of defective cells are found, they are replaced by redundant memory cells.

FIG. 1 is a circuit diagram showing the configuration of a redundancy decoder circuit and its peripheral circuits. The chip select signal enables the redundant word line to enter the redundancy decoder circuit from the non-select mode to the select mode. This signal is generated in synchronization with the clock signal and is closely related to the clock to data output (tCD). In contrast, asynchronous signals PORESET and PDOWN that are not synchronized to the clock are not related to the chip access time and are only needed to enter the non-select mode. Therefore, it has no effect on enabling the word line.

Referring to FIG. 1, when the chip select signal and the PDOWN are applied to the NAND gate when entering the select mode from the non-select mode, the output of the deselect signal is delayed and enabled. This also affects the enable of redundant word lines. In the non-select mode by PORESET, when a low level PORESET is applied to the inverter, it is inverted to a high level, turning on N1 and latching it. Then, the latched low level signal is applied to the NAND gate 2, which outputs a high level deselect signal regardless of the input level of the other input terminal due to the NAND gate characteristic. The non-select signal turns off the PMOS transistor 3 of the redundancy decoder circuit to deactivate the redundancy decoder circuit.

In the case of entering the non-select mode by the PDOWN and CS signals, when the two signals are input to the NAND gate, a high level non-select signal is output. This is possible only if the NAND gate combines the two signals, thus enabling the redundant word line.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of improving the enable time of a redundant word line more quickly.

1 is a circuit diagram showing a configuration of a redundancy decoder circuit and its peripheral circuit according to the prior art:

2 is a circuit diagram showing a configuration of a redundancy decoder circuit and its peripheral circuits according to a preferred embodiment of the present invention:

3 shows an output of a power on reset signal:

* Explanation of symbols on main parts of the drawings

100: redundancy decoder circuit 200: control circuit

210: first control circuit 220: second control circuit

(Configuration)

According to one aspect of the present invention, there is provided a semiconductor memory device including a redundancy decoder circuit for repairing defective cells, the semiconductor memory device comprising: a first control circuit that receives a chip select signal and activates the redundancy decoder circuit; A second control circuit for receiving a first signal and a second signal deactivating the redundancy decoder circuit and generating a non-selection signal for entering the redundancy decoder circuit into a non-selection mode; And a driver circuit for receiving and driving the first control signal or the non-select signal, the redundancy decoder circuit being deactivated when the first and second signals are activated.

In a preferred embodiment, the second control circuit comprises a NOR gate at which input terminals receive the second and third signals, and an inverter at which an input terminal is connected to an output terminal of the NOR gate.

(Example)

Hereinafter, a reference drawing according to a preferred embodiment of the present invention will be described with reference to FIGS. 2 and 3.

2 is a circuit diagram illustrating a configuration of a redundancy decoder circuit and its peripheral circuits according to an exemplary embodiment of the present invention.

The redundancy decoder circuit 100 includes an enable circuit 110 having master fuses Fm1 and Fm2, transistors 104 and 105 for precharging a node, and a data storage circuit 120. The data storage circuit 120 includes an NMOS transistor NM1 having a channel formed between the fuses F1 to F6 having one end connected to the first node N1 and the other end of the fuses F1 to F6 and ground. To NM6).

Referring to FIG. 2, the redundancy decoder circuit 100 determines whether to enter the non-select mode or the select mode due to the first and second control circuits 210 and 220. The first control circuit 210 receives the chip select signal CS to enable the redundancy decoder circuit 100. The second control circuit 220 receives the first (PORESET) and the second signal (PDOWN) to enter the non-selection mode to deactivate the redundancy decoder circuit (100). The second control circuit 220 includes a NOR gate 221 for inputting a first (PORESET) and a second signal (PDOWN) and an inverter 222 connected in series thereto.

FIG. 3 is a view illustrating an output of the first signal PORESET. When the first control signal PORESET and the second control signal PDOWN of the high level are applied to the second control circuit in the non-selection mode, the NOR gate 221 is applied. The high level signal is finally outputted to the inverter 222 via the < RTI ID = 0.0 > This turns on 223 to latch N2 to the low level.

Since the chip select signal CS activates the redundant word line, the chip select signal CS affects the speed. The second control signal PDOWN does not affect the speed of the redundant decoder circuit, so the two signals are separated as shown in FIG. The low level N2 outputs a high level deselect signal through the inverter 224. Since the output node of the inverter 224 corresponds to a long bussing line, the driving force must be as large as the number of redundancy decoders, so using an inverter than the conventional NAND gate is a great help in speeding up.

The high level deselect signal is transmitted to the redundancy decoder circuit through a delay circuit. As a result, 104 and 105 are turned off to maintain the non-select mode. In addition, the second control circuit 220 may receive a signal as shown in FIG. 3 to reduce standby current consumption in the non-select mode. Conventionally, CS and PDOWN are combined through a NAND gate to enter a selection mode from a non-selection mode through a delay circuit. However, in the present invention, as the inverter is used instead of the NAND gate, the speed is further improved by a delayed section of the NAND gate, so that a redundant word line enable time can be brought faster.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

Therefore, the present invention has the effect of bringing the enable time of the redundant word line faster.

Claims (2)

A semiconductor memory device having a redundancy decoder circuit for repairing defective cells, comprising: A first control circuit for accepting a chip select signal to activate a redundancy decoder circuit; A second control circuit for receiving a first signal and a second signal to deactivate the redundancy decoder circuit and generating a non-select signal for entering the redundancy decoder circuit into a non-select mode; A latch circuit for receiving and storing the non-selection signal; A driving circuit for receiving the first control signal or the non-selection signal and driving the same; The redundancy decoder circuit is inactivated when the first and second signals are activated. The method of claim 1, The second control circuit includes a NOR gate at which input terminals receive the second and third signals; And an inverter having an input terminal connected to an output terminal of the NOR gate.