KR19990060831A - Contact hole formation method of semiconductor device - Google Patents
Contact hole formation method of semiconductor device Download PDFInfo
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- KR19990060831A KR19990060831A KR1019970081077A KR19970081077A KR19990060831A KR 19990060831 A KR19990060831 A KR 19990060831A KR 1019970081077 A KR1019970081077 A KR 1019970081077A KR 19970081077 A KR19970081077 A KR 19970081077A KR 19990060831 A KR19990060831 A KR 19990060831A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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Abstract
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 반도체 소자의 제조 공정에서 층간 절연막은 표면 평탄화를 위해 보론 포스포러스 실리카 글라스(boron phosphorous silica glass; BPSG)를 사용하며, 이 층간 절연막의 선택된 부분을 식각하여 콘택홀을 형성하게 되는데, 층간 절연막으로 사용되는 보론 포스포러스 실리카 글라스의 보론(B)과 포스포러스(P)의 농도를 두께가 증가함에 따라 선형적으로 증가시켜 층간 절연막을 형성하므로, 버티컬 콘택홀(vertical contact hole)을 형성한 후 버퍼드 옥사이드 에첸트(buffered oxide etchant; BOE)를 사용한 세정(cleaning)으로 경사 콘택홀(sloped contact hole)을 얻을 수 있어, 금속 콘택 공정을 용이하게 실시할 수 있게 하는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, wherein an interlayer insulating film uses boron phosphorous silica glass (BPSG) for surface planarization in a semiconductor device manufacturing process, and selected portions of the interlayer insulating film. Is formed to form a contact hole, since the concentrations of boron (B) and phosphorus (P) in the boron phosphor silica glass used as the interlayer insulating film increase linearly as the thickness increases, thereby forming the interlayer insulating film, After forming a vertical contact hole, a sloped contact hole can be obtained by cleaning using a buffered oxide etchant (BOE), thereby facilitating a metal contact process. The present invention relates to a method for forming a contact hole in a semiconductor device.
Description
본 발명은 반도체 소자의 콘택홀 형성 방법에 관한 것으로, 층간 절연막에 사용되는 보론 포스포러스 실리카 글라스(boron phosphorous silica glass; BPSG)의 보론(B)과 포스포러스(P)의 농도를 두께가 증가함에 따라 선형적으로 증가시켜 버티컬 콘택 식각(vertical contact etch) 및 세정(cleaning)으로 경사 콘택홀(sloped contact hole)을 용이하게 형성할 수 있는 반도체 소자의 콘택홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, wherein the concentration of boron (B) and phosphorus (P) in boron phosphorous silica glass (BPSG) used in an interlayer insulating film is increased. Accordingly, the present invention relates to a method for forming a contact hole in a semiconductor device which can be easily formed by vertical contact etch and cleaning to form a sloped contact hole.
일반적으로, 반도체 소자의 제조 공정에서 층간 절연막은 표면 평탄화를 위해 보론 포스포러스 실리카 글라스를 사용하며, 이 층간 절연막의 선택된 부분을 식각하여 콘택홀을 형성하게 된다. 반도체 소자가 고집적화 되어감에 따라 기존의 건식 식각 기술로는 2.5㎛ 이상의 깊이를 갖으며, 0.3㎛ 이하의 폭을 갖는 콘택홀을 형성할 때, 식각면이 경사지게 형성하기가 불가능하다. 경사가 지지 않은 깊은 버티컬 콘택홀에서 금속을 증착 하게 되면 콘택홀의 상단부가 콘택홀의 하단부보다 더 빠른 속도로 증착 되는 소위 오버-행(over-hang) 이라 불리는 현상이 발생하여 콘택홀의 하단부에 금속이 완전히 채워지기 전에 콘택홀의 상단부가 막혀 콘택의 중앙에 보이드(void)가 형성되게 된다. 이러한 보이드는 소자의 신뢰성을 나쁘게 하여 생산 수율에 치명적인 악영향을 미치는 단점으로 대두된다.In general, in the process of manufacturing a semiconductor device, the interlayer insulating film uses boron phosphor silica glass to planarize the surface, and select portions of the interlayer insulating film are etched to form contact holes. As semiconductor devices have been highly integrated, conventional etching methods have a depth of 2.5 μm or more, and when forming contact holes having a width of 0.3 μm or less, it is impossible to form an inclined etching surface. When metal is deposited in a deep vertical non-sloped contact hole, a phenomenon called so-called over-hang occurs in which the upper end of the contact hole is deposited at a faster rate than the lower end of the contact hole. Before filling, the upper end of the contact hole is blocked so that a void is formed in the center of the contact. These voids emerge as a disadvantage that adversely affects the production yield by deteriorating the reliability of the device.
따라서, 본 발명은 층간 절연막에 사용되는 보론 포스포러스 실리카 글라스(BPSG)의 보론(B)과 포스포러스(P)의 농도를 두께가 증가함에 따라 선형적으로 증가시켜 버티컬 콘택 식각 및 세정으로 경사 콘택홀을 형성하므로써, 금속 콘택 공정을 용이하게 실시할 수 있게 하는 반도체 소자의 콘택홀 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention linearly increases the concentrations of boron (B) and phosphorus (P) of boron phosphor silica glass (BPSG) used in the interlayer insulating film as the thickness increases, thereby inclining contact by vertical contact etching and cleaning. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device which makes it possible to easily perform a metal contact process by forming a hole.
이러한 목적을 달성하기 위한 본 발명의 콘택홀 형성 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 반도체 웨이퍼 상에 보론 포스포러스 실리카 글라스(BPSG)를 사용하여 층간 절연막을 형성하되, 상기 층간 절연막의 하단부보다 상단부쪽으로 갈수록 보론(B) 및 포스포러스(P)의 농도가 증가되도록 형성하는 단계; 비등방성 식각 공정으로 상기 층간 절연막의 선택된 부분을 식각하여 버티컬 콘택홀을 형성하는 단계; 및 상기 버티컬 콘택홀을 버퍼드 옥사이드 에첸트(BOE) 용액으로 세정하여, 이로 인하여 상기 버티컬 콘택홀을 경사 콘택홀이 되도록 하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In order to achieve the above object, the contact hole forming method of the present invention forms an interlayer insulating film using boron phosphor silica glass (BPSG) on a semiconductor wafer having various elements for forming a semiconductor device. Forming a concentration of boron (B) and phosphorus (P) to increase toward an upper end than a lower end of the; Etching a selected portion of the interlayer insulating layer by an anisotropic etching process to form a vertical contact hole; And cleaning the vertical contact hole with a buffered oxide etchant (BOE) solution, thereby making the vertical contact hole an inclined contact hole.
도 1은 층간 절연막으로 사용되는 보론 포스포러스 실리카 글라스의 보론(B)과 포스포러스(P)의 농도를 두께가 증가함에 따라 선형적으로 증가시키는 방법을 설명하기 위해 도시한 도면.1 is a view for explaining a method of linearly increasing the concentration of boron (B) and phosphorus (P) of boron phosphor silica glass used as an interlayer insulating film as the thickness increases.
도 2(a) 및 도 2(b)는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위해 도시된 소자의 단면도.2 (a) and 2 (b) are cross-sectional views of a device shown to explain a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
1: 화학적 기상 증착 챔버 2A 내지 2E: 노즐1: Chemical Vapor Deposition Chamber 2A to 2E: Nozzle
10: 반도체 웨이퍼 11: 층간 절연막10: semiconductor wafer 11: interlayer insulating film
12: 감광막 패턴 13A: 버티컬 콘택홀12: Photoresist pattern 13A: Vertical contact hole
13B: 경사 콘택홀13B: Inclined Contact Hole
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1은 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 반도체 웨이퍼 상에 층간 절연막으로 사용되는 보론 포스포러스 실리카 글라스의 보론(B)과 포스포러스(P)의 농도를 두께가 증가함에 따라 선형적으로 증가시키는 방법을 설명하기 위해 도시한 도면이고, 도 2(a) 및 도 2(b)는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성 방법을 설명하기 위해 도시된 소자의 단면도이다.FIG. 1 is a graph illustrating linear concentrations of boron (B) and phosphorus (P) of boron phosphor silica glass used as an interlayer insulating film on a semiconductor wafer having various elements for forming a semiconductor device. 2A and 2B are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to an embodiment of the present invention.
도 1을 참조하면, 화학적 기상 증착(CVD) 챔버(1)에 다수의 노즐(2A 내지 2E)이 구비되고, 웨이퍼(10)를 제 1 노즐(2A)에서부터 제 5 노즐(2E)까지 순차적으로 통과하게 하여 웨이퍼(10)상에 보론 포스포러스 실리카 글라스를 증착 시킨다. 제 1 노즐(2A)에서는 보론(B)과 포스포러스(P)의 농도가 낮은 상태의 보론 포스포러스 실리카 글라스가 분사되도록 하고, 제 2 노즐(2B), 제 3 노즐(2C), 제 4 노즐(2D), 제 5 노즐(2E)로 갈수록 보론(B)과 포스포러스(P)의 농도가 증가된 상태의 보론 포스포러스 실리카 글라스가 분사되도록 한다.Referring to FIG. 1, a plurality of nozzles 2A to 2E are provided in the chemical vapor deposition (CVD) chamber 1, and the wafer 10 is sequentially moved from the first nozzles 2A to the fifth nozzles 2E. The boron phosphor silica glass is deposited on the wafer 10 by passing through it. In the 1st nozzle 2A, boron phosphorus silica glass of the state where the density | concentration of boron B and phosphorus P is low is sprayed, and the 2nd nozzle 2B, the 3rd nozzle 2C, and the 4th nozzle 2D and the fifth nozzle 2E, the boron phosphor silica glass in which the concentrations of boron B and phosphorus P are increased is sprayed.
보론 포스포러스 실리카 글라스 증착시 보론(B)의 농도는 0 내지 10% 로하고, 포스포러스(P)의 농도는 0 내지 10%로 하여 각각의 농도를 선형적으로 증가시킨다. 보론 포스포러스 실리카 글라스는 상압, 플라즈마 증가 또는 저압 화학적 기상 증착(APCVD, PECVD 또는 LPCVD) 방식으로 증착 한다.In the case of boron phosphor silica glass deposition, the concentration of boron (B) is set to 0 to 10% and the concentration of phosphorus (P) is set to 0 to 10%, thereby increasing each concentration linearly. Boron phosphor silica glass is deposited by atmospheric pressure, plasma enhanced or low pressure chemical vapor deposition (APCVD, PECVD or LPCVD).
도 2(a)를 참조하면, 상기한 방법으로 증착된 보론 포스포러스 실리카 글라스가 사용된 층간 절연막(11)의 선택된 부분을 감광막 패턴(12)을 식각 마스크로 한 비등방성 식각 공정으로 식각하여 반도체 웨이퍼(10)가 노출되는 버티컬 콘택홀(13A)이 형성된다.Referring to FIG. 2 (a), the selected portion of the interlayer insulating film 11 using the boron phosphor silica glass deposited by the above method is etched by an anisotropic etching process using the photoresist pattern 12 as an etching mask. A vertical contact hole 13A through which the wafer 10 is exposed is formed.
도 2(b)를 참조하면, 감광막 패턴(12)을 제거하고, 버티컬 콘택홀(13A) 형성을 위한 식각 공정으로 콘택홀(13A) 내에 존재하는 감광막의 찌꺼기 또는 옥사이드 잔존물을 없앨 목적으로 버퍼드 옥사이드 에첸트(BOE) 용액으로 세정 공정을 실시하여, 이로 인하여 버티컬 콘택홀(13A)의 식각면이 일부 제거되면서 경사 콘택홀(13B)이 형성된다.Referring to FIG. 2 (b), the photoresist pattern 12 is removed and buffered for the purpose of removing residues or oxide residues of the photoresist film present in the contact hole 13A by an etching process for forming the vertical contact hole 13A. Since the cleaning process is performed with an oxide etchant (BOE) solution, the inclined contact hole 13B is formed while partially removing the etched surface of the vertical contact hole 13A.
상기에서, BOE 용액으로 세정 공정을 실시할 때, 보론 포스포러스 실리카 글라스로 된 층간 절연막(11)의 식각 정도는 보론(B) 또는 포스포러스(P)의 농도가 증가될수록 높다. 따라서, 본 발명에 적용된 층간 절연막(11)은, 도 1에서 설명한 바와 같이, 층간 절연막(11)의 하단부보다 상단부쪽으로 갈수록 보론(B) 및 포스포러스(P)의 농도가 증가되기 때문에 층간 절연막(11)의 상단부가 빨리 식각 되고, 하단부가 늦게 식각 되어 경사 콘택홀(13B) 형성이 가능하다. BOE 용액은 NH4F와 H2O의 비가 1 : 300 또는 1 : 100 으로 하여 사용한다.In the above, when the cleaning process is performed with a BOE solution, the etching degree of the interlayer insulating film 11 made of boron phosphor silica glass is higher as the concentration of boron (B) or phosphorus (P) is increased. Therefore, as described in FIG. 1, the interlayer insulating film 11 applied to the present invention increases the concentration of boron (B) and phosphorus (P) toward the upper end than the lower end of the interlayer insulating film 11. The upper end of 11) is etched quickly, and the lower end is etched late to form the inclined contact hole 13B. The BOE solution is used with the ratio of NH 4 F and H 2 O as 1: 300 or 1: 100.
이와 같이, 경사 콘택홀(13B)을 용이하게 얻을 수 있어, 이러한 경사 콘택홀(13B)에 금속 콘택 공정을 실시할 경우 금속 스텝 커버리지가 향상되어 종래와 같은 보이드 등이 발생되지 않는다.As described above, the inclined contact hole 13B can be easily obtained, and when the metal contact process is performed on the inclined contact hole 13B, the metal step coverage is improved, and voids and the like are not generated.
상술한 바와 같이, 본 발명은 반도체 소자의 제조 공정에서 층간 절연막으로 사용되는 보론 포스포러스 실리카 글라스의 보론(B)과 포스포러스(P)의 농도를 두께가 증가함에 따라 선형적으로 증가시켜 층간 절연막을 형성하므로, 버티컬 콘택홀을 형성한 후 버퍼드 옥사이드 에첸트(BOE)를 사용한 세정으로 경사 콘택홀을 얻을 수 있어, 금속 콘택 공정시 금속 스텝 커버리지를 개선시킬 수 있어 소자의 신뢰성을 향상시킬 수 있다.As described above, the present invention is to increase the concentration of boron (B) and phosphorus (P) of boron phosphor silica glass used as an interlayer insulating film in the manufacturing process of a semiconductor device by increasing the thickness linearly to increase the interlayer insulating film Since the vertical contact hole is formed, the inclined contact hole can be obtained by using a buffered oxide etchant (BOE) to improve the metal step coverage during the metal contact process, thereby improving the reliability of the device. have.
Claims (5)
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| JPH04369854A (en) * | 1991-06-18 | 1992-12-22 | Seiko Instr Inc | Semiconductor device and manufacture thereof |
| KR930003278A (en) * | 1991-07-08 | 1993-02-24 | 김광호 | Formation of openings with gentle profile |
| KR100269595B1 (en) * | 1992-05-14 | 2000-10-16 | 김영환 | Method of forming contact hole with improved profile |
| KR960000368B1 (en) * | 1992-07-28 | 1996-01-05 | 삼성전자주식회사 | Semiconductor device and fabricating method thereof |
| KR960002063B1 (en) * | 1992-10-21 | 1996-02-10 | Lg Semicon Co Ltd | Forming method of contact hole in semiconductor device |
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| CN113690218B (en) * | 2020-05-18 | 2023-11-07 | 中国科学院微电子研究所 | Semiconductor device, manufacturing method and electronic equipment |
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