KR19990060821A - Method of forming barrier metal layer of metal wiring in semiconductor device - Google Patents
Method of forming barrier metal layer of metal wiring in semiconductor device Download PDFInfo
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- KR19990060821A KR19990060821A KR1019970081067A KR19970081067A KR19990060821A KR 19990060821 A KR19990060821 A KR 19990060821A KR 1019970081067 A KR1019970081067 A KR 1019970081067A KR 19970081067 A KR19970081067 A KR 19970081067A KR 19990060821 A KR19990060821 A KR 19990060821A
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- titanium
- layer
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- barrier metal
- metal layer
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 46
- 239000002184 metal Substances 0.000 title claims abstract description 46
- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000004888 barrier function Effects 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title abstract description 7
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 11
- LCKIEQZJEYYRIY-UHFFFAOYSA-N Titanium ion Chemical compound [Ti+4] LCKIEQZJEYYRIY-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 64
- 239000010936 titanium Substances 0.000 claims description 32
- 229910052719 titanium Inorganic materials 0.000 claims description 25
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 23
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 13
- 239000010703 silicon Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 12
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 9
- 239000011229 interlayer Substances 0.000 claims description 9
- 150000002500 ions Chemical class 0.000 claims description 5
- -1 titanium ions Chemical class 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76858—After-treatment introducing at least one additional element into the layer by diffusing alloying elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76823—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. transforming an insulating layer into a conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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Abstract
본 발명은 반도체 소자의 금속 배선에서 장벽 금속층(barrier metal layer)의 접착층(adhesion layer)을 스퍼터링법(sputtering) 대신에 티타늄(Ti) 이온 주입법으로 형성하므로, 균일한 두께 및 농도를 갖는 티타늄 실리사이드(TiSi2)를 형성할 수 있고, 콘택 저항을 낮출 수 있는 반도체 소자에서 금속 배선의 장벽 금속층 형성 방법에 관한 것이다.According to the present invention, since an adhesion layer of a barrier metal layer is formed by a titanium ion implantation method instead of sputtering in a metal wiring of a semiconductor device, titanium silicide having a uniform thickness and concentration ( A method for forming a barrier metal layer of a metal wiring in a semiconductor device capable of forming TiSi 2 ) and lowering a contact resistance.
Description
본 발명은 반도체 소자에서 금속 배선의 장벽 금속층(barrier metal layer) 형성 방법에 관한 것으로, 특히 장벽 금속층의 접착층(adhesion layer) 형성 공정의 개선을 통해 균일한 두께 및 농도를 갖는 티타늄 실리사이드(TiSi2)층을 형성할 수 있고, 콘택 저항 및 스텝 커버리지(step coverage)를 개선할 수 있는 반도체 소자에서 금속 배선의 장벽 금속층 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a barrier metal layer of a metal wiring in a semiconductor device. In particular, titanium silicide (TiSi 2 ) having a uniform thickness and concentration through an improvement in the process of forming an adhesion layer of the barrier metal layer is disclosed. A method for forming a barrier metal layer of metal wiring in a semiconductor device capable of forming a layer and improving contact resistance and step coverage.
일반적으로, 반도체 소자의 금속 배선에서 장벽 금속층은 티타늄(Ti)과 티타늄 나이트라이드(TiN)의 이중층(double layer)으로 구성된다. 티타늄층은 금속 배선의 주 재료인 텅스텐(W)이나 알루미늄(Al)이 하부층과 잘 접착되도록 하는 접착층 역할을 하면서, 실리콘 기판과 반응하여 티타늄 실리사이드층(Ti silicide layer)을 형성하므로 콘택 저항을 낮추어 주는 역할을 한다. 티타늄 나이트라이드층은 금속 배선의 주 재료인 텅스텐(W)이나 알루미늄(Al)이 실리콘 기판과 직접 반응하는 것을 차단하는 확산 장벽층(diffusion barrier layer) 역할을 하면서, 금속층 증착시 시드층(seed layer) 역할을 한다.In general, in the metal wiring of a semiconductor device, the barrier metal layer is composed of a double layer of titanium (Ti) and titanium nitride (TiN). The titanium layer acts as an adhesive layer that allows the tungsten (W) or aluminum (Al), which is the main material of the metal wiring, to adhere well to the lower layer, and forms a titanium silicide layer by reacting with the silicon substrate to lower the contact resistance. Role. The titanium nitride layer serves as a diffusion barrier layer that blocks the direct reaction of tungsten (W) or aluminum (Al), which is the main material of the metal wiring, with the silicon substrate, and is a seed layer when the metal layer is deposited. ) Plays a role.
최근, 반도체 소자의 고집적화로 금속 콘택홀의 애스택트 비(aspect ratio)가 커지게 되어, 장벽 금속층의 스텝 커버리지가 나빠지게 된다. 즉, 티타늄층이 콘택홀 저면부에서 스텝 커버리지가 나빠지게 되면, 콘택 저항이 증가되는 주요 원인으로 작용하게 된다. 티타늄층은 주로 물리적 기상 증착법(PVD)으로 증착 하는데, 스텝 커버리지를 개선시키기 위하여, 이온화된 금속 물리적 기상 증착법(Ionized Metal PVD; IMP) 또는 화학적 기상 증착법(CVD)등을 적용하여 증착하고 있다. 이온화된 금속 물리적 기상 증착법은 증착 균일도(deposition uniformity)가 10% 이상으로 너무 나쁜 단점이 있으며, 화학 기상 증착법은 금속 본질 화학 기상 증착법(Metal Organic CVD; MOCVD)을 적용하는 관계로 카본(carbon) 등의 이물질들이 티타늄층을 오염(contamination)시키는 문제가 있다.In recent years, due to the high integration of semiconductor devices, the aspect ratio of the metal contact holes is increased, resulting in poor step coverage of the barrier metal layer. That is, when the titanium layer has a poor step coverage at the bottom of the contact hole, the titanium layer acts as a main cause of increasing the contact resistance. The titanium layer is mainly deposited by physical vapor deposition (PVD). In order to improve step coverage, ionized metal PVD (IMP) or chemical vapor deposition (CVD) is applied. Ionized metal physical vapor deposition method has a disadvantage that the deposition uniformity (deposition uniformity) is more than 10% is too bad, and chemical vapor deposition method is applied to metal organic chemical vapor deposition (MOCVD), carbon (carbon), etc. Foreign matters contaminate the titanium layer.
따라서, 본 발명은 장벽 금속층의 접착층의 스텝 커버리지 불량으로 인한 소자의 전기적 특성 저하를 방지하면서 균일한 두께 및 농도를 갖는 티타늄 실리사이드층을 형성할 수 있고, 콘택 저항을 낮출 수 있는 금속 배선의 장벽 금속층 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention can form a titanium silicide layer having a uniform thickness and concentration while preventing the deterioration of electrical characteristics of the device due to poor step coverage of the adhesive layer of the barrier metal layer, and the barrier metal layer of the metal wiring capable of lowering the contact resistance. The purpose is to provide a forming method.
이러한 목적을 달성하기 위한 본 발명의 장벽 금속층 형성 방법은 층간 절연막의 일부분을 식각 하여 실리콘 기판의 일부가 노출되는 콘택홀을 형성한 후, 티타늄 이온 주입 공정을 실시하여 티타늄층을 형성하는 단계; 상기 콘택홀을 포함한 상기 층간 절연막 상에 티타늄 나이트라이드층이 형성하여, 이로 인하여 상기 티타늄층과 상기 티타늄 나이트라이드층으로 된 장벽 금속층이 형성되는 단계; 및 상기 장벽 금속층을 열처리하여 상기 콘택홀 저면을 이루는 상기 실리콘 기판에 티타늄 실리사이드층을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The barrier metal layer forming method of the present invention for achieving the above object comprises etching a portion of the interlayer insulating film to form a contact hole to expose a portion of the silicon substrate, and then performing a titanium ion implantation process to form a titanium layer; Forming a titanium nitride layer on the interlayer insulating film including the contact hole, thereby forming a barrier metal layer comprising the titanium layer and the titanium nitride layer; And heat treating the barrier metal layer to form a titanium silicide layer on the silicon substrate forming the contact hole bottom surface.
도 1(a) 내지 도 1(d)는 본 발명의 실시예에 따른 금속 배선의 장벽 금속층 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of devices for explaining a method for forming a barrier metal layer of metal wiring according to an embodiment of the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
1: 실리콘 기판 2: 접합부1: silicon substrate 2: junction
3: 층간 절연막 4: 콘택홀3: interlayer insulating film 4: contact hole
5: 티타늄층 6: 티타늄 나이트라이드층5: titanium layer 6: titanium nitride layer
7: 티타늄 실리사이드층 10: 장벽 금속층7: titanium silicide layer 10: barrier metal layer
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1(a) 내지 도 1(d)는 본 발명의 실시예에 따른 금속 배선의 장벽 금속층 형성 방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of devices for explaining a method for forming a barrier metal layer of metal wiring according to an embodiment of the present invention.
도 1(a)를 참조하면, 접합부(2)가 형성된 실리콘 기판(1)상에 층간 절연막(3)을 형성하고, 층간 절연막(3)의 일부분을 식각 하여 접합부(2)가 노출되는 콘택홀(4)이 형성된다.Referring to FIG. 1A, an interlayer insulating film 3 is formed on a silicon substrate 1 having a junction part 2 formed thereon, and a portion of the interlayer insulating film 3 is etched to expose a junction hole 2. (4) is formed.
도 1(b)를 참조하면, 티타늄 이온 주입 공정을 실시하여 콘택홀(4)을 통해 노출된 실리콘 기판(1)의 표면부 및 층간 절연막(3)의 표면부에 티타늄층(5)이 형성된다.Referring to FIG. 1B, a titanium layer 5 is formed on the surface of the silicon substrate 1 and the surface of the interlayer insulating layer 3 exposed through the contact hole 4 by performing a titanium ion implantation process. do.
티타늄 이온 주입 공정은 티타늄 소오스 가스로 티타늄이 포함된 TiCl4, Ti(N(CH3)2)4, 티타늄 금속 증기(Ti metal evaporation) 등의 가스를 이용하여 이온 주입 장비에서 Ti+이온을 생성시키고, Ti+이온만을 2 내지 100 KeV의 에너지로 가속시켜 주입한다. 이때 티타늄 이온의 도우즈(dose)는 1E15 내지 1E17 정도로 하고, 이온 주입 장비는 약 10_5Torr 의 고진공 상태로 유지된다.The titanium ion implantation process generates Ti + ions in the ion implantation equipment by using a gas such as TiCl 4 , Ti (N (CH 3 ) 2 ) 4 , titanium metal evaporation, which contains titanium as a titanium source gas. And only Ti + ions are injected to accelerate the energy to 2 to 100 KeV. The dose of titanium ions is about 1E15 to 1E17, and the ion implantation equipment is maintained at a high vacuum of about 10 _5 Torr.
도 1(c)를 참조하면, 화학 기상 증착법 또는 물리적 화학 기상 증착법으로 콘택홀(4)을 포함한 층간 절연막(3)상에 티타늄 나이트라이드층(6)이 형성된다. 티타늄층(5)과 티타늄 나이트라이드층(6)으로 된 장벽 금속층(10)이 형성된다.Referring to FIG. 1C, the titanium nitride layer 6 is formed on the interlayer insulating layer 3 including the contact hole 4 by chemical vapor deposition or physical chemical vapor deposition. A barrier metal layer 10 consisting of a titanium layer 5 and a titanium nitride layer 6 is formed.
도 1(d)를 참조하면, 장벽 금속층(10)을 열처리하여 콘택홀(4) 저면을 이루는 실리콘 기판(1) 표면부에 티타늄 실리사이드층(7)이 형성된다. 티타늄 실리사이드층(7)은 열처리 공정 동안에 실리콘 기판(1)에 형성된 티타늄층(5)의 티타늄 이온과 실리콘 기판(1)의 실리콘 이온이 반응하여 40 내지 1000Å의 두께로 형성된다.Referring to FIG. 1D, a titanium silicide layer 7 is formed on the surface of the silicon substrate 1 forming the bottom surface of the contact hole 4 by heat-treating the barrier metal layer 10. The titanium silicide layer 7 is formed to a thickness of 40 to 1000 kPa by the reaction between the titanium ions of the titanium layer 5 formed on the silicon substrate 1 and the silicon ions of the silicon substrate 1 during the heat treatment process.
이후, 텅스텐(W) 또는 알루미늄(Al) 등으로 금속층 증착 및 패터닝 공정으로 금속 배선이 형성된다.Subsequently, a metal wiring is formed by a metal layer deposition and patterning process using tungsten (W) or aluminum (Al).
상술한 바와 같이, 본 발명은 티타늄층을 2 내지 100 KeV의 에너지로 이온 주입하여 형성하므로 스텝 커버리지로 인한 문제점을 배제시킬 수 있고, 티타늄 이온 주입시 티타늄 이온의 도우즈를 1E15 내지 1E17 정도로 하므로 티타늄 실리사이드층을 충분히 형성시킬 수 있을 뿐만 아니라, 티타늄 실리사이드층은 주입된 티타늄 원자와 실리콘 원자가 직접 반응하여 형성되기 때문에 실리시데이션(silicidation)이 보다 원활하게 이루어져 균일한 두께 및 농도를 갖게 되며, 티타늄 이온은 이온 주입시 직진성을 갖기 때문에 웨이퍼의 표면부분이나 좁은 콘택홀의 하부 지역에 이온의 양을 동일하게 주입할 수 있다.As described above, the present invention is formed by ion implantation of the titanium layer with energy of 2 to 100 KeV, which can eliminate problems due to step coverage, and the titanium ion dose is about 1E15 to 1E17 during titanium ion implantation. Not only can the silicide layer be sufficiently formed, but the titanium silicide layer is formed by directly reacting the injected titanium atoms with the silicon atoms, so that silicidation is more smooth and uniform thickness and concentration are achieved. Since silver has a straightness upon ion implantation, the amount of ions can be equally injected into the surface portion of the wafer or the lower region of the narrow contact hole.
따라서, 본 발명은 장벽 금속층의 티타늄층을 이온 주입 공정으로 형성하므로 스텝 커버리지에 대한 문제점을 배제시킬 수 있을 뿐만 아니라, 콘택 저항을 낮출 수 있어 소자의 전기적 특성 및 수율을 향상시킬 수 있다.Therefore, since the titanium layer of the barrier metal layer is formed by an ion implantation process, the present invention can not only eliminate the problem of step coverage, but also lower the contact resistance, thereby improving the electrical characteristics and the yield of the device.
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