KR19990059065A - Method of manufacturing thin film transistor of semiconductor device - Google Patents
Method of manufacturing thin film transistor of semiconductor device Download PDFInfo
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- KR19990059065A KR19990059065A KR1019970079262A KR19970079262A KR19990059065A KR 19990059065 A KR19990059065 A KR 19990059065A KR 1019970079262 A KR1019970079262 A KR 1019970079262A KR 19970079262 A KR19970079262 A KR 19970079262A KR 19990059065 A KR19990059065 A KR 19990059065A
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- 239000010409 thin film Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000010408 film Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000005229 chemical vapour deposition Methods 0.000 claims description 13
- 150000004767 nitrides Chemical class 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- RLOWWWKZYUNIDI-UHFFFAOYSA-N phosphinic chloride Chemical compound ClP=O RLOWWWKZYUNIDI-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
- H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
- H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Chemical & Material Sciences (AREA)
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- Semiconductor Memories (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 박막 트랜지스터(thin film transistor; TFT) 제조 방법에 관한 것으로, 반도체 소자에서 스택 랜덤 액세스 메모리(SRAM) 소자 및 액정 표시기(liquid crystal display; LCD) 제조 공정에 사용되는 바텀 게이트(bottom gate) 구조의 박막 트랜지스터의 게이트 절연막을 산화막-질화막-산화막(oxide-nitride-oxide)의 ONO 구조로 형성하여 게이트 절연막의 막질을 개선시키므로, 박막 트랜지스터의 절연 파괴 전압(break down voltage)을 증대시키고 누설 전류(leakage current)를 감소시켜 소자의 신뢰성을 향상시킬 수 있는 박막 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor (TFT), and is a bottom gate used in a stack random access memory (SRAM) device and a liquid crystal display (LCD) manufacturing process in a semiconductor device. The gate insulating film of the thin film transistor having the structure is formed in the ONO structure of the oxide-nitride-oxide film to improve the film quality of the gate insulating film, thereby increasing breakdown voltage and increasing leakage current of the thin film transistor. The present invention relates to a method of manufacturing a thin film transistor that can improve the reliability of a device by reducing leakage current.
Description
본 발명은 박막 트랜지스터(thin film transistor; TFT) 제조 방법에 관한 것으로, 특히 바텀 게이트(bottom gate) 구조의 박막 트랜지스터의 게이트 절연막의 막질을 개선시킴에 의해 박막 트랜지스터의 절연 파괴 전압(break down voltage)를 증대시키고 누설 전류(leakage current)를 감소시켜 소자의 신뢰성을 향상시킬 수 있는 박막 트랜지스터 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor (TFT), and in particular, to improve the film quality of a gate insulating film of a thin film transistor having a bottom gate structure. The present invention relates to a thin film transistor manufacturing method capable of increasing the reliability and reducing the leakage current to improve the reliability of the device.
일반적으로, 박막 트랜지스터(thin film transistor; TFT)는 반도체 소자에서 스택 랜덤 액세스 메모리(SRAM) 소자 및 액정 표시기(liquid crystal display; LCD) 제조 공정에 널리 사용되고 있다. 반도체 소자가 고집적화 되어감에 따라 박막 트랜지스터의 동작 특성이 전체 소자의 동작 특성에 많은 영향을 미치게 된다.In general, thin film transistors (TFTs) are widely used in manufacturing processes of stacked random access memory (SRAM) devices and liquid crystal displays (LCDs) in semiconductor devices. As semiconductor devices are highly integrated, the operating characteristics of the thin film transistors have a great influence on the operating characteristics of the entire device.
도 1은 종래 박막 트랜지스터의 제조 방법을 설명하기 위한 소자 단면도이다.1 is a cross-sectional view of an element for describing a method of manufacturing a conventional thin film transistor.
도 1을 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(1)상에 게이트 전극(2), 게이트 절연막(3) 및 채널 영역(4)을 순차적으로 형성하여 박막 트렌지스터가 제조된다.Referring to FIG. 1, a thin film transistor is manufactured by sequentially forming a gate electrode 2, a gate insulating layer 3, and a channel region 4 on a substrate 1 having a structure in which various elements for forming a semiconductor device are formed. do.
게이트 전극(2)은 인-시튜(in-situ) 방식으로 n-타입 도프트 아몰포스 실리콘(n-type doped amorphous silicon)을 증착 시키거나, 약 620℃ 의 온도에서 언 도프트 폴리실리콘(undoped polysilicon) 을 증착 시킨 후, POCl3개스의 확산 주입이나 n-타입 도판트(dopant)의 이온 주입(inplantation) 방법을 이용하여 불순물을 도핑(doping)하여 제조한 후, 패터닝 공정으로 형성된다. 게이트 절연막(3)은 화학적 기상 증착(CVD) 방식으로 게이트 전극(2)상에 산화물(oxide)을 증착 하여 형성된다. 채널 영역(4)은 게이트 절연막(3)상에 폴리실리콘을 증착 하여 형성된다.The gate electrode 2 deposits n-type doped amorphous silicon in-situ, or undoped polysilicon at a temperature of about 620 ° C. After the deposition of polysilicon, the dopants are prepared by doping impurities using diffusion injection of POCl 3 gas or ion implantation method of n-type dopant, and then formed by patterning process. The gate insulating film 3 is formed by depositing an oxide on the gate electrode 2 by chemical vapor deposition (CVD). The channel region 4 is formed by depositing polysilicon on the gate insulating film 3.
상기한 방법으로 제조된 박막 트랜지스터는 게이트 절연막(3)이 화학적 기상 증착 방식으로 형성되기 때문에 누설 전류의 생성을 방지하는데 한계가 있어 박막 트랜지스터의 절연 파괴 전압(break down voltage)이 낮아지고, 온/오프 전류비(on/off current ratio) 또한 저하되는 문제점이 있다.The thin film transistor manufactured by the above-described method has a limit in preventing generation of leakage current because the gate insulating film 3 is formed by chemical vapor deposition, so that the breakdown voltage of the thin film transistor is lowered, There is also a problem in that the on / off current ratio is lowered.
따라서, 본 발명은 박막 트랜지스터의 게이트 절연막의 막질을 개선시킴에 의해 박막 트랜지스터의 절연 파괴 전압을 증대시키고 누설 전류를 감소시켜 소자의 신뢰성을 향상시킬 수 있는 박막 트랜지스터 제조 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method of manufacturing a thin film transistor which can improve the reliability of the device by increasing the dielectric breakdown voltage of the thin film transistor and reducing the leakage current by improving the film quality of the gate insulating film of the thin film transistor. .
이러한 목적을 달성하기 위한 본 발명의 박막 트랜지스터 제조 방법은 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판 상에 게이트 전극을 형성하는 단계; 상기 게이트 전극을 포함한 전체 구조상에 하부 산화막을 형성하는 단계; 상기 하부 산화막 상에 질화막을 형성하는 단계; 상기 질화막 상에 상부 산화막을 형성하여, 이로 인하여 상기 하부 산화막, 질화막 및 상부 산화막으로 된 게이트 절연막이 형성되는 단계; 및 상기 게이트 절연막 상에 채널 영역을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor, the method including: forming a gate electrode on a substrate having a structure in which various elements for forming a semiconductor device are formed; Forming a lower oxide film on the entire structure including the gate electrode; Forming a nitride film on the lower oxide film; Forming an upper oxide film on the nitride film, thereby forming a gate insulating film comprising the lower oxide film, the nitride film, and the upper oxide film; And forming a channel region on the gate insulating layer.
도 1은 종래 박막 트랜지스터의 제조 방법을 설명하기 위한 소자 단면도.1 is a cross-sectional view of an element for explaining a method of manufacturing a conventional thin film transistor.
도 2는 본 발명의 실시예에 따른 박막 트랜지스터의 제조 방법을 설명하기 위한 소자의 단면도.2 is a cross-sectional view of a device for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 및 11: 기판 2 및 12: 게이트 전극1 and 11: substrate 2 and 12: gate electrode
3 및 13: 게이트 절연막 13A: 하부 산화막3 and 13: gate insulating film 13A: lower oxide film
13B: 질화막 13C: 상부 산화막13B: nitride film 13C: upper oxide film
4 및 14: 채널 영역4 and 14: channel area
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 실시예에 따른 반도체 소자의 박막 트랜지스터 제조 방법을 설명하기 위한 소자의 단면도이다.2 is a cross-sectional view of a device for describing a method of manufacturing a thin film transistor of a semiconductor device according to an embodiment of the present invention.
도 2를 참조하면, 반도체 소자를 형성하기 위한 여러 요소가 형성된 구조의 기판(11)상에 게이트 전극(12), 게이트 절연막(13) 및 채널 영역(14)을 순차적으로 형성하여 박막 트렌지스터가 제조된다.Referring to FIG. 2, a thin film transistor is fabricated by sequentially forming a gate electrode 12, a gate insulating layer 13, and a channel region 14 on a substrate 11 having various elements for forming a semiconductor device. do.
게이트 전극(12)은 실리콘 소오스 가스(silicon source gas)로 모노 사일렌(SiH4) 가스 또는 디사일렌(Si2H6)가스를 사용하여 450 내지 800℃의 온도와 0.1 내지 1Torr의 압력에서 300 내지 2000Å의 두께로 도프트 폴리실리콘을 증착 시킨 후, 패터닝 공정으로 형성된다. 이때 도판트(dopant)의 농도는 약 5 × 1019atoms/cm3이상이 되도록 한다.Gate electrode 12 is a silicon source gas (silicon source gas) using a mono-silylene (SiH 4 ) gas or a disylene (Si 2 H 6 ) gas at a temperature of 450 to 800 ℃ and a pressure of 0.1 to 1 Torr After the doped polysilicon is deposited to a thickness of 300 to 2000 kPa, it is formed by a patterning process. At this time, the concentration of the dopant is about 5 × 10 19 atoms / cm 3 or more.
게이트 절연막(13)은 패터닝 공정 후에 50 : 1 HF 용액에 담근 후, H2O2를 함유하는 NH4OH 용액을 사용하여 실시되는 세정 공정시에 게이트 전극(12)상에 5 내지 30Å의 두께로 생성되는 하부 산화막(bottom oxide film; 13A)과, SiH2Cl2와 NH3가스를 소오스 가스로 하는 화학적 기상 증착(CVD) 방식으로 500 내지 900℃ 온도에서 30 내지 400Å의 두께로 하부 산화막(13A)상에 형성된 질화막(13B)과, SiH4와 N2O 가스 또는 Si2H6가스와 N2O 가스를 소오스 가스로 하는 화학적 기상 증착(CVD) 방식으로 500 내지 1000℃ 온도에서 30 내지 500Å의 두께로 질화막(13B)상에 형성된 상부 산화막(13C)을 순차적으로 형성하여 ONO 구조로 형성된다.The gate insulating film 13 is immersed in a 50: 1 HF solution after the patterning process, and then has a thickness of 5 to 30 kPa on the gate electrode 12 during the cleaning process performed using the NH 4 OH solution containing H 2 O 2 . The bottom oxide film (13A) is produced by the chemical vapor deposition (CVD) method using a source gas of SiH 2 Cl 2 and NH 3 gas as a source gas at a thickness of 30 to 400 Pa at a temperature of 500 to 900 ℃ ( 30 to at a temperature of 500 to 1000 ° C. by a chemical vapor deposition (CVD) method using a nitride film 13B formed on 13A) and SiH 4 and N 2 O gas or Si 2 H 6 gas and N 2 O gas as the source gas. An upper oxide film 13C formed on the nitride film 13B with a thickness of 500 Å was formed sequentially to form an ONO structure.
채널 영역(14)은 ONO 구조의 게이트 절연막(13)상에 언도프트 폴리실리콘층으로 형성된다.The channel region 14 is formed of an undoped polysilicon layer on the gate insulating film 13 of the ONO structure.
상술한 바와 같이, 본 발명은 반도체 소자에서 스택 랜덤 액세스 메모리(SRAM) 소자 및 액정 표시기(liquid crystal display; LCD) 제조 공정에 사용되는 바텀 게이트(bottom gate) 구조의 박막 트랜지스터의 게이트 절연막을 ONO 구조로 형성하여 게이트 절연막의 막질을 개선시키므로, 박막 트랜지스터의 절연 파괴 전압을 증대시키고, 누설 전류를 감소시키며, 온/오프 전류비를 향상시켜 소자의 신뢰성을 향상시킬 수 있다.As described above, the present invention provides an ONO structure for a gate insulating film of a bottom gate structure thin film transistor used in a stack random access memory (SRAM) device and a liquid crystal display (LCD) manufacturing process in a semiconductor device. Since the film quality of the gate insulating film is improved, the breakdown voltage of the thin film transistor can be increased, the leakage current can be reduced, and the on / off current ratio can be improved to improve the reliability of the device.
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| KR100400253B1 (en) * | 2001-09-04 | 2003-10-01 | 주식회사 하이닉스반도체 | Method for forming the thin film transistor of semiconductor device |
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| KR100400253B1 (en) * | 2001-09-04 | 2003-10-01 | 주식회사 하이닉스반도체 | Method for forming the thin film transistor of semiconductor device |
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