KR19990057933A - A method of forming a conductive film for planarization of semiconductor devices - Google Patents

A method of forming a conductive film for planarization of semiconductor devices Download PDF

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Publication number
KR19990057933A
KR19990057933A KR1019970078012A KR19970078012A KR19990057933A KR 19990057933 A KR19990057933 A KR 19990057933A KR 1019970078012 A KR1019970078012 A KR 1019970078012A KR 19970078012 A KR19970078012 A KR 19970078012A KR 19990057933 A KR19990057933 A KR 19990057933A
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South Korea
Prior art keywords
forming
bit line
insulating film
interlayer insulating
transistor
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KR1019970078012A
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Korean (ko)
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최경석
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김영환
현대전자산업 주식회사
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Priority to KR1019970078012A priority Critical patent/KR19990057933A/en
Publication of KR19990057933A publication Critical patent/KR19990057933A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/485—Bit line contacts

Abstract

본 발명은 평탄화된 전하저장전극의 플러그와 비트라인을 갖기 위한 반도체 소자 제조방법에 관한 것으로써, 반도체 기판상에 소스 및 드레인 접합을 갖는 트랜지스터를 형성하고 그 상부에 층간절연막을 형성하는 단계; 상기 층간절연막을 관통하여 상기 트랜지스터의 어느한 접합에 콘택되는 전하저장전극 콘택 플러그를 형성하는 단계; 상기 트랜지스터를 오픈시키지 않는 한도에서 비트라인이 형성될 부위의 상기 층간절연막을 소정깊이 선택적으로 식각하여 홈을 형성하는 단계; 상기 홈의 형성에 의해 잔류되는 층간절연막을 선택식각하여 상기 트랜지스터의 다른 한 접합을 노출시키는 비트라인 콘택홀을 형성하는 단계; 및 상기 홈 및 콘택홀 내부에 비트라인용 전도막을 형성하는 단계를 포함하여 이루어진다.The present invention relates to a method of fabricating a semiconductor device having a plug and a bit line of a planarized charge storage electrode, the method comprising: forming a transistor having a source and a drain junction on a semiconductor substrate and forming an interlayer insulating film thereon; Forming a charge storage electrode contact plug penetrating the interlayer insulating film and contacting any junction of the transistor; Forming a groove by selectively etching the interlayer insulating film in a region where a bit line is to be formed to a predetermined depth unless the transistor is opened; Selectively etching the interlayer insulating film remaining by the formation of the groove to form a bit line contact hole exposing the other junction of the transistor; And forming a conductive film for the bit line in the groove and the contact hole.

Description

반도체 소자의 평탄화를 위한 전도막 형성 방법A method of forming a conductive film for planarization of semiconductor devices

본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 반도체 소자의 평탄화를 이룰수 있는 전도막을 갖는 반도체 소자 제조 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a conductive film capable of flattening the semiconductor device.

잘 알려진 바와 같이, 소자의 고집적화에 따라 적층형의 소자 형성 방법이 성행하고 있으며, 이처럼 적층 되는 소자가 서로 다르기 때문에 부분적으로 서로 다른 단차 특성을 나타내어 후속 공정 진행시 평탄화 공정이 필수적으로 진행되어야 하는 문제점이 대두되고 있는 실정이다.As is well known, a stacked type device forming method is prevalent according to the high integration of devices, and since the stacked devices are different from each other, they have different step characteristics in part, so that the planarization process must be performed in the subsequent process. It is emerging.

도1a 내지 도1d는 종래 기술에 따른 반도체 소자 제조 방법을 나타내는 공정 단면도로서, 전하저장전극의 플러그와 비트라인 형성 방법을 나타내는 공정을 나타낸다.1A to 1D are cross-sectional views illustrating a method of fabricating a semiconductor device according to the related art, and illustrating a process of forming a plug and a bit line of a charge storage electrode.

먼저, 도1a에 도시된 바와 같이, 실리콘 기판(11)위에 게이트산화막(12), 게이트 전극용 폴리 실리콘막(13), 산화막(14)을 차례로 형성한 후, 트랜지스터의 게이트 전극형성용 식각마스크를 사용한, 상기 산화막(14), 폴리 실리콘막(13), 게이트 산화막(12)을 차례로 식각한다. 형성된 게이트 전극의 수직구조 측면에 산화막 스페이서(15)를 형성한다. 여기서 산화막(14)과 산화막 스페이서(15)는 폴리 실리콘막(13)의 식각을 방지하기 위한 식각방지막으로 사용된다. 다음으로 소스 및 드레인 영역(도시되지 않음)을 실리콘 기판(11)에 형성한다. 이어서, 이러한 트랜지스터를 절연시킬수 있는 층간 절연막(16)을 형성하고, 선택식각하여 상기 트랜지스터의 소스(또는 드레인)영역을 노출시킨다. 그리고, 이러한 소스(또는 드레인)영역에 콘택되는 전하저장전극의 플러그(17)를 형성한다.First, as shown in FIG. 1A, a gate oxide film 12, a polysilicon film 13 for a gate electrode 13, and an oxide film 14 are sequentially formed on a silicon substrate 11, and then an etching mask for forming a gate electrode of a transistor is formed. The oxide film 14, the polysilicon film 13, and the gate oxide film 12 are etched sequentially. An oxide film spacer 15 is formed on the side of the vertical structure of the formed gate electrode. Here, the oxide film 14 and the oxide film spacer 15 are used as an etch stop film for preventing etching of the polysilicon film 13. Next, source and drain regions (not shown) are formed in the silicon substrate 11. Next, an interlayer insulating film 16 capable of insulating such a transistor is formed and selectively etched to expose the source (or drain) region of the transistor. Then, the plug 17 of the charge storage electrode that contacts the source (or drain) region is formed.

다음으로, 도1b에 도시된 바와 같이, 전체구조상부에 절연막(18)을 형성한 후, 그 상부에 비트라인 콘택홀을 형성하기 위한 식각마스크 패턴(101)을 형성한다. 그리고, 이러한 식각마스크 패턴(101)을 마스크로 하는 절연막(18), 층간절연막(16)의 식각공정을 진행하여 트랜지스터의 드레인(또는 소스)영역을 노출시킨다.Next, as shown in FIG. 1B, an insulating film 18 is formed on the entire structure, and an etch mask pattern 101 for forming a bit line contact hole is formed thereon. The etching process of the insulating film 18 and the interlayer insulating film 16 using the etching mask pattern 101 as a mask is performed to expose the drain (or source) region of the transistor.

다음으로, 도1c에 도시된 바와 같이, 노출된 드레인(또는 소스)영역에 콘택되는 비트라인용 폴리 실리콘막(19)을 형성하고 계속해서 비트라인용 폴리실리콘막(19) 상부에 절연막(20)을 형성한 후 비트라인의 패터닝을 위한 식각마스크 패턴(102)을 형성한다.Next, as shown in FIG. 1C, a bit line polysilicon film 19 is formed in contact with the exposed drain (or source) region, and then the insulating film 20 over the bit line polysilicon film 19 is formed. ) And then form an etching mask pattern 102 for patterning the bit lines.

다음으로, 도1d에 도시된 바와 같이, 식각마스크 패턴(102)을 사용하여 절연막(20)과 비트라인용 폴리 실리콘막(19)을 식각하여 비트라인을 패터닝 한다. 그리고, 비트라인 산화막 스페이서(21)를 형성한다.Next, as illustrated in FIG. 1D, the bit line is patterned by etching the insulating film 20 and the polysilicon film 19 for the bit line using the etching mask pattern 102. Then, the bit line oxide film spacer 21 is formed.

그러나 전술한 바와 같은 공정으로 형성되는 전하저장전극의 플러그 및 비트라인은 도시된 바와 같이 단차를 유발하여 추후 진행되는 사진 식각공정의 초점심도불량 등의 문제를 야기시킨다. 따라서 이러한 문제를 해결할 수 있는 전하저장전극 플러그 및 비트라인의 형성 방법의 개발이 필요하게 되었다.However, the plug and the bit line of the charge storage electrode formed by the above-described process causes a step as shown in the drawing, causing problems such as poor depth of focus of the subsequent photolithography process. Therefore, it is necessary to develop a method of forming a charge storage electrode plug and a bit line which can solve this problem.

상기와 같은 제반 요구 사항에 의해 안출된 본 발명은, 반도체 소자 제조 방법에 있어서, 전하저장전극 플러그와 비트라인의 형성후에도 평탄화를 유지할 수 있는 반도체 소자 제조 방법을 제공하고자 함을 그 목적으로 한다.The present invention devised by the above-described requirements is to provide a semiconductor device manufacturing method capable of maintaining planarization even after the formation of the charge storage electrode plug and the bit line in the semiconductor device manufacturing method.

도1a 내지 도1d는 종래 기술에 따른 반도체 소자 제조 방법을 나타내는 공정 단면도.1A to 1D are cross-sectional views showing a method of manufacturing a semiconductor device according to the prior art.

도2a 내지 도2f는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 나타내는 공정 단면도.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* 도면의 주요 부분에 대한 부호의 명칭.* Names of symbols for main parts of the drawings.

31 : 실리콘 기판 32 : 게이트 산화막31 silicon substrate 32 gate oxide film

33 : 게이트 전극용 폴리 실리콘막33: polysilicon film for the gate electrode

34 : 산화막 35 : 산화막 스페이서34: oxide film 35: oxide film spacer

36 ; 층간 절연막 37 : 전하 저장 전극 패드36; Interlayer insulating film 37: charge storage electrode pad

38 ; 절연막38; Insulating film

39 : 비트라인용 폴리 실리콘막39: polysilicon film for bit line

40 : 비트라인 상부 절연막40: bit line upper insulating film

상기 목적을 달성하기 위하여 본 발명의 반도체 소자 제조 방법은, 반도체 기판상에 소스 및 드레인 접합을 갖는 트랜지스터를 형성하고 그 상부에 층간절연막을 형성하는 단계; 상기 층간절연막을 관통하여 상기 트랜지스터의 어느한 접합에 콘택되는 전하저장전극 콘택 플러그를 형성하는 단계; 상기 트랜지스터를 오픈시키지 않는 한도에서 비트라인이 형성될 부위의 상기 층간절연막을 소정깊이 선택적으로 식각하여 홈을 형성하는 단계; 상기 홈의 형성에 의해 잔류되는 층간절연막을 선택식각하여 상기 트랜지스터의 다른 한 접합을 노출시키는 비트라인 콘택홀을 형성하는 단계; 및 상기 홈 및 콘택홀 내부에 비트라인용 전도막을 형성하는 단계를 포함하여 이루어진다.In order to achieve the above object, the semiconductor device manufacturing method of the present invention comprises the steps of: forming a transistor having a source and drain junction on a semiconductor substrate and forming an interlayer insulating film thereon; Forming a charge storage electrode contact plug penetrating the interlayer insulating film and contacting any junction of the transistor; Forming a groove by selectively etching the interlayer insulating film in a region where a bit line is to be formed to a predetermined depth unless the transistor is opened; Selectively etching the interlayer insulating film remaining by the formation of the groove to form a bit line contact hole exposing the other junction of the transistor; And forming a conductive film for the bit line in the groove and the contact hole.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도2a 내지 도2f는 본 발명의 일실시예에 따른 반도체 소자 제조 방법을 나타내는 공정 단면도이다.2A through 2F are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

먼저, 도2a에 도시된 바와 같이, 실리콘 기판(31)위에 게이트산화막(32), 게이트 전극용 폴리 실리콘막(33), 산화막(34)을 차례로 형성한 후, 트랜지스터의 게이트 전극형성용 식각마스크를 사용하여, 상기 산화막(34), 폴리 실리콘막(33), 게이트 산화막(32)을 차례로 식각한다. 형성된 게이트 전극의 수직 구조 측면에 산화막 스페이서(35)를 형성한다. 여기서 산화막(34)과 산화막 스페이서(35)는 폴리 실리콘막(33)의 식각을 방지하기 위한 식각방지막으로 사용된다. 다음으로 도면에는 도시되지 않은 소스 및 드레인 영역을 실리콘 기판(31)에 형성한다. 이러한 트랜지스터를 절연시킬수 있는 층간 절연막(36)을 형성하고, 선택식각하여 상기 트랜지스터의 소스(또는 드레인)영역을 노출시킨다. 그리고, 이러한 소스(또는 드레인)영역에 콘택되는 전하저장전극의 플러그(37)를 형성한다.First, as shown in FIG. 2A, a gate oxide film 32, a polysilicon film 33 for a gate electrode 33, and an oxide film 34 are sequentially formed on the silicon substrate 31, and then an etching mask for forming a gate electrode of the transistor is formed. The oxide film 34, the polysilicon film 33, and the gate oxide film 32 are etched sequentially. An oxide film spacer 35 is formed on the side of the vertical structure of the formed gate electrode. Here, the oxide film 34 and the oxide spacer 35 are used as an etch stop layer for preventing etching of the polysilicon layer 33. Next, source and drain regions not shown in the figure are formed in the silicon substrate 31. An interlayer insulating film 36 capable of insulating such a transistor is formed and selectively etched to expose the source (or drain) region of the transistor. Then, the plug 37 of the charge storage electrode that contacts the source (or drain) region is formed.

다음으로, 도2b에 도시된 바와 같이, 비트라인 마스크와 반전된 이미지를 갖는 즉, 비트라인이 형성될 지역이 오픈된 식각마스크 패턴(201)을 형성한다. 그리고, 이러한 식각마스크 패턴(201)을 마스크로하여 층간절연막(36)을 일정깊이 부분식각한다. 여기서 이러한 층간절연막(36)의 부분식각공정은 하부에 형성되어 있는 트랜지스터를 오픈시키기 않는 범위에서 진행하도록 함에 유의하여야 한다. 이러한 부분식각공정에 의하여 비트라인이 패터닝 된다.Next, as shown in FIG. 2B, an etch mask pattern 201 having an inverted image with the bit line mask, that is, an area where the bit line is to be formed is formed. The interlayer insulating layer 36 is partially etched by using the etching mask pattern 201 as a mask. In this case, it should be noted that the partial etching process of the interlayer insulating layer 36 is performed in a range in which the transistor formed underneath is not opened. The bit line is patterned by this partial etching process.

다음으로, 도2c에 도시된 바와 같이, 전체구조 상부에 절연막(38)을 형성한 후 절연막(38) 상부에 포토레지스트(202)를 도포한 후 포토리소그라피 공정을 실시하여 비트라인 콘택홀이 형성될 지역의 절연막(38)을 오픈시키는 포토레지스트 패턴(202)을 형성한다. 그리고, 이러한 포토레지스트 패턴(202)을 사용한 절연막(38), 층간절연막(36)의 식각공정을 실시하여 기 형성된 트랜지스터의 드레인(또는 소스)영역을 노출시킨다.Next, as shown in FIG. 2C, an insulating film 38 is formed over the entire structure, a photoresist 202 is applied over the insulating film 38, and a photolithography process is performed to form a bit line contact hole. A photoresist pattern 202 is formed to open the insulating film 38 in the region to be formed. The etching process of the insulating film 38 and the interlayer insulating film 36 using the photoresist pattern 202 is performed to expose the drain (or source) region of the formed transistor.

다음으로, 도2d에 도시된 바와 같이, 포토레지스트 패턴(202)을 제거한 후 전술한 공정에 의하여 형성된, 층간절연막(36)이 제거된 부분에 비트라인용 폴리 실리콘막(39)을 형성한다. 여기서 비트라인 전도막으로 형성되는 폴리 실리콘막은 폴리 실리콘막 상부에 실리사이드막을 형성하는 폴리사이드 구조로 대체될 수도 있다.Next, as shown in FIG. 2D, the polysilicon film 39 for bit lines is formed on the portion where the interlayer insulating film 36 is removed by the above-described process after removing the photoresist pattern 202. The polysilicon layer formed of the bit line conductive layer may be replaced with a polyside structure forming a silicide layer on the polysilicon layer.

다음으로, 도2e에 도시된 바와 같이, 비트라인용 폴리 실리콘막(39)을 전면식각하여 전하저장전극 플러그 보다 상대적으로 낮게 형성되는 비트라인을 형성한다. 이어서 이러한 비트라인을 절연시키는 절연막(40)을 형성한다.Next, as shown in FIG. 2E, the bit line polysilicon layer 39 is etched to form a bit line that is formed lower than the charge storage electrode plug. An insulating film 40 is then formed to insulate these bit lines.

마지막으로, 도2f에 도시된 바와 같이, 절연막(40)을 전면식각하여 평탄화를 이룬다. 도면에 도시된 바와 같이, 비트라인과 전하저장전극 콘택 플러그 사이에서 표면단차는 발생되지 않으며, 이에 의해 후속 공정 마진이 증대될 것이다.Finally, as shown in FIG. 2F, the insulating film 40 is etched entirely to planarize it. As shown in the figure, no surface step is generated between the bit line and the charge storage electrode contact plug, thereby increasing the subsequent process margin.

이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능함이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

상기와 같이 이루어지는 본 발명은, 전하저장전극의 플러그와 비트라인을 갖는 반도체 소자의 제조시, 전하저장전극 플러그의 형성후에 층간절연막을 부분식각하고 이 부분식각된 부위에 패터닝 되는 비트라인을 형성함으로써, 종래의 단차문제를 충분히 극복하여 소자의 수율 및 신뢰성을 향상시킨다.According to the present invention as described above, in the manufacture of a semiconductor device having a plug and a bit line of a charge storage electrode, after forming the charge storage electrode plug, by partially etching the interlayer insulating film and forming a bit line patterned on the partially etched portion In order to sufficiently overcome the conventional step problem, the yield and reliability of the device are improved.

Claims (4)

반도체 기판상에 소스 및 드레인 접합을 갖는 트랜지스터를 형성하고 그 상부에 층간절연막을 형성하는 단계;Forming a transistor having a source and a drain junction on the semiconductor substrate and forming an interlayer insulating film thereon; 상기 층간절연막을 관통하여 상기 트랜지스터의 어느한 접합에 콘택되는 전하저장전극 콘택 플러그를 형성하는 단계;Forming a charge storage electrode contact plug penetrating the interlayer insulating film and contacting any junction of the transistor; 상기 트랜지스터를 오픈시키지 않는 한도에서 비트라인이 형성될 부위의 상기 층간절연막을 소정깊이 선택적으로 식각하여 홈을 형성하는 단계;Forming a groove by selectively etching the interlayer insulating film in a region where a bit line is to be formed to a predetermined depth unless the transistor is opened; 상기 홈의 형성에 의해 잔류되는 층간절연막을 선택식각하여 상기 트랜지스터의 다른 한 접합을 노출시키는 비트라인 콘택홀을 형성하는 단계; 및Selectively etching the interlayer insulating film remaining by the formation of the groove to form a bit line contact hole exposing the other junction of the transistor; And 상기 홈 및 콘택홀 내부에 비트라인용 전도막을 형성하는 단계Forming a conductive film for the bit line in the groove and the contact hole 를 포함하여 이루어지는 반도체 소자 제조 방법.A semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 전하저장전극 콘택 플러그의 표면을 덮는 절연막을 형성한 후 상기 비트라인용 전도막을 형성하는 반도체 소자 제조 방법.And forming an insulating film covering the surface of the charge storage electrode contact plug and then forming the bit line conductive film. 제1항에 있어서,The method of claim 1, 상기 비트라인용 전도막 형성후 평탄화 절연막을 형성하는 단계를 더 포함하는 반도체 소자 제조 방법.And forming a planarization insulating film after forming the bit line conductive film. 제1항에 있어서,The method of claim 1, 상기 비트라인용 전도막을 형성하는 단계는,Forming the conductive film for the bit line, 상기 비트라인 콘택홀이 형성된 기판상에 상기 비트라인용 전도막을 증착하는 단계;Depositing a conductive film for the bit line on the substrate on which the bit line contact hole is formed; 상기 층간절연막 표면이 노출되도록 상기 전도막을 화학적 기계적 연마하는 단계; 및Chemical mechanical polishing the conductive film to expose the surface of the interlayer insulating film; And 상기 전도막을 전면식각하는 단계Etching the entire conductive film 를 포함하여 이루어지는 반도체 소자 제조 방법.A semiconductor device manufacturing method comprising a.
KR1019970078012A 1997-12-30 1997-12-30 A method of forming a conductive film for planarization of semiconductor devices KR19990057933A (en)

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