KR19990055165A - Device isolation film formation method using trench - Google Patents
Device isolation film formation method using trench Download PDFInfo
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- KR19990055165A KR19990055165A KR1019970075077A KR19970075077A KR19990055165A KR 19990055165 A KR19990055165 A KR 19990055165A KR 1019970075077 A KR1019970075077 A KR 1019970075077A KR 19970075077 A KR19970075077 A KR 19970075077A KR 19990055165 A KR19990055165 A KR 19990055165A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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Abstract
본 발명은 보이드의 발생을 방지하여 소자의 특성을 향상시킬 수 있는 트렌치(trench)를 이용한 소자분리막 형성 방법을 제공하고자 하는 것으로, 이를 위해 본 발명은, 실리콘 기판 상에 산화막 및 질화막 패턴을 형성하여 실리콘 기판을 노출하고 선택적으로 제거하여 트렌치를 형성한 후, 식각 결함을 제거하기 위하여 고온에서 트렌치 표면을 산화시켜 희생산화막을 형성한 후, 고온 화학기상증착 방법으로 유동성이 좋은 산화막을 얇게 증착하여 트렌치 표면의 희생산화막을 제거하는 식각과정에서 실리콘 기판 및 질화막 사이의 산화막이 일부 제거되어 발생된 보이드를 제거하고 고밀도 플라즈마 화학기상증착법으로 산화막을 형성하여 트렌치를 매립한다.The present invention is to provide a device isolation film forming method using a trench (trench) that can prevent the generation of voids to improve the characteristics of the device, for this purpose, by forming an oxide film and a nitride film pattern on a silicon substrate After forming the trench by exposing and selectively removing the silicon substrate, to form a sacrificial oxide film by oxidizing the trench surface at a high temperature in order to remove the etching defects, and by depositing a thin layer of a good fluidity oxide film by high temperature chemical vapor deposition method In the etching process of removing the sacrificial oxide film on the surface, a portion of the oxide film between the silicon substrate and the nitride film is removed to remove voids, and an oxide film is formed by high-density plasma chemical vapor deposition to fill the trench.
Description
본 발명은 반도체 장치 제조 방법에 관한 것으로, 특히 트렌치(trench)를 이용한 소자분리막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a device isolation film using a trench.
통상적인 트렌치를 이용한 소자분리막 형성 공정에서는, 실리콘 기판 내에 트렌치를 형성하는 건식식각 과정에서 발생하는 식각 결함을 제거하기 위하여, 희생산화막을 형성한 후 건식 또는 습식식각을 실시하는데, 이때 실리콘 기판과 질화막 사이에 형성된 산화막의 일부가 제거되어 보이드(void)가 발생한다. 이후에 고밀도 플라즈마 화학기상증착 방법으로 산화막을 형성하여 트렌치를 매립할 경우 고밀도 플라즈마 화학기상증착법의 특성상 산화막 형성 가스가 직진성이 강하기 때문에 보이드는 산화막으로 채워지지 않은 채 남게되어 문제점을 유발하게 된다.In a conventional isolation layer forming process using a trench, in order to remove an etching defect generated during the dry etching process of forming a trench in a silicon substrate, a sacrificial oxide film is formed and then dry or wet etching is performed. A portion of the oxide film formed therebetween is removed to cause voids. Subsequently, when the oxide film is formed by filling the trench with the high density plasma chemical vapor deposition method, the voids remain unfilled with the oxide film due to the strong straightness of the oxide forming gas due to the characteristics of the high density plasma chemical vapor deposition method, causing problems.
도1a 내지 도1e는 종래 기술에 따른 트렌치를 이용한 소자분리막 형성 공정 단면도이다. 종래 기술에 따른 트렌치를 이용한 소자분리막 형성 방법은 다음과 같이 이루어진다.1A to 1E are cross-sectional views of a device isolation film forming process using trenches according to the prior art. A device isolation film forming method using a trench according to the prior art is as follows.
먼저, 도1a에 도시한 바와 같이 실리콘 기판(10) 상에 산화막(11) 및 질화막(12)을 형성하고, 산화막(11) 및 질화막(12)을 선택적으로 식각하여 소자분리 영역의 실리콘 기판(10) 표면을 노출한다. 이어서, 노출된 실리콘 기판을 소정 깊이까지 식각하여 트렌치(13)를 형성하고, 트렌치를 형성하기 위한 식각 과정에서 발생하는 식각 결함을 제거하기 위하여 고온에서 트렌치 표면에 희생산화막(도시하지 않음)을 형성하고 습식 또는 건식식각을 실시하여 희생산화막을 제거한다. 이때, 실리콘 기판과 질화막 사이에 형성된 산화막의 일부가 제거되게 된다. 이어서, 희생산화막이 제거되어 트렌치 내부에 노출된 실리콘 표면에 바로 고밀도 플라즈마 화학기상증착법으로 산화막을 형성할 경우 발생하는 계면포획전하(interface trap charge)의 발생을 방지하기 위하여 열산화공정을 실시하여 산화막(14)을 형성한다.First, as shown in FIG. 1A, the oxide film 11 and the nitride film 12 are formed on the silicon substrate 10, and the oxide film 11 and the nitride film 12 are selectively etched to form a silicon substrate in the device isolation region ( 10) Expose surface. Subsequently, the exposed silicon substrate is etched to a predetermined depth to form the trench 13, and a sacrificial oxide film (not shown) is formed on the trench surface at a high temperature to remove the etching defects generated during the etching process for forming the trench. The sacrificial oxide film is removed by performing wet or dry etching. At this time, a part of the oxide film formed between the silicon substrate and the nitride film is removed. Subsequently, the oxide film is thermally oxidized to prevent the occurrence of interface trap charge, which is generated when the oxide film is formed on the silicon surface exposed in the trench by high density plasma chemical vapor deposition. (14) is formed.
이어서, 도1b에 도시한 바와 같이 고밀도 화학기상증착법으로 산화막(15)을 형성하여 트렌치(14)를 매립한다. 이때, 고밀도 화학기상증착법으로 트렌치를 매립할 경우 고밀도 플라즈마 화학기상증착방법의 특성상 산화막 형성 가스가 직진하여, 실리콘 기판과 질화막 사이의 산화막이 식각되어 형성된 보이드(a)가 채워지지 않은 채 있게된다.Next, as shown in FIG. 1B, the oxide film 15 is formed by high density chemical vapor deposition to fill the trench 14. At this time, when the trench is filled by the high density chemical vapor deposition method, the oxide film forming gas is straight due to the characteristics of the high density plasma chemical vapor deposition method, so that the void (a) formed by etching the oxide film between the silicon substrate and the nitride film is not filled.
도1c 및 도1d는 각각 상기와 같이 이루어지는 종래 기술에 따라 형성된 트렌치를 이용한 소자분리막의 단면을 보이는 SEM 사진 및 개략도이다. 도1d는 도1c의 'A' 부분을 개략적으로 도시한 것으로 실리콘 기판(10)에 트렌치 형성 후 고밀도 플라즈마 화학기상증착법으로 산화막(15)을 트렌치에 매립한 상태에서 보이드가 남아있음을 보이고 있다.1C and 1D are SEM photographs and schematic diagrams showing cross-sections of device isolation films using trenches formed according to the prior art, respectively, as described above. FIG. 1D schematically illustrates a portion 'A' of FIG. 1C, and shows that voids remain in the state where the oxide film 15 is embedded in the trench by high-density plasma chemical vapor deposition (CVD) after the trench is formed in the silicon substrate 10.
다음으로, 도1e에 도시한 바와 같이 상기 고밀도 화학기상증착법으로 형성된 산화막(15), 질화막(12) 및 산화막(11)을 전면식각하여 고밀도 플라즈마 화학기상증착법으로 형성된 산화막(15)이 트렌치 내에만 남도록 한다. 이때, 보이드로 인하여 트렌치 입구에 해자(moat) (b)가 형성되는데, 이후 폴리실리콘막을 형성하고 식각하는 과정에서 해자 부분에 폴리실리콘이 남게되어 소자의 단락이 유발되고, 또한, 해자의 발생으로 드러나는, 트렌치를 이루는 실리콘 기판 모서리 부분에 전기장이 집중됨으로 인하여 소자의 전기적 특성 열화를 초래한다.Next, as shown in FIG. 1E, the oxide film 15 formed by the high density chemical vapor deposition method, the nitride film 12, and the oxide film 11 are etched all over, so that the oxide film 15 formed by the high density plasma chemical vapor deposition method is in the trench only. To remain. At this time, a moat (b) is formed at the inlet of the trench due to the void, and then, in the process of forming and etching the polysilicon film, polysilicon remains in the moat, causing short circuiting of the device, and also by generating the moat. The electrical field is concentrated at the edges of the silicon substrate forming the trench, which causes deterioration of the electrical characteristics of the device.
상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은 보이드의 발생을 방지하여 소자의 특성을 향상시킬 수 있는 트렌치를 이용한 소자분리막 형성 방법을 제공하는데 그 목적이 있다.The present invention devised to solve the above problems is to provide a device isolation film forming method using a trench that can improve the characteristics of the device by preventing the generation of voids.
도1a 내지 도1e는 종래 기술에 따른 트렌치를 이용한 소자분리막 형성 공정 단면도.1A to 1E are cross-sectional views of a device isolation film forming process using trenches according to the prior art.
도2a 내지 도2h는 본 발명의 일실시예에 따른 트렌치를 이용한 소자분리막 형성 공정 단면도.Figure 2a to Figure 2h is a cross-sectional view of the device isolation film forming process using a trench in accordance with an embodiment of the present invention.
* 도면의 주요 부분에 대한 설명* Description of the main parts of the drawing
20: 실리콘 기판 21, 24, 25: 산화막20: silicon substrate 21, 24, 25: oxide film
22: 질화막 23: 트렌치22: nitride film 23: trench
26: 고밀도 화학기상증착법으로 형성된 산화막26: oxide film formed by high density chemical vapor deposition
상기 목적을 달성하기 위한 본 발명은 트렌치를 이용한 소자분리막 형성 방법에 있어서, 반도체 기판 상에 제1 산화막 및 질화막을 형성하는 단계; 상기 제1 산화막 및 질화막을 선택적으로 제거하여 소자분리영역의 반도체 기판 표면을 노출하는 패턴을 형성하는 단계; 상기 노출된 반도체 기판을 선택적으로 제거하여 상기 반도체 기판 내부에 트렌치를 형성하는 단계; 열공정을 실시하여 상기 트렌치 표면에 제2 산화막을 형성하고 제2 산화막을 식각하여 상기 트렌치 형성 과정에서 생성된 식각결함을 제거하는 단계; 화학기상증착법으로 반도체 기판 전면에 제3 산화막을 형성하는 단계; 고밀도 플라즈마 화학기상증착법으로 전체 구조를 덮는 제4 산화막을 형성하는 단계; 및 상기 반도체 기판이 노출되도록 전면식각하여 상기 제4 산화막이 상기 트렌치 내부에 남도록 하는 단계를 포함하여 이루어진다.In order to achieve the above object, the present invention provides a device isolation film forming method using a trench, comprising: forming a first oxide film and a nitride film on a semiconductor substrate; Selectively removing the first oxide film and the nitride film to form a pattern exposing a surface of a semiconductor substrate in an isolation region; Selectively removing the exposed semiconductor substrate to form a trench in the semiconductor substrate; Performing a thermal process to form a second oxide film on the surface of the trench and etching the second oxide film to remove the etching defects generated during the trench formation; Forming a third oxide film on the entire surface of the semiconductor substrate by chemical vapor deposition; Forming a fourth oxide film covering the entire structure by high density plasma chemical vapor deposition (CCVD); And etching the entire surface of the semiconductor substrate so that the fourth oxide layer remains inside the trench.
본 발명에 따른 트렌치를 이용한 소자분리막 형성 방법은, 실리콘 기판 상에 산화막 및 질화막 패턴을 형성하여 실리콘 기판을 노출하고 선택적으로 제거하여 트렌치를 형성한 후, 식각 결함을 제거하기 위하여 고온에서 트렌치 표면을 산화시켜 희생산화막을 형성한 후, 고온 화학기상증착 방법으로 유동성이 좋은 산화막을 얇게 증착하여, 트렌치 표면의 희생산화막을 제거하는 식각과정에서 실리콘 기판 및 질화막 사이의 산화막이 일부 제거되어 발생된 보이드를 제거하고 고밀도 플라즈마 화학기상증착법으로 산화막을 형성하여 트렌치를 매립한다.In the method of forming an isolation layer using a trench according to the present invention, an oxide film and a nitride film pattern are formed on a silicon substrate to form a trench by exposing and selectively removing the silicon substrate, and then forming a trench surface at a high temperature to remove an etching defect. After oxidization to form a sacrificial oxide film, a thin fluid oxide film is deposited by a high temperature chemical vapor deposition method to remove voids formed by partially removing an oxide film between the silicon substrate and the nitride film during the etching process of removing the sacrificial oxide film on the trench surface. The trench is removed and an oxide film is formed by a high density plasma chemical vapor deposition method.
첨부된 도면 도2a 내지 도2h는 본 발명의 일실시예에 따른 트렌치를 이용한 소자분리막 형성 공정 단면도이다. 이하 도2a 내지 도2h를 참조하여 본 발명의 일실예에 따른 트렌치를 이용한 소자분리막 형성 방법을 설명한다.2A through 2H are cross-sectional views of a device isolation layer forming process using trenches according to an embodiment of the present invention. Hereinafter, a method of forming a device isolation layer using trenches according to an embodiment of the present invention will be described with reference to FIGS. 2A to 2H.
먼저, 도2a에 도시한 바와 같이 열공정을 실시하여 습식 또는 건식 방법으로 실리콘기판(20) 상에 50 Å 내지 200 Å 두께의 산화막(21)을 형성하고, 산화막(21) 상에 1000 Å 내지 3000 Å 두께의 질화막(22)을 형성한다.First, as shown in FIG. 2A, a thermal process is performed to form an oxide film 21 having a thickness of 50 GPa to 200 GPa on a silicon substrate 20 by a wet or dry method, and from 1000 GPa to an oxide film 21. A nitride film 22 having a thickness of 3000 mm 3 is formed.
다음으로, 도2b에 도시한 바와 같이 질화막(22) 및 산화막(21)을 선택적으로 제거하여 소자분리영역의 실리콘 기판(20)을 노출하는 질화막(22) 및 산화막(21) 패턴을 형성한다. 이어서, 노출된 실리콘 기판(20)을 1500 Å 내지 4000 Å 깊이만큼 선택적으로 건식식각하여 실리콘 기판(20) 내에 트렌치(23)를 형성한다.Next, as shown in FIG. 2B, the nitride film 22 and the oxide film 21 are selectively removed to form a pattern of the nitride film 22 and the oxide film 21 exposing the silicon substrate 20 in the device isolation region. Subsequently, the exposed silicon substrate 20 is selectively dry etched to a depth of 1500 kPa to 4000 kPa to form the trench 23 in the silicon substrate 20.
다음으로, 도2c에 도시한 바와 같이 상기 트렌치(23) 형성을 위한 건식식각 과정에서 실리콘 기판(20) 표면에 발생하는 식각 결함을 제거하기 위하여, 열공정을 실시하여 트렌치(23) 표면에 50 Å 내지 200 Å 두께의 희생산화막(도시하지 않음)을 형성하고 습식식각을 실시한다. 이때의 희생산화막을 제거하기 위한 습식식각 과정에서 질화막(22) 및 산화막(21) 패턴 형성으로 측벽이 노출된 산화막(21)이 일부 제거되어 트렌치(23)와 질화막(22) 사이에 보이드(c)가 발생한다.Next, as shown in FIG. 2C, in order to remove the etching defects occurring on the surface of the silicon substrate 20 in the dry etching process for forming the trench 23, a thermal process is performed on the surface of the trench 23. A sacrificial oxide film (not shown) having a thickness of 200 kV to 200 kV is formed and wet etching is performed. In the wet etching process for removing the sacrificial oxide film at this time, the oxide film 21 having the sidewalls exposed by the pattern of the nitride film 22 and the oxide film 21 is partially removed, thereby voiding between the trench 23 and the nitride film 22. ) Occurs.
다음으로, 도2d에 도시한 바와 같이 희생산화막을 제거함으로써 실리콘층이 드러난 트렌치(23) 표면에, 이후에 화학기상증착법으로 산화막을 바로 형성될 경우 일어나는 계면포획전하의 발생을 방지하기 위하여, 건식 또는 습식 방법으로 열공정을 실시하여 산화막(24)을 형성한다. 이어서, 화학기상증착법으로 유동성있는 산화막(25)을 기판 전면에 형성하여 보이드를 제거한다. 이때, 유동성 있는 산화막(25)을 형성하기 위하여 600 ℃ 이상의 온도 조건에서 화학기상증착법으로 산화막을 형성한다. 또한, 고온 화학기상증착법으로 형성되는 산화막(25)을 그 두께가 200 Å이 넘지 않도록 한다.Next, as shown in FIG. 2D, dry etching is performed to prevent the occurrence of interfacial trapping charges that occur when the oxide film is directly formed by chemical vapor deposition on the surface of the trench 23 where the silicon layer is exposed by removing the sacrificial oxide film. Alternatively, a thermal process is performed by a wet method to form the oxide film 24. Subsequently, a fluidized oxide film 25 is formed on the entire substrate by chemical vapor deposition to remove voids. At this time, in order to form a flowable oxide film 25, an oxide film is formed by chemical vapor deposition at a temperature of 600 ° C. or higher. In addition, the thickness of the oxide film 25 formed by the high temperature chemical vapor deposition method does not exceed 200 kPa.
다음으로, 도2e에 도시한 바와 같이 고밀도 플라즈마 화학기상증착법으로 3000 Å 내지 8000 Å 두께의 산화막(26)을 형성하여 트렌치를 매립한다.Next, as shown in FIG. 2E, an oxide film 26 having a thickness of 3000 Pa to 8000 Pa is formed by high density plasma chemical vapor deposition to fill the trench.
도2f 및 도2g는 각각 상기와 같이 이루어지는 본 발명에 따라 형성된 트렌치를 이용한 소자분리막의 단면을 보이는 SEM 사진 및 개략도이다. 도2g는 도2f의 'B' 부분을 개략적으로 도시한 것으로, 실리콘 기판(20)에 트렌치 형성 후 고밀도 플라즈마 화학기상증착법으로 산화막(26)을 트렌치에 매립한 상태에서 보이드가 제거되었음을 보이고 있다.2F and 2G are SEM photographs and schematic diagrams showing a cross section of an isolation layer using trenches formed according to the present invention made as described above, respectively. FIG. 2G schematically illustrates a portion 'B' of FIG. 2F, and shows that voids are removed in a state in which the oxide layer 26 is embedded in the trench by high density plasma chemical vapor deposition after trench formation in the silicon substrate 20.
다음으로, 도2h에 도시한 바와 같이 상기 고밀도 플라즈마 화학기상증착법으로 형성된 산화막(26), 고온 화학기상증착법으로 형성된 산화막(25), 질화막(22) 및 산화막(21)을 전면식각하여 고밀도 플라즈마 화학기상증착법으로 형성된 산화막(26)이 트렌치 내에만 남도록 한다. 이때, 고온 화학기상증착법으로 형성된 산화막(25)은 고밀도 화학기상증착법으로 형성된 산화막(26)과 습식식각비가 거의 같기 때문에 트렌치 입구에 해자가 발생하지 않는다.Next, as shown in FIG. 2H, the oxide film 26 formed by the high-density plasma chemical vapor deposition method, the oxide film 25, the nitride film 22, and the oxide film 21 formed by the high temperature chemical vapor deposition method are etched to the high-density plasma chemistry. The oxide film 26 formed by the vapor deposition method is left in the trench only. At this time, since the wet etching ratio is almost the same as that of the oxide film 25 formed by the high temperature chemical vapor deposition method, the moat does not occur in the trench inlet.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the technical field of the present invention without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.
상기와 같이 이루어지는 본 발명은 트렌치 형성 공정에서 발생하는 보이드를 고온 화학기상증착법으로 유동성 있는 산화막을 형성하여 제거한 후, 고밀도 플라즈마 화학기상증착법으로 산화막을 형성하여 트렌치를 매립함으로써 트렌치 입구에 해자의 발생을 방지하여 이후의 공정에서 폴리실리콘막이 잔류하는 것을 방지하고, 실리콘 기판 모서리가 노출되어 전기장이 집중되는 것을 방지함으로써 소자의 전기적 특성을 향상시킬 수 있다. 또한, 고온 화학기상증착법으로 형성된 산화막은 고밀도 플라즈마 화학기상증착법으로 산화막을 증착하는 과정에서 산화 가스에 의한 물리적 충돌로 표면에 결함이 발생하는 것을 방지하기도 한다.According to the present invention as described above, the voids generated in the trench forming process are removed by forming a fluidized oxide film by a high temperature chemical vapor deposition method, and then an oxide film is formed by a high density plasma chemical vapor deposition method to fill the trench to form a moat at the inlet of the trench. By preventing the polysilicon film from remaining in a subsequent process, and preventing the concentration of the electric field by exposing the edge of the silicon substrate, the electrical characteristics of the device may be improved. In addition, the oxide film formed by the high temperature chemical vapor deposition method may prevent the occurrence of defects on the surface due to physical collisions by the oxidizing gas during the deposition of the oxide film by the high density plasma chemical vapor deposition method.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400301B1 (en) * | 1999-12-30 | 2003-10-01 | 주식회사 하이닉스반도체 | A method for forming a field oxide of semiconductor device |
| KR100419754B1 (en) * | 1999-12-31 | 2004-02-21 | 주식회사 하이닉스반도체 | A method for forming a field oxide of a semiconductor device |
| KR100429678B1 (en) * | 1999-12-30 | 2004-05-03 | 주식회사 하이닉스반도체 | A method for forming a field oxide of semiconductor device |
| KR100967669B1 (en) * | 2003-04-25 | 2010-07-07 | 주식회사 하이닉스반도체 | Method for forming STI of semiconductor device |
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1997
- 1997-12-27 KR KR1019970075077A patent/KR100257759B1/en not_active IP Right Cessation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400301B1 (en) * | 1999-12-30 | 2003-10-01 | 주식회사 하이닉스반도체 | A method for forming a field oxide of semiconductor device |
| KR100429678B1 (en) * | 1999-12-30 | 2004-05-03 | 주식회사 하이닉스반도체 | A method for forming a field oxide of semiconductor device |
| KR100419754B1 (en) * | 1999-12-31 | 2004-02-21 | 주식회사 하이닉스반도체 | A method for forming a field oxide of a semiconductor device |
| KR100967669B1 (en) * | 2003-04-25 | 2010-07-07 | 주식회사 하이닉스반도체 | Method for forming STI of semiconductor device |
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