KR19990052188A - Package structure and manufacturing method of a semiconductor device having a slot - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for packaging and manufacturing a semiconductor device (integrated circuit IC or die of a single element), wherein a plurality of dies are attached to a predetermined substrate in one substrate, and the substrate is vertically slotted. The present invention relates to a method and a manufacturing method that can dramatically increase the number of dies (mounting density) per unit area occupied by the entire package underside by inserting it in a package. The present invention is a useful invention that can increase the mounting density, and ultimately to implement a three-dimensional multichip module by arranging several substrates vertically in a single package.

Description

Package structure and manufacturing method of a semiconductor device having a slot

An object of the present invention is to mount a plurality of die on one substrate, and then to mount them in a slot form in a package to increase the mounting density, the portion corresponding to the back born to adopt a multi-chip module substrate or multi-chip substrate Ultimately, a three-dimensional multichip module is realized. Therefore, the cross talk can be reduced compared to the multi-chip module integrated on the plane, the mounting density can be increased compared to the multi-chip module on the general plane, and the slot type is for easy rework.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for packaging a semiconductor device (integrated circuit IC or die of a single element) and a method of packaging the same, wherein a plurality of dies are attached to a predetermined substrate in one substrate, and the substrate is vertically slotted. The present invention relates to a method and a manufacturing method which can dramatically increase the number of dies (mounting density) per unit area of the bottom surface of a package by inserting it into an external package.

In general, the actual semiconductor device is limited to one or two in terms of the area of the packaged semiconductor device occupied when the packaged semiconductor device IC is used on a system level board. Therefore, in the case of a complex system requiring a large number of ICs, the system board becomes inevitably large, and thus the entire system becomes large, which makes installation and maintenance difficult.

As a solution to this problem, a multi-chip module may be considered, but there is an advantage of increasing performance or mounting density, but it requires a lot of effort and cost to manufacture a board of a multi-chip module. In addition, even in the case of a multi-chip module, since the die is placed in a planar two-dimensional space, the mounting density is not very high.

As described above, the related art is a field for packaging a semiconductor integrated circuit device, and the related art has a disadvantage in that the mounting density can not be dramatically increased because the die is packaged or a plurality of chips are formed on a flat surface. have.

The present invention can increase the mounting density by vertically arranging a plurality of substrates in a single package, and ultimately, by implementing a three-dimensional multichip module, the mounting density can be increased, and the package can be expanded not only as a simple package but also as a small system array. And a method of packaging thereof.

1 is a plan view and a side view of a semiconductor device 1 having eight bonding pads 2;

2A is a plan view and a side view of a chip carrier substrate 4 having sixteen wire bonding pads 3 on the top surface thereof;

FIG. 2B is a plan view and a side view of the chip carrier substrate 6 having sixteen solder bumps 5 for flip chip bonding on the top surface thereof;

3 is a plan view and a side view of a state in which the semiconductor device 1 is die-bonded to the substrate 4;

4A is a plan view and a side view of the wire bonded 11 of the semiconductor device 1 die-bonded to the substrate 4;

4B is a plan view and a side view of a semiconductor device 1 in which flip chip bonding is performed on a substrate 6;

5A is a plan view and a side view of a substrate 13 having a via hole 14 as a substrate corresponding to a base surface of an entire package and having a pattern 15 formed thereon so that the lead 25 can be attached thereto.

5B is a plan view and a side view of a small substrate forming a package slot and being a pattern for connection of a signal pattern;

6 is a plan view and a side view of the base substrate 13 to which the leads 25 are attached;

7 is a plan view and a side view of a package base plate assembled with the base substrate 13 and the slot substrate 16;

8 is a plan view and a side view of a metal package case, i.e., a package completed by attaching the housing 23;

9 is a plan view and a side view of a state in which the boards 4 and 6 are inserted into the slots;

10 is a plan view and a side view of a state in which the lid 26 is covered after the assembly is completed.

* Explanation of symbols for main parts of the drawings

1 semiconductor device 2 bonding pad

3: wire bonding pad of substrate 4: chip carrier substrate for wire bonding

5: solder bump for flip chip bonding of substrate

6: chip carrier substrate for flip chip bonding

7: die-bonding pad 8: metal pattern of substrate 4,6

9: metal pattern in contact with the slot 17

10: die bonding material 11: bonding wire

12: flip chip bonded flip chip bump 13: base substrate

14: via hole 15: metal pattern connected to the lead 25

16: small substrate 17: slot pattern

18: top wiring

19: Via hole for connecting to the substrate and the pattern on the back of the small substrate

20: Pattern of the back side connecting the via holes of the small substrate

21: pattern of the back of the small substrate to be connected to the base substrate (13)

22: Via hole penetrating through the base substrate 13 and the small substrate 16.

23: Metal package case or housing mounted on the package base plate

24: guide 25: external lead

26: package lid

In order to achieve the above object, the present invention basically manufactures a metal-cut housing 23 by processing a Kovar alloy, a Cu-W alloy, a low carbon steel alloy, and the like, which are commonly used in a general semiconductor packaging process, and a base substrate 13 ), The small substrate 16, and the chip carrier substrates 4 and 6 are manufactured by coating the slot pattern 17 and the metal patterns 15, 18, 20, and 21 with a thick film or a thin film on the alumina substrate. 19 and 14 are pre-drilled with a laser perforator. The process of joining the base substrate 13 and the small substrate 16 is performed by using a nonconductive epoxy. The lead 25 used for connection to the outside is bonded to the base substrate 13 by brazing process using Kovar alloy. In addition, the method of attaching the chip carrier substrates 4 and 6 to the slots is bonded using silver-containing epoxy or solder. The lid 26 is joined by a seam sealing method or a method of melt attaching a solder preform in an inert atmosphere.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a first process for manufacturing chip carrier substrates 4 and 6 on which semiconductor device 1 can be placed. Specifically, when alumina or heat transfer is important, a pattern such as a thin film or a thick film is coated on a substrate such as 0.635 or 0.381 mm in thickness of aluminum nitride so that the wire carrier chip carrier substrate 4 can be wire-bonded well. The thickness should be over 2㎛.

In the case of the chip carrier substrate 6 for flip chip, a pattern is formed of a gold thin film or a thick film, and then 50w / t% Pb-50w / t% In, 95% w / t Pb-5w by thermal evaporation or electroplating. Flip chip solder bumps are deposited or plated with one of the following compositions: / t% Sn, 80w / t% Au-20w / t% Sn, and heated at about 300 ° C. to reflow the bumps into a round shape. The 37% w / t Pb-63% w / t Sn series, which is the most popular solder, is not used because Sn reacts with Au of metal pattern and degrades mechanical strength after flip chip bonding.

The second step is a step of die bonding the semiconductor device 1 to the chip carrier substrate 4 for wire bonding.

This is because the semiconductor device 1 must be attached to the substrate 4 in order to wire bond. When the flip chip bonding process is applied, the die bonding process is omitted. The die-bonding material 10 is attached at about 310 ° C. in the case of using a 1 mil solder preform having a thickness of 80% Au-20% Sn, and after using an epoxy containing silver, Allow to cure at about 150 ° C. for about one hour. Since the semiconductor device 1 can be attached to both sides of the board | substrate 4, it die-bonds using a special jig | tool of a U-shape.

The third process (FIG. 4) shows a wire bonding process (FIG. 4B) or a flip chip bonding process (FIG. 4B) for electrical connection between the semiconductor device 1 and the substrates 4 and 6. FIG.

Since wire bonding may use a general wire bonder, the bonding pad 2 of the semiconductor device 1 and the bonding pad 3 of the substrate 4 are connected. At this time, since the semiconductor device is attached to both sides of the substrate, when the substrate 4 is mounted on the wire bonder, it is designed in a U-shape and is carried out using a special jig having a center. Flip chip bonding aligns and attaches a semiconductor device using a common flip chip bonder. At this time, the process temperature is carried out at about 350 ℃.

The fifth step is a step of manufacturing the base substrate 13 (FIG. 5A).

If the alumina of 0.635 or 0.381mm thickness or heat transfer is a problem, it is made of thin film or thick film using aluminum nitride. A pattern 15 is formed on the bottom surface of the substrate 13 to attach the signal 25 and the lead 25 so that the lead 25 is attached to the pattern. This pattern is also connected to the signal pattern of the small substrate 16 through which the slot to be placed on the upper part is made via the via hole 14.

In the sixth step (FIG. 5B), the chip carrier substrates 4 and 6 form a slot for flowering, and a small substrate 16 having a pattern for signal wiring is produced.

Since it is attached to the base substrate 13, the coefficients of thermal expansion should be the same, so that they are made of the same material and have a thickness of about 0.635 mm. In FIG. 5B, since the four chip carrier substrates 4 and 6 are mounted, the five small substrates 16 are manufactured.

Also, three types of wiring patterns are formed on the small substrate 16 for the signal wiring, the top wiring 18, the bottom wiring 20 through the via hole 19, and the bottom wiring 21 for connecting with the lead 25. need. This wiring pattern is not shown in detail because it depends on the semiconductor device 1 to be applied and the function to be implemented. In addition, the signal wiring connected from the chip carrier substrates 4 and 6 starts from the slot pattern 17 and is connected to the outside through the signal wirings 18, 20 and 21 and the via holes 19 of the small substrate 16. to be.

In the seventh step (FIG. 6), the lead 25 is attached, and the lead 25 made in advance is attached to the base substrate 13 using the brazing process.

The eighth step (FIG. 7) is a step of assembling the part corresponding to the bottom plate of the package and attaching the base substrate 13 and the small substrate 16 forming the slot.

A silver-free epoxy is used to adhere to each other and to cure at 150 ° C. for about 1 hr. Via holes 22 through which the base substrate 13 and the small substrate 16 penetrate are electrically connected to each other and pre-filled with solder or silver-containing epoxy to ensure the sealability of the package.

The ninth process (FIG. 8) is a process of attaching the manufactured package housing 23 to the package base plate.

First, the package housing is manufactured by processing Kovar alloy, Cu-W alloy or low-carbon steel alloy, and the like. The chip housing substrates 4 and 6 are processed in a U-shape to form a slot for flower slots. Make 24). The package housing 23 is attached and secured using silver containing epoxy. So far, the entire package has been completed.

The tenth step (Fig. 9) is a step in which the chip carrier substrates 4 and 6, on which the semiconductor devices 1 are placed, are mounted in the slots.

At this time, the electrical connection between the slot pattern 17 and the slot pattern 9 of the chip carrier substrate is melt-fixed by infrared or hot air blow method using solder paste.

The eleventh step (Fig. 10) is a step of covering the lid 26 after the assembly is completed.

Fix with epoxy or solder preform or by ventilating in nitrogen atmosphere.

Although the invention has been described and illustrated with respect to particular embodiments, it is not intended to limit the invention, and those skilled in the art will recognize that various modifications and variations are possible within the spirit and scope of the invention. Could be.

The present invention overcomes the limitations of single chip packaging and integrates and packaged the maximum semiconductor device in a limited space to increase the mounting density, and at the same time, by mounting the appropriate patterns and other passive elements on the base substrate and the small substrate together, It is a useful invention that can be developed into a system. In addition to the bottom of the package made of the illustrated base and small substrates, multi-layer circuit boards can be developed into 3D multi-chip modules that can perform even more complex functions. It is an invention that can achieve.

Claims (5)

Small systems with special functions by overcoming the limitations of single chip packaging and by integrating and packaging the maximum number of semiconductor devices in a limited space to increase the mounting density and by mounting appropriate patterns and other passive elements on the base and small substrates. In order to be able to develop into a multi-dimensional multi-chip module, the package structure has a feature of being able to insert a plurality of chip carrier substrates while having the bottom surface of the package patterned with signal wiring. The method of claim 1, Chip carrier substrate structure that can hold several semiconductor devices with a slot pattern. The method of claim 1, When the semiconductor device is placed, a structure consisting of general die bonding / wire bonding and flip chip bonding. The method of claim 1, A structure of the bottom surface of the package made of alumina or aluminum nitride having two layers of via holes, signal wiring, and slot patterns. A method of attaching a base substrate and a small substrate, a method of attaching a lead, a method of attaching a metal case or a housing, and a method of fixing a chip carrier substrate to a slot.