KR19990051091A - A reset signal generator for error detection and automatic recovery of a synchronous transmission module timer with automatic initialization in asynchronous transmission based on synchronous digital hierarchy - Google Patents

Abstract

The present invention relates to an apparatus for generating a reset signal for error detection and automatic recovery of a STM-n (Synchronous Transport Module-n, n = 1,4,16 ..) timer in SDH based ATM communication. The present invention detects the switching operation between two clock sources from the Loss Of Signal (LOS) information of the bit synchronization device, and determines whether the digital circuit is affected by the switching, out of frame (OFF) and Framing Word Detection Indication Signal (FPID). ) If it is judged that it is abnormal operation state after judging from the information, it generates a reset signal and initializes the timer circuit of STM-n (n = 1,4,16) frame data so that it can automatically recover from abnormal operation state caused by clock glitch. The present invention relates to an apparatus for generating a reset signal for error detection and automatic recovery of a timer circuit for processing STM-n (n = 1,4,16) frame data.

Description

Reset signal generation device for error detection and automatic recovery of synchronous transmission module timer with automatic initialization in asynchronous transmission method based on synchronous digital hierarchy

The present invention is to detect the error of the STM (Synchronous Transport Module) -n (n = 1, 4, 16 ...) timer with automatic initialization in Asynchronous Transfer Mode (ATM) communication based on SDH (Synchronous Digital Hierarchy) And a reset signal generator for automatic recovery.

In ATM communication, user information is formatted into a frame structure of STM-n (n = 1, 4, 16 ..) and then transmitted and received as serial data. In order to retime the serial data transmitted over the line and recover the clock from the received data, a bit synchronization device including a PLL is essentially used. The bit synchronizer must always provide a stable clock with or without input data. That is, if input data normally exists, the clock is recovered from the received data. If there is no input data, the local clock is selected and multiplied to the required frequency. Therefore, since two clock sources are selected depending on the presence or absence of input data, there is always a possibility of occurrence of a clock click.

In the conventional method, a method of comparing clock phases of two clock sources at the moment when switching between two clock sources occurs so that clock glitches do not occur is mainly used.

The glitch present in the clock signal is generated at the moment of selecting a different clock source according to the presence or absence of input data in the bit synchronization device. In the conventional method of providing only the data and the clock recovered from the bit synchronization device, the glitch exists in the clock signal. There was no countermeasure against malfunction of digital circuit due to glitch.

In the conventional method, a method of preventing glitches in a clock generation step is mainly used. However, in the present invention, an operation in which a clock may be glitch may be detected, and at this time, an operation state of a digital circuit may be analyzed and determined to determine an abnormal state. Only when the reset signal is generated and the timer for STM-n (n = 1,4,16) frame data processing is initialized, it automatically recovers from the malfunction caused by the clock glitch.

Accordingly, in the present invention, when the operation of switching between two clock sources is detected in the bit synchronization device, when it is determined that the timer operates abnormally, the STM-n (n = 1, 4, 16) frame data for processing Its purpose is to increase the reliability of the system by initializing the timer so that it can automatically recover from malfunctions caused by clock glitches.

1 is a configuration diagram of a timer having an automatic initialization function for processing STM-n (n = 1,4,16) frame data in SDH based ATM communication;

2 is a timing diagram showing normal operation of the present invention;

3 is a timing diagram showing an operation of detecting and automatically recovering from abnormal operation by a clock glitch of the present invention;

4 is a reset signal generation circuit diagram for monitoring an abnormal operation in a timer for processing STM-n (n = 1, 4, 16) frame data and generating a reset signal for automatic recovery;

Fig. 5 is a timing diagram showing the operation of the reset signal generation circuit diagram.

<Description of the symbols for the main parts of the drawings>

200, 300, 400, 500: bit synchronizer, reset signal generator, frame aligner, alarm detector

600,700: STM decoder, local clock

109,209,309,409: 1st H2L edge detector, 2nd H2L edge detector, 2nd stage shifter, pulse generator

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

First, FIG. 1 is a configuration diagram of a timer 100 for processing STM-n (n = 1,4,16) frame data in SDH based ATM communication.

Looking at the configuration of the timer, the bit synchronization device 200 for recovering the clock from the serial data 10 outputs the LOS (20, Loss Of Signal) information, the clock 30 and the 8-bit parallel data 40. Framing word detection information which is an output of the frame aligner 400 and the frame aligner 400 which retrieve the framing word from the output 8-bit parallel data 40 of the bit synchronization device 200 and perform byte and frame boundary alignment. Alarm detector 500, which monitors whether FPID 60 appears normally in a frame period, and outputs the result, LOS 20 information of bit synchronization device 200 and OOF (50, Out Of Frame) of alarm detector 500. Information and the framing word detection information FPID 60 of the frame aligner 400 are input to monitor the operation state of the timer 100, and according to the result, a reset signal RSTB (initialization block) for initializing the component blocks of the timer 100 device. A reset signal generator 300 for generating 70, an STM decoder 600 for providing various timing signals 110 for STM-n (n = 1, 4, 16) frame data processing, and a frame aligner 400 Input the output FPID (60) and output OOF (50) of the alarm detector (500). A NAND gate 201, a two-input AND gate 101 which inputs the output of the NAND gate 201 and the output RSTB 70 of the reset signal generator 300, a local clock source 700, or the like. Consists of.

In FIG. 1, the bit synchronization device 200 monitors the serial input data 10 received through the line and sets the output LOS 20 to '1' when no transition occurs in the input data for a predetermined time. If it is set and input data exists normally, it outputs as '0'. When the serial input data exists, the clock is recovered from the serial input data 10. When there is no input data, the local clock source 700 is multiplied and used. That is, when the LOS 20 signal is '0', the clock is recovered from the input data 10, and when the LOS 20 signal is '1', the local clock source 700 is selected and used. The glitch component of the clock is generated at the moment of switching between two clock sources. In addition, the bit synchronization device 200 simply serial-to-parallel converts the serial input data 10 to output 8-bit parallel data 40 having no byte boundary aligned.

The frame aligner 400 retrieves the framing word from the 8-bit parallel data 40 stream of the bit synchronizer 200, aligns the byte and the STM-n (n = 1, 4, 16) frame boundary, and inputs the frame boundary. Whenever a unique framing word is detected in the 8-bit parallel data 40 stream, the framing word detection information FPID 60 is output as '1'.

The alarm detector 500 monitors whether or not a framing word is normally detected every frame in the received data. The strobe pulse STB of one clock width having a logical value of '1' in a frame period at a predetermined position from the STM decoder 600 is detected. In step 90, it is checked whether the framing word detection information FPID 60 of the frame sorter 400 appears. As shown in the ITU-T recommendation, if the framing word is not confirmed in the frame period for four consecutive frames, the OOF 50 is declared as '1'. If the normal framing word is detected for two consecutive frames, the OOF 50 is outputted as '0'. do.

The reset signal generator 300 corresponding to the present invention includes the output LOS 20 of the bit synchronization device 200, the frameword detection information FPID 60 of the frame aligner 400, and the output OOF of the alarm detector 500. 50) When the state transition occurs from the LOS 20 signal to '1'-> '0' and analyzes the correlation between the frameword detection information FPID 60 and the OOF 50, and confirms the abnormal operation state. It is determined that the clock has been affected by the glitch, and the reset signal of one clock width having a logical '0' value for initializing the frame sorter 400, the alarm detector 500, and the STM decoder 600 of the timer 100 ( Output 70).

The STM decoder 600 is composed of a counter that operates at STM-n (n = 1, 4, 16) frame periods, and a decoder for decoding the output of the counter. STM-n (n = 1) 4 and 16 output various timing signals 110 necessary for frame data processing, and provide the strobe pulse STB 90 of the frame period to the alarm detector 500.

2 shows a general operation of the timer 100 generating a timing signal for processing STM-n (n = 1,4,16) frame data in SDH based ATM communication.

The framing word detection information FPID (60) is shifted from the position of the strobe pulse STB (90), which is the output of the four-frame continuous STM decoder 600, after the frame periodicity of the framing word detection information FPID (60) is broken at the 'A' position in FIG. OOF 50 is declared as '1' ('B' in Fig. 2) and OOF 50 information and framing word detection information FPID 60 are generated to generate a timing signal aligned to a new frame boundary. The reset signal ('C' in FIG. 2) generated through the NAND gate 201 and the AND gate 101 having the input as the input initializes the STM decoder 600. Therefore, the STM decoder 600 initialized by the reset signal 89 outputs the timing signal 110 and the strobe pulse STB 90 signal arranged in a new frame, and the framing word detection information FPID 60 is continuous for two frames. OOF 50 is released to '0' because it is identified at the strobe pulse STB 90 position, which is the output of STM decoder 600 ('D' in FIG. 2).

3 detects when the timer 100 operates in an abnormal state by a clock glitch caused by the bit synchronization device 200 in the timer 100 device and generates a reset signal for initialization to generate the timer 100. The reset signal generator 300, the frame sorter 400, the alarm detector 500, and the STM decoder 600 are initialized to recover the normal state.

'E' of FIG. 3 shows a clock glitch caused by switching operations between clock sources in the bit synchronization device 200 as an example, and 'F' shows the effect of the clock glitch despite detecting two consecutive framewords. Since the Out Of Frame state is not released, the reset signal generator 300 determines that this is an abnormal state and is a reset signal 70 generated for initialization.

4 is a detailed circuit diagram of the reset signal generator 300.

Its configuration is the H2L edge detector 109 which monitors the switching from '1' to '0' of the LOS 19 and outputs a '0' pulse of one clock width, and from '1' to '0' of the OOF 39. H2L edge detector 209 for monitoring switching to 0 'and outputting' 0 'pulse of one clock width, two-stage shifter 309 for shifting OOF 39 information to pulse period of FPID 59, and H2L The edge detector 109, the H2L edge detector 209, and the pulse generator 409 for generating a '0' pulse having a FPID 59 pulse width in accordance with the outputs of the two-stage shifter 309.

In addition, in FIG. 4, the H2L edge detector 109 includes a D flip flop 11 for inputting the LOS 19 and a D flip flop 21 for inputting the output Q 61 of the D flip flop 11. And an OR gate 41 for inputting the output QB 71 of the D flip-flop 21 and the output Q 61 of the D flip-flop 11, and the output LOS of the bit synchronization device 200. Whenever (19) switches from '1' to '0', an '0' pulse 51 of one clock width is output. This pulse output 51 is used to initialize the H2L edge detector 209, the second stage shifter 309 and the pulse generator 409 block of the reset signal generator 300. It is used to eliminate the effects of clock glitches that can be caused at the moment of switching the distance.

The H2L edge detector 209 is configured in the same manner as the H2L edge detector 109 and monitors the switching from '1' to '0' of the OOF 39 to monitor the '0' pulse 52 of one clock width. Output This pulse is used to initialize the pulse generator 409.

The second stage shifter 309 has an OOF 39 signal connected to the '1' input terminal and connected to the output Q 93 of the D flip-flop 23 mixed with the OOF 39 and the D flip-flop 113. The muxed D flip-flop 23 and the output Q of the muxed D flip-flop 23 whose outputs of the three-input AND gate 13, which takes the output Q 83 of the inputs, are connected to an input terminal of '0'. 3 is connected to an input terminal of '1' and inputs the output Q 73 of the OOF 39, the muxed D flip-flop 43, and the output Q 83 of the D flip-flop 113 as inputs. The muxed D flip-flop 43 whose output of the input AND gate 33 is connected to an input terminal of '0', the output Q 73 of the muxed D flip-flop 43 and the FPID 59 as inputs. 2 input NAND gate 53, and D flip-flop 113, etc., which inputs the output 63 of the 2 input NAND gate 53, and the output 63 of the two-stage shifter 309. The OOF 39 is set to '1' even though the pulse of the FPID 59 is confirmed more than once. Outputs a '0' pulse having a width of FPID 59 only when 'is maintained.

The pulse generator 409 has a D flip-flop 24 for delaying the output 51 of the H2L edge detector 109 by one clock, and an output Q 84 of the D flip-flop 24 is connected to the 'S' input terminal. And the output 114 of the two-input AND gate 34 which inputs the output Q 104 of the mixed D-flop 54 and the output 52 of the H2L edge detector 209 to the '1' input terminal. Muxed D flip-flop 54, VDD connected to input terminal of '0' so that '1' is always applied, output QB 124 and two-stage shifter of muxed D flip-flop 54 A two-input OR gate 74 having an output 83 of 309 as an input, an output 51 of the H2L edge detector 109, and an HRSTB 29, which is a hardware reset signal input from the outside, are input. 2 input AND gates 14, and the like. In this configuration, the pulse width of the FPID 59 only when the LOS 19 is switched from '1' to '0' and the FPID 59 pulse is checked more than once, but the OOF 39 remains '1'. Output a '0' pulse 134 with

5 is an operation timing diagram of the reset signal generator 300.

Switching from '1' to '0' in the LOS 19 signal and FPID 59 pulses for initialization when OOF 39 has a value of '1' until three FPIDs 59 are identified. It shows outputting a '0' pulse RSTB 134 having a width. This output RSTB 134 continues to be output in three FPID 59 pulse periods when the OOF 39 is not released to '0' even though the FPID 59 signal normally appears.

If malfunction is detected by clock glitch and abnormal status is confirmed, STM-n (n = 1,4,16) is automatically initialized to restore normal status. Thus, system reliability can be improved by recovering from malfunctions caused by clock glitches without a separate hardware reset.

Claims (4)

In STM-n (n = 1,4,16, ...) timer structure with automatic initialization function in ATM communication based on SDH, When the output signal loss information (LOS) 19 of the bit synchronization device switches from the '1' to the '0' state, the H2L edge detector 109 outputs a '0' pulse 51 of one clock width. ; The H2L is configured in the same manner as the H2L edge detector 109, and outputs a '0' pulse 52 of one clock width by monitoring switching from '1' to '0' of the frame alert (OOF) 39. An edge detector 209; Although the pulse of the framing word detection information (FPID) 59 from the alarm detector has been checked more than once, the framing word detection information (FPID) 59 only when the frame alarm (OOF) 39 is kept '1'. A two stage shifter 309 for outputting a '0' pulse having a width; And Framing word detection only when frame alarm 39 maintains '1' even though the signal loss information 19 is switched from '1' to '0' and the framing word detection information 59 pulse is checked more than once. And a pulse generator (409) for outputting a '0' pulse (134) having a pulse width of information (59). The method of claim 1, The H2L edge detector 109, A D flip-flop 11 for inputting signal loss information 19; A D flip flop (21) which takes an output Q (61) of the D flip flop (11) as an input; And And an OR gate (41) for performing an OR operation as the input QB (71) of the D flip flop (21) and the output Q (61) of the D flip flop (11). The method of claim 1, The two stage shifter 309 is The frame alert (OOF) 39 signal is connected to an input terminal of '1' and is connected to the output Q 93 of the D flip-flop 23, which is muxed with the frame alert 39, to the D flip-flop 113. A muxed D flip-flop 23 having an output of a three-input AND gate 13 having an output Q 83 as an input thereof connected to an input terminal of '0'; The output Q 93 of the muxed D flip-flop 23 is connected to an input terminal of '1' and the frame alert 39, the output Q 73 of the muxed D flip-flop 43 and the D flip-flop ( A muxed D flip-flop 43 having an output of a three-input AND gate 33 that takes an output Q83 of 113 as an input to a '0' input terminal; A two-input NAND gate 53 for inputting the output Q 73 and the framing word detection information 59 of the muxed D flip-flop 43; And a D flip-flop (113) having an output (63) of the two-input NAND gate (53) as an input. The method of claim 1, The pulse generator 409, A D flip-flop (24) for delaying the output (51) of the H2L edge detector (109) by one clock; The output Q 84 of the D flip-flop 24 is connected to the 'S' input terminal, and the output Q 104 of the muxed D flip-flop 54 and the output 52 of the H2L edge detector 209 are connected. A muxed D flip with the power supply VDD connected to the input terminal of '0' so that the output 114 of the two-input AND gate 34 as an input is connected to the '1' input terminal and is always applied with a '1'. Flop 54; A two-input orifice (74) for inputting the output QB (124) of the muxed D flip-flop (54) and the output (83) of the two-stage shifter (309); And And a two-input AND gate (14) for inputting an output (51) of the H2L edge detector (109) and an HRSTB (29), which is a hardware reset signal input from the outside.