KR19990049418A - Data output buffer circuit - Google Patents

Abstract

1. Technical field to which the invention described in the claims belongs

The present invention relates to a data output buffer circuit which can minimize the influence of noise caused by power lines when reading data stored in a memory cell and transferring the data output to another device.

2. Technical problem that the invention tries to solve

It is to reduce the output noise by the power supply line and to ensure a sufficient output level.

3. Summary of the solution of the invention

The output voltage driving circuit is composed of small sized driving circuit and large sized driving circuit to drive the two driving circuits with a certain time difference.

4. Important uses of the invention

A data output buffer circuit of all semiconductor memory devices for reading data stored in a memory cell to the outside.

Description

Data output buffer circuit

The present invention relates to a data output buffer circuit, and more particularly, to a data output buffer circuit capable of minimizing the influence of noise caused by power lines when reading data stored in a memory cell and transferring the data output to an arbitrary input device.

In general, a data output buffer circuit uses a large size PMOS transistor and an NMOS transistor to supply a large current to bear a large load of an output driver circuit. At this time, the noise caused by the power line is generated by the instantaneous large current, which affects the input / output level of the product, thereby degrading the characteristics of the product. If the size of the PMOS transistors and NMOS transistors used as output voltage driving circuits is reduced to solve the noise caused by the power line, a desired output level is abnormally output.

Therefore, the present invention is configured by dividing the output voltage driving circuit into a small output voltage driving circuit and a large output voltage driving circuit, and turning on and outputting the small output voltage driving circuit to raise or lower the output potential. It is an object of the present invention to provide a data output buffer circuit that can solve the above-mentioned disadvantages by sensing output potential and turning on a large output voltage driving circuit to output data.

The data output buffer circuit according to the present invention for achieving the above object is an output data enable control circuit for sensing the data stored in the memory cell to output to the first and second data lines, and the first and second data A first output voltage driving circuit for driving output data by inputting data supplied through a line through first and second inverters, and an output data enable control circuit supplied through the first and second data lines First and second latch circuits for latching output data of the first and second latch circuits, and second output voltage drives for driving output data by inputting the output data of the first and second latch circuits through third and fourth inverters. A circuit and an output circuit for supplying output data of the first and second output voltage driving circuits to an output terminal. And that is characterized.

Also, an output data enable control circuit for sensing data stored in a memory cell and outputting the data to the first and second data lines, and outputting the data supplied through the first and second data lines to the first and second inverters. A first output voltage driving circuit for driving output data as an input via the first voltage control circuit, and a first voltage control circuit outputting a first control signal in accordance with output data of the output data enable control circuit and output data of the first inverter. And a second voltage control circuit for outputting a second control signal in accordance with output data of the output data enable control circuit and output data of a second inverter, and output according to output data of the first and second voltage control circuits. A second output voltage driving circuit for driving data and output data of the first and second output voltage driving circuits; It characterized in that it comprises an output circuit for supplying.

1 is a data output buffer circuit diagram according to the present invention;

Figure 2 is another embodiment of a data output buffer circuit according to the present invention.

<Explanation of symbols for main parts of the drawings>

1, 11: output data enable control circuit 2, 12: first output voltage driving circuit

3 and 4: first and second latch circuits 5 and 15: second output voltage driving circuit

6, 16: output circuit 7, 17: output terminal

13 and 14: first and second voltage driving circuit

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of a data output buffer according to an exemplary embodiment of the present invention. After sensing and controlling data stored in a memory cell (not shown), output data for outputting the controlled data to the first and second data lines A and B is shown in FIG. Output data of the enable control circuit 1 and the output data enable control circuit 1 supplied through the first and second data lines A and B are output to the first and second inverters I1 and I2. First and second latch circuits 3 and 4 which stably store the output data of the first output voltage driving circuit 2 and the output data enable control circuit 1. And a second output voltage driving circuit 5 which is driven secondary by inputting the output data of the first and second latch circuits 3 and 4 through the third and fourth inverters I3 and I4; Outputs the first and second output voltage driving circuits 2 and 5; An output circuit (6) for supplying the emitter to the output terminal (7).

Referring to the operation of the data output buffer circuit according to the present invention configured as described above in detail as follows.

The first and second data lines A and B when the potentials of the first and second data lines A and B controlled by the output data enable control circuit 1 are both high. The potential of is reversed to the low state through the first and second inverters I1 and I2 and input to the first driving circuit 2, respectively. At this time, the first pull-up transistor P1 of the first output voltage driving circuit 2 having the output of the first inverter I1 is turned on while the first pull-up transistor P1 has the output of the second inverter I2 as the input. Pull-down transistor N1 is turned off. Therefore, the high state output of the first output voltage driving circuit 2 is supplied to the node K1. In addition, the output of each of the first and second inverters I1 and I2 is input to the first and second latch circuits 3 and 4 so that the output is latched in a high state. The high state output latched to the first and second latch circuits 3 and 4 is inverted back to a low state through the third and fourth inverters I3 and I4 to the second output driving circuit 5, respectively. Will be entered. At this time, the second pull-up transistor P2 of the second output voltage driving circuit 5 having the output of the third inverter I3 is turned on while the second having the output of the fourth inverter I4 is input. Pull-down transistor N2 is turned off. Therefore, the output of the normal high state of the second output voltage driving circuit 5 is supplied to the node K1, and the voltage of the normal high state is output. At this time, the first and second latch circuits 3 and 4 maintain the same data until the output potentials of the first and second inverters I1 and I2 change.

That is, the first and second output voltage driving circuits 2 and 5 have a slight time difference, and after the first output voltage driving circuit 2 is first turned on, the second output voltage driving circuit 5 is set to 2. The vehicle is turned on and the potential of the node K1 becomes high. The voltage of the node K1, which is the output of the first and second output voltage driving circuits 2 and 5, is output in the high state to the output terminal 7 through the output circuit 6.

In contrast, when the potentials of the first and second data lines A and B controlled by the output data enable control circuit 1 are both low, the first and second output voltage driving circuits ( The first and second pull-up transistors P1 and P2 of 2 and 5 are turned off while the first and second pull-down transistors N1 and N2 are turned on at regular time intervals so that the first output voltage driving circuit ( The output of 2) goes to the low state primarily, and the output of the second output voltage drive circuit 5 goes to the low state secondary. Therefore, the potential of the node K1 goes low.

In addition, when the potential of the first data line A is high and the potential of the second data line B is low, the output potential of the first output voltage driving circuit 2 is first turned low. After that, the output potential of the second output voltage driving circuit 5 is brought into a low state in a secondary manner, and the potential of the node K1 is brought into a low state. Therefore, the voltage output through the output circuit 6 to the final output terminal 7 goes low.

However, when the potential of the first data line A is low and the potential of the second data line B is high, the first and second of the first and second output voltage driving circuits 2 and 5 are high. Both the pull up and pull down transistors are turned off, which causes the output data output to the output terminal 7 to be in a high impedance (Hi-Z) state.

FIG. 2 is a diagram illustrating another embodiment of a data output buffer circuit according to an exemplary embodiment of the present invention. After sensing and controlling data stored in a memory cell (not shown), the controlled data is transferred to the first and second data lines A and B. First and second output data enable control circuits 11 for outputting and output data of each of the output data enable control circuits 11 supplied through the first and second data lines A and B, respectively. 2, the first output voltage driving circuit 12 driven as input via the inverters I11 and I12, the output data of the output data enable control circuit 11 and the output data of the first inverter I11. According to the first voltage control circuit 13 outputting the first control signal and the output data of the output data enable control circuit 11 and the output data of the second inverter I12. The second voltage A second output voltage driving circuit 15 which is driven second by inputting the circuit 14, the output data of the first and second voltage control circuits 13 and 14, respectively, and the first and second outputs; It consists of an output circuit 16 for supplying the output data of the voltage drive circuits 12 and 15 to the output terminal 17. In addition, the second output voltage driving circuit 15 has a plurality of transistors connected in parallel to each of the pull-up and pull-down transistors P2 and N2 in order to drive the output data quickly.

Referring to the operation of the data output buffer circuit according to the present invention configured as described above in detail as follows.

When the potentials of the first and second data lines A and B controlled by the output data enable control circuit 11 are both high, the first and second data lines A and B The potential of is inverted to a low state through the first and second inverters I11 and I12, respectively, and is input to the first output voltage driving circuit 12. At this time, while the first pull-up transistor P1 of the first output voltage driving circuit 12 having the output of the first inverter I11 is turned on, the first output having the output of the second inverter I12 is input. Pull-down transistor N1 is turned off. Therefore, the output of the high state of the first output voltage driving circuit 12 is supplied to the node K1.

In addition, the first voltage control circuit 13 which inputs the data of the first data line A, which is the output of the output data enable control circuit 11, and the output data of the first inverter I11, respectively, is a first input. The PMOS transistor P11 is turned off and the second PMOS transistor P12 is turned on so that the output is output in a low state. In addition, the second voltage control circuit 14 which inputs the data of the second data line B, which is the output of the output data enable control circuit 1, and the output data of the second inverter I2, respectively, is a third one. The PMOS transistor P13 is turned on, and the fourth PMOS transistor P14 is turned off to be output in a low state. Therefore, the second output voltage drive circuit 15 having the output of the first and second voltage control circuits 13 and 14 as an input is the second pull-up having the output of the first voltage control circuit 13 as an input. The transistor P2 is turned on while the second pull-down transistor N2, which takes the output of the second voltage control circuit 14 as an input, is turned off. Therefore, the output of the normal high state of the second output voltage driving circuit 15 is supplied to the node K1, and the voltage of the normal high state is output.

That is, the first and second output voltage driving circuits 12 and 15 have a slight time difference, and after the first output voltage driving circuit 12 is first turned on, the second output voltage driving circuit 15 is set to 2. The vehicle is turned on and the potential of the node K11 becomes high. The voltage of the node K11, which is the output of the first and second output voltage driving circuits 12 and 15, is output in a high state to the output terminal 7 through the output circuit 6.

Conversely, when the potentials of the first and second data lines A and B controlled by the output data enable control circuit 11 are both low, the first and second output voltage driving circuits 12 and 15. Of the first and second pull-up transistors P1 and P2 are turned off, and the first and second pull-down transistors N1 and N2 are turned on at regular time intervals so that the output of the first output voltage driving circuit 12 The state goes low first, and the output of the second output voltage drive circuit 15 goes state low. At this time, the outputs of the first and second voltage control circuits 3 and 4 go low. Therefore, the potential of the node K11 to which the outputs of the first and second output voltage driving circuits 12 and 15 are supplied becomes low, and is supplied to the output terminal 17 through the output circuit 16. The voltage goes low.

In addition, when the potential of the first data line A is high and the potential of the second data line B is low, the output potential of the first output voltage driving circuit 12 is first low. After that, the output potential of the second output voltage driving circuit 15 is made low in the secondary state, and the potential of the node K11 is made low. Thus, the voltage output to the final output terminal 17 through the output circuit 16 goes low.

In contrast, when the potential of the first data line A is low and the potential of the second data line B is high, the pull-up and pull-down transistors of the first and second output voltage driving circuits 12 and 15 All of them are turned off, so that the output data output to the output terminal 17 is in a high impedance (Hi-Z) state.

As described above, according to the present invention, the output voltage driving circuit is composed of a small driving circuit and a large driving circuit, and the two driving circuits are driven at a constant time difference, thereby reducing output noise caused by the power supply line, and There is an excellent effect to ensure the output level.

Claims (5)

An output data enable control circuit for sensing data stored in the memory cell and outputting the first and second data lines; A first output voltage driving circuit for driving output data by inputting data supplied through the first and second data lines through first and second inverters; First and second latch circuits for latching output data of an output data enable control circuit supplied through the first and second data lines; A second output voltage driving circuit for driving output data by inputting the output data of the first and second latch circuits through third and fourth inverters; And an output circuit for supplying output data of the first and second output voltage driving circuits to an output terminal. The first output voltage driving circuit of claim 1, wherein the pull-up and pull-down transistors are connected in series between a power supply terminal and a ground terminal, and configured to be driven according to an input of output data of the output data enable control circuit. Data output buffer circuit. The data output buffer circuit as claimed in claim 1, wherein the second output voltage driving circuit includes pull-up and pull-down transistors having a larger current driving force than the current driving force of the first output voltage driving circuit. The second output voltage driving circuit of claim 1, wherein the second output voltage driving circuit is configured such that pull-up and pull-down transistors are connected in series between a power supply terminal and a ground terminal, and driven according to an input of data latched to the first and second latch circuits. Output buffer circuit. An output data enable control circuit for sensing data stored in the memory cell and outputting the first and second data lines; A first output voltage driving circuit for driving output data by inputting data supplied through the first and second data lines through first and second inverters; A first voltage control circuit outputting a first control signal according to output data of the output data enable control circuit and output data of the first inverter; A second voltage control circuit outputting a second control signal in accordance with output data of the output data enable control circuit and output data of a second inverter; A second output voltage driving circuit for driving output data according to the output data of the first and second voltage control circuits; And an output circuit for supplying output data of the first and second output voltage driving circuits to an output terminal.