KR19990048187A - Subboard Recognition System and Method in ATM-LAN Interface Board - Google Patents

Abstract

The present invention relates to an ATM-LAN system, and in particular, a main board recognizes a sub board on an interface board so that each board in a NMS (Network Management System) The present invention relates to a sub-board recognition system and method in an ATM-LAN interface board implemented to automatically recognize information.

In the prior art, the main board was not provided with a hardware signal from the sub board, but according to the present invention, when the CPU of the main board reads the sub board recognition area allocated on the memory map by the present invention. NMS activates the output enable signal in the buffer and receives each recognition signal applied through the three-way jumper of the sub-board and switches to the data bus to automatically recognize whether the corresponding sub-board is installed and the type. It can automatically collect information from, providing convenience for effective information recognition.

Description

Subboard Recognition System and Method in ATM-LAN Interface Board

The present invention relates to an ATM-LAN system, and in particular, a main board recognizes a sub board on an interface board so that each board in a NMS (Network Management System) The present invention relates to a sub-board recognition system and method in an ATM-LAN interface board implemented to automatically recognize information.

The general AMT-LAN system includes an ATM physical layer device, an UPC / OAM device, and a routing table device on a main board including various peripheral devices such as a CPU and a DRAM. In the method of recognizing the sub board, the main board could not recognize the sub board in hardware, but it is assumed that the user knows the information of the sub board in the NMS that manages the whole system. In case of inputting any value manually, the NMS shows the information of the manually inputted sub-board.

In other words, when the main board recognizes the sub board, the NMS recognizes the specific sub board, and the main board does not directly receive the hardware signal from the sub board, and the existence of the sub board already exists. On the assumption that you know it, the NMS itself displays the appropriate random values.

As described above, the conventional technology has a disadvantage in that the main board does not receive the hardware signal from the sub-board and the NMS does not automatically collect information and must manually indicate an arbitrary input value.

In order to solve the above disadvantages, an object of the present invention is to enable the NMS-LAN interface board to automatically collect the information of each board in the NMS by automatically recognizing the sub-board directly.

In other words, when the main board consisting of the CPU and peripheral devices is to recognize the sub board consisting of the AMT physical layer and the AMT layer on the interface board constituting the ATM-LAN system, the subboard on the memory map of the CPU In order to recognize the information effectively in the NMS by recognizing the purpose, there is a purpose.

1 is a block diagram showing a sub-board recognition system in the AT-LAN interface board according to an embodiment of the present invention.

2 is a flowchart illustrating a method for recognizing a sub board in an AT-LAN interface board according to an exemplary embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

10: main board 11: address decoding unit

12: buffer control unit 13: buffer

14 CPU 15 Memory

20-1 to 20-N: Sub board 21-1, 21-2: Three way jumper

22-1, 22-2: pull-up resistor 23-1, 23-2: pull-down resistor

Sub-board recognition system in the ATM-LAN interface board according to an embodiment of the present invention for achieving the above object, in the ATI-LAN system, a plurality of settings for generating a recognition signal by setting its own recognition intrinsic value, respectively Two sub-boards; And a main board for automatically recognizing whether the sub board is mounted and the type thereof by allocating a sub board recognition area by the recognition signal applied from each sub board.

Here, each sub board includes two pull-up resistors connected to a power source; Two pull-down resistors connected to ground; Two terminals are respectively connected to the one pull-up resistor and one pull-down resistor, and the other terminal is respectively connected to the main board, and the recognition signal is applied to the main board according to the connection relationship between the other terminal and the two terminals. It characterized in that it comprises two jumpers to the main board, the main board comprises a memory unit having a sub-board recognition area allocated on the memory map by the control data; An address decoding unit for detecting whether the sub-board recognition region stored in the memory unit is read and generating a read detection signal; A buffer controller which receives a read detection signal from the address coding unit and activates an output enable signal; A buffer which loads a recognition signal applied from each sub-board by a data bus by activating an output enable signal of the buffer controller; And a CPU that allocates and reads a sub-board recognition area in the memory unit, reads the recognition signal through the data bus, and recognizes whether or not each sub-board is mounted.

The number of subboard recognitions for recognizing the subboards is equal to 1/2 of the total number of bits of the buffer.

In addition, the sub-board recognition method in the ATM-LAN interface board according to an embodiment of the present invention, when the sub-board recognition area on the memory map is read, A first step of detecting whether to read; A second step of activating an output enable signal by applying a read detection signal when detecting that the sub-board recognition region has been read; And a third process of switching the recognition signal to the data bus to automatically recognize whether the sub-board is mounted and the type according to the switched recognition signal.

Hereinafter, with reference to the accompanying drawings will be described as follows.

1 is a block diagram illustrating a sub-board recognition system in an AT-LAN interface board according to an exemplary embodiment of the present invention, and FIG. 2 illustrates a sub-board recognition method in an AT-LAN interface board according to an exemplary embodiment of the present invention. The flow chart shown.

First, referring to FIG. 1, a configuration of a sub-board recognition system in an AT-LAN interface board according to an embodiment of the present invention for automatically recognizing a sub-board in a main board is a board composed of a CPU and peripheral devices. It may be divided into a main board 10 and a plurality of sub boards 20-1 to 20-N which are AT boards related to ATM protocol.

The main board 10 receives the recognition signals S1 and S2 from each of the sub boards 20-1 to 20 -N and allocates a sub board recognition area to each of the sub boards 20-1 to 20 -N. ) Can be automatically recognized whether or not it is mounted, and includes an address decoding unit 11, a buffer control unit 12, a unidirectional buffer 13, a CPU 14, and a memory unit 15. It is done by

In this case, the address decoding unit 11 detects the address bus of the CPU 14 to generate a read detection signal, and applies the activation signal to the buffer control unit 12.

The buffer control unit 12 receives a read detection signal from the address coding unit 11, generates an output enable signal (/ OE), applies the buffer to the buffer 13, and generates an output enable signal (OEOE). Perform activation control.

The buffer 13 stores the recognition signals S1 and S2 applied from the sub-boards 20-1 to 20-N according to the output enable signal / OE applied from the buffer control unit 12. Switch to the CPU 14 via the bus.

The CPU 14 allocates a sub board recognition area to a memory map of the memory unit 15, reads the allocated sub board recognition area, and switches the recognition signals S1 and S2 that are switched through the buffer 13. ) To recognize whether each sub-board (20-1 ~ 20-N) is mounted and the type.

The sub-board recognition area is allocated on the memory map under the control of the CPU 14, and the sub-board recognition area secured by the address decoding unit 11 is synthesized.

Each of the sub-boards 20-1 to 20 -N sets its own unique value and applies recognition signals S 1 and S 2 to the main board 10. -Way jumpers 21-1 and 21-2, two pull-up resistors 22-1 and 22-2, and two pull-down resistors 23-1, 23-2).

Here, the two jumpers 21-1 and 21-2 are equipped with one pull-up resistor 22-1 and 22-2 and pull-down resistors 23-1 and 23-2, respectively. The first pull-up resistor 22-1 and the first pull-down resistor 23-1 are connected to two terminals of the first jumper 21-1, and the other terminal is connected to the main board 10. The second pull-up resistor 22-2 and the second pull-down resistor 23-2 are connected to two terminals of the second jumper 21-2, and the other terminal is connected to the main board 10. have.

The jumpers 21-1 and 21-2 are connected to the pull-up resistors 22-1 and 22-2 or the pull-down resistors 23-1 and 23-2 to set the recognition eigenvalues that are unique values, thereby recognizing the recognition signal. S1 and S2 are applied to the main board 10 side.

The pull-up resistors 22-1 and 22-2 are connected to the power supply Vcc and allow the 'high' level recognition signals S1 and S2 to be applied to the jumpers 21-1 and 21-2. .

The pull-down resistors 23-1 and 23-2 are connected to the ground GND, and enable the low-level recognition signals S1 and S2 to be applied to the jumpers 21-1 and 21-2. .

Next, the process of performing the operation of the sub-board recognition system in the AT-LAN interface board according to an embodiment of the present invention will be described as follows.

First, the operation of each sub board 20-1 to 20-N will be described. Each of the jumpers 21-1 and 21-2 provided in the sub boards 20-1 to 20-N may be powered. By connecting to pull-up resistors 22-1 and 22-2 connected to Vcc) or to pull-down resistors 23-1 and 23-2 connected to ground GND, the respective sub-boards 20 are connected. -1 to 20-N) can be set.

That is, when the respective jumpers 21-1 and 21-2 are connected to the pull-up resistors 22-1 and 22-2, the respective jumpers are connected through the pull-up resistors 22-1 and 22-2. Since the power supply Vcc is applied to the 21-1 and 21-2, the recognition signals S1 and S2 of the 'high' level are applied to the main board 10.

On the contrary, when the respective jumpers 21-1 and 21-2 are connected to the pull-down resistors 23-1 and 23-2, the respective jumpers are connected through the pull-down resistors 23-1 and 23-2. Since 21-1 and 21-2 are connected to the ground GND, the recognition signals S1 and S2 of the 'low' level are applied to the main board 10. Here, the first recognition signal S1 is a recognition signal output through the first jumper 21-1 and the second recognition signal S2 is a recognition signal output through the second jumper 21-2.

For example, as shown in Table 1 below, recognition intrinsic values of the sub-boards 20-1 to 20-N may be set. Here, "H" represents a recognition signal of a "high" level and "L" represents a recognition signal of a "low" level.

S1 S2 Type of sub board L L No condition H L No condition L H Single mode H H Multi mode

Accordingly, the recognition signals S1 and S2 output from the sub boards 20-1 to 20 -N are applied to the main board 10, that is, the main board 10 is the jumper 21. -1, 21-2) receives a recognition signal of 'high' level or 'low' level.

Thus, the main board 10 further secures the sub board recognition area on the memory map in the memory unit 15, that is, the address decoding unit 11 provided in the main board 10 secures the corresponding area. The sub board recognition area is synthesized.

Accordingly, the recognition process of the main board 10 will be described with reference to the flowchart of FIG. 2, that is, the sub-boards 20-1 to 20 currently present on the main board 10 in the CPU 14. In the case where it is desired to recognize the existence of -N), first, the CPU 14 reads the sub-board recognition region existing on the memory map of the memory unit 15 (step S1).

Then, the address coding unit 11 detects the address bus of the CPU 14 (step S2), detects that the sub-board recognition area has been read by the CPU 14, and activates and buffers. The control unit 12 is activated, that is, the address coding unit 11 applies a read detection signal to the corresponding buffer control unit 12 (step S3).

Accordingly, when the buffer control unit 12 receives the read detection signal from the address coding unit 11 and generates an output enable signal / OE and applies it to the buffer 13, that is, the corresponding output enable signal / When OE is activated (step S4), the corresponding buffer 13 is opened by the output enable signal / OE applied from the buffer control unit 12, so that each of the sub-boards 20-1 to 20- Recognition signals S1 and S2, which are recognition values of N), are applied to switch to the CPU 14 via the data bus (step S5).

Accordingly, the CPU 14 reads recognition signals S1 and S2 switched through the buffer 13 to automatically recognize whether each sub-board 20-1 to 20 -N is mounted and the type thereof. This can be done (step S6).

However, since the number that can recognize each of the sub-boards 20-1 to 20-N is determined according to the size and number of the buffer 13, each sub-board 20-1 to 20-N is determined. The recognized number N of sub-boards is expressed by Equation 1 below. Here, the number of bits of the buffer 13 is allocated by 2 bits per board.

N = 1/2 × number of bits in the buffer

Accordingly, if the number and type of the buffers 13 are different from each other, the sub boards 20-1 to 20-N may be theoretically recognized.

In the prior art, the main board was not provided with a hardware signal from the sub board, but by automatically recognizing the sub boards 20-1 to 20-N on the main board 10 according to the present invention, Hardware information of each of the sub-boards 20-1 to 20 -N is automatically recognized so that hardware configuration information can be known from the NMS.

As described above, when the CPU of the main board reads the sub board recognition area allocated on the memory map on the AT-LAN interface board, the output enable signal is activated to enable the three-way jumper of the sub board in the buffer. By receiving each recognition signal applied through the switch and switching to the data bus to automatically recognize whether the corresponding sub board is mounted and the type, the information of each sub board can be automatically collected by the NMS, which is convenient for effective information recognition. Can provide.

Claims (5)

An ATI-LAN system, comprising: a plurality of sub-boards 20-1 to 20-N that set their own recognition intrinsic values to generate recognition signals S1 and S2, respectively; Whether or not to mount each sub board 20-1 to 20-N by allocating the sub board recognition area by the recognition signals S1 and S2 applied from the sub boards 20-1 to 20-N. Sub-board recognition system in the ATM-LAN interface board, characterized in that comprises a main board for automatically recognizing the. 2. The apparatus of claim 1, wherein each of the sub-boards 20-1 to 20-N includes two pull-up resistors 22-1 and 22-2 connected to a power supply Vcc; Two pull-down resistors 23-1 and 23-2 connected to ground GND; Two terminals are connected to the one pull-up resistors 22-1 and 22-2 and the pull-down resistors 23-1 and 23-2, respectively, and the other terminal is connected to the main board 10, respectively. It characterized in that it comprises two jumpers (21-1, 21-2) for applying the recognition signal (S1, S2) to the main board 10 in accordance with the connection relationship between the other terminal and two terminals Sub-Board Recognition System at AMT-LAN Interface Board. 2. The apparatus of claim 1, wherein the main board (10) comprises: a memory unit (15) having a sub board recognition area allocated on a memory map by control data; An address decoding unit (11) for detecting whether or not the sub board recognition region stored in the memory unit (15) is read to generate a read detection signal; A buffer controller 12 which receives a read detection signal from the address coding unit 11 and activates an output enable signal / OE; A buffer 13 which loads the recognition signals S1 and S2 applied from the sub-boards 20-1 to 20-N by the output enable signal / OE of the buffer controller 12 to the data bus. )Wow; The sub board recognition area is allocated and read in the memory unit 15, and the recognition signals S1 and S2 are read through the data bus to determine whether or not each of the sub boards 20-1 to 20 -N is mounted. Sub-board recognition system in the AT-LAN interface board, characterized in that comprises a CPU 14 for recognizing the kind. The number of subboard recognition numbers N that can recognize the subboards 20-1 to 20 -N is 1/2 of the total number of bits of the buffer 13. Sub-board recognition system in the AT-LAN interface board, characterized in that the same as. An ATI-LAN system, comprising: a first process of detecting whether a corresponding subboard recognition region is read when a subboard recognition region existing on a memory map is read; A second step of activating an output enable signal (/ OE) by applying a read detection signal when detecting that the sub board recognition region has been read; And a third process of switching the recognition signals S1 and S2 to the data bus to automatically recognize whether the sub-board is mounted and the type according to the switched recognition signals S1 and S2. Sub board recognition method in LAN interface board.