KR19990047951A - Static random access memory device - Google Patents

Abstract

The static random access memory device of the present invention comprises at least one memory cell for storing information; A pair of bit lines connected to said memory cell; A first sense amplifying circuit connected to the pair of bit lines and configured to sense amplify a data pair transferred through the bit lines; A second sense amplifying circuit connected to the first sense amplifying circuit through a first data line pair, for secondly sensing and amplifying the data pair sensed and amplified by the first sense amplifying circuit; A switch circuit for coupling with a third data line pair corresponding to the second data line pair; A third sense amplifying circuit for third-order sense amplifying the data pair transferred from the second data line pair to the third data line pair through the switch circuit; A dynamic-static conversion circuit coupled to the third sense amplifier circuit through a fourth data line pair, for latching the data pair sense sense amplified by the third sense amplifier circuit and then transferring the data pair to the next stage; A first reset circuit for automatically generating a first reset signal for precharging and equalizing the first and second data line pairs in accordance with the potential of the first and second data line pairs; And a second reset circuit for automatically generating a second reset signal for precharging and equalizing the third data line pair in accordance with the potentials of the third and fourth data line pairs.

Description

STATIC RANDOM ACCESS MEMORY DEVICE

The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory device for automatically precharging and equalizing data lines according to its level.

In the bit line core structure of the static random access memory (SRAM), when the read path through the sense amplifier circuit is examined, the data of the selected cell is stored in a pair of bit lines BL / BLB (not shown). Will be loaded. Then, the data is loaded on the data lines RSDL and RSDLB through a column path gate (not shown) (see FIG. 1). At this time, the latch sense amplifier stage 10 activated by the signal BSAEN senses and amplifies the read data so that the data of the data lines RSDL and RSDLB are moved to the block sense amplifier stage 20.

In this case, the signal RS_SDL is used for precharge and equalization of the data lines RSDL and RSDLB. The outputs SA01 and SA01B of the latch sense amplifier stage 10, that is, delivered to the block sense amplifier stage 20, are generated as CMOS level sensing outputs called data MDL and MDLB, and the data MDL and It receives (MDLB) and finally generates data DATAA and DATAAB. Data DATAA and DATAAB are made through the asynchronous dynamic-static conversion stage 30, data DLAT and DLATB.

In this process, data lines SA01 and SA01B are precharged and equalized by the signal RS_SA01B and data lines MDL and MDLB by the signal RS_MDLB. In this read operation, sensing and data generation are possible at the optimum speed. In the conventional case, when generating such important signals RS_SA01B and RS_MDLB, using an external clock and using pulsed internal signals as a separate control signal for a sensing read path important to the performance of the chip. Doing.

However, according to the generation method of the signals RS_SA01B and RS_MDLB according to the prior art, since the operation margin is greatly influenced by the mutual margin and process variation of the internal signals, it is possible to ensure accurate and stable operation of the chip. Comes with a lot of inconvenience.

It is therefore an object of the present invention to provide a static random access memory device capable of precharging and equalizing corresponding data lines by tracking the level of the data lines.

1 is a block diagram showing the configuration of a static random access memory device according to a preferred embodiment of the present invention;

2 is an operation timing diagram according to the present invention;

* Explanation of symbols on the main parts of the drawings

10: latch detection amplifier stage 20: block detection amplifier stage

30: Asynchronous dynamic-static conversion stage 40, 50: Auto-reset circuit

(Configuration)

According to one aspect of the present invention for achieving the above object, at least one memory cell for storing information; A pair of bit lines connected to said memory cell; A first sense amplifying circuit connected to the pair of bit lines and configured to sense amplify a data pair transferred through the bit lines; A second sense amplifying circuit connected to the first sense amplifying circuit through a first data line pair, for secondly sensing and amplifying the data pair sensed and amplified by the first sense amplifying circuit; A switch circuit for coupling with a third data line pair corresponding to the second data line pair; A third sense amplifying circuit for third-order sense amplifying the data pair transferred from the second data line pair to the third data line pair through the switch circuit; A dynamic-static conversion circuit coupled to the third sense amplifier circuit through a fourth data line pair, for latching the data pair sense sense amplified by the third sense amplifier circuit and then transferring the data pair to the next stage; A first reset circuit for automatically generating a first reset signal for precharging and equalizing the first and second data line pairs in accordance with the potential of the first and second data line pairs; And a second reset circuit for automatically generating a second reset signal for precharging and equalizing the third data line pair in accordance with the potentials of the third and fourth data line pairs.

In this embodiment, the memory cell is a static random access memory.

In this embodiment, the first reset circuit comprises: a NAND gate having input terminals connected to the first data line pair; A NOR gate having input terminals connected to the second data line pair; An inverter connected to the NOR gate and for inverting its output; And a flip-flop having a setting terminal and an initialization terminal, the setting terminal being connected to an output terminal of the NAND gate, and the initialization terminal being connected to an output terminal of the inverter, and outputting a first reset signal through an output terminal. do.

In this embodiment, the flip-flop includes two latched NAND gates.

In this embodiment, the second reset circuit comprises: a NAND gate having input terminals connected to the third data line pair; A NOR gate having input terminals connected to the fourth data line pair; An inverter connected to the NOR gate and for inverting its output; And a flip-flop having a setting terminal and an initialization terminal, the setting terminal being connected to an output terminal of the NAND gate, and the initialization terminal being connected to an output terminal of the inverter, and outputting a second reset signal through an output terminal. do.

In this embodiment, the flip-flop includes two latched NAND gates.

(Action)

By such an apparatus, an external clock can be used to track the level of data lines and automatically precharge and equalize it without generating an internal signal processed by a pulse.

(Example)

Hereinafter, reference will be made in detail with reference to FIGS. 1 and 2 according to an embodiment of the present invention.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those of ordinary skill in the art, the present invention may be practiced only by the above description without these details.

In particular, the semiconductor memory device according to the present invention, in particular, a static random access memory device, receives a sensing output terminal and a sensing input terminal as inputs and uses the outputs as control signals (e.g., precharge and equalization signals) to improve the conventional problems. It is possible to generate pulsed control signals RS_SA01B and RS_MDLB while automatically tracking the lines. With this auto-tracking reset, the chip's performance depends only on process changes and external environmental factors, not on internal signal margins, and controls critical paths such as the sensing readout structure of the bit line core. There is no need for a separate control signal.

1 is a circuit diagram illustrating a sense amplification structure according to a read path of a semiconductor memory device according to an exemplary embodiment of the present invention. 2 is an operation timing diagram according to the present invention.

Referring to FIG. 1, a cell data sensing structure includes a latch sensing amplifier stage 10 that senses data lines RSDL and RSDLB on which read data is loaded through a column pass gate (not shown), and receives an output thereof. Block sensing amplification stage 20 for generating (MDL) and (MDLB) and (DATA) and (DATAB), and an asynchronous dynamic-static transformation stage for converting data (DATAA) and (DATAAB) into static data, And auto-reset circuits 40 and 50.

In Fig. 1, the transistors M1-M4 are dynamic drivers and the output of the transistor M1 is SA02 and the output of the transistor M2 is SA02B. The transistors M5, M6, M13, and M14 serve as cross coupled latches to improve noise immunity. Transistors M7, M8, M9, M10, M11, and M12 serve as clamp transistors to remove leakage current.

Auto-reset circuits 40 and 50 use control lines RS_SA01B and RS_MDLB for precharge and equalization of data lines using data lines as inputs of corresponding, significant sense amplification readout paths. Used to generate The circuits 40 and 50 comprise an RS-flipflop consisting of a NAND gate G1, a NOR gate G2, an inverter G3 and two latched NAND gates G4 and G5. do.

The auto-reset circuit 40 receives the output of the data lines to the NOR gate G2 and applies them to the reset terminal Reset of the RS flip-flop, and receives the input terminals of the data lines to the NAND gate G1. The output of the RS flip-flop generated by applying to (Set) is used as a control signal. For example, the auto-reset circuit 40 accepts the potentials on the data lines SA01 and SA01B and SA02 and SA02B as inputs so that the data lines SA01 and SA01B and SA02 and A signal RS_SA01B for precharging and equalizing SA02B is generated as shown in FIG. The auto-reset circuit 50 then accepts the potentials on the data lines MDL and MDLB and DATAA and DATAAB as inputs to precharge the data lines MDL and MDLB. A signal RS_MDLB for equalizing and an inverted signal RS_MDLB for resetting the data lines are generated as shown in FIG. 2.

As can be seen in FIG. 2, the signals RS_SA01B and RS_MDLB accept a potential on the data lines and automatically track its level to precharge and equalize the data lines. As such, the auto-reset, auto-tracking structure eliminates the need to generate a separate control signal externally to control the critical sense amplification readout path. Therefore, when generating a control signal of an important sense amplification read path from the outside, it is possible to reduce the burden of performance degradation due to the margin between signals. In addition, the performance of the sense amplification readout path is only affected by process changes or changes in external environmental factors. The adoption of this structure is also very advantageous for the implementation of critical sense amplified readout paths for high frequency, high speed readout operations and can provide improved performance.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As noted above, with auto-tracking reset, the chip's performance is controlled only by process changes and external environmental factors, not by margins of internal signals, and by sensing read-out structures of bit line cores. There is no need for a separate external control signal to control the critical path.

Claims (6)

At least one memory cell for storing information; A pair of bit lines connected to said memory cell; A first sense amplifying circuit connected to the pair of bit lines and configured to sense amplify a data pair transferred through the bit lines; A second sense amplifying circuit connected to the first sense amplifying circuit through a first data line pair, for secondly sensing and amplifying the data pair sensed and amplified by the first sense amplifying circuit; A switch circuit for coupling with a third data line pair corresponding to the second data line pair; A third sense amplifying circuit for third-order sense amplifying the data pair transferred from the second data line pair to the third data line pair through the switch circuit; A dynamic-static conversion circuit coupled to the third sense amplifier circuit through a fourth data line pair, for latching the data pair sense sense amplified by the third sense amplifier circuit and then transferring the data pair to the next stage; A first reset circuit for automatically generating a first reset signal for precharging and equalizing the first and second data line pairs in accordance with the potential of the first and second data line pairs; And a second reset circuit for generating a second reset signal for precharging and equalizing the third data line pair automatically in accordance with the potentials of the third and fourth data line pairs. The method of claim 1, And the memory cell is a static random access memory. The method of claim 1, The first reset circuit includes a NAND gate having input terminals connected to the first data line pair; A NOR gate having input terminals connected to the second data line pair; An inverter connected to the NOR gate and for inverting its output; And a flip-flop having a setting terminal and an initialization terminal, the setting terminal being connected to an output terminal of the NAND gate, and the initialization terminal being connected to an output terminal of the inverter, and outputting a first reset signal through an output terminal. A semiconductor memory device. The method of claim 3, wherein And the flip-flop includes two latched NAND gates. The method of claim 1, The second reset circuit includes a NAND gate having input terminals connected to the third data line pair; A NOR gate having input terminals connected to the fourth data line pair; An inverter connected to the NOR gate and for inverting its output; And a flip-flop having a setting terminal and an initialization terminal, the setting terminal being connected to an output terminal of the NAND gate, and the initialization terminal being connected to an output terminal of the inverter, and outputting a second reset signal through an output terminal. A semiconductor memory device. The method of claim 5, And the flip-flop includes two latched NAND gates.