KR19990047342A - Method of forming multi-layered metal wiring of semiconductor device - Google Patents
Method of forming multi-layered metal wiring of semiconductor device Download PDFInfo
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- KR19990047342A KR19990047342A KR1019970065703A KR19970065703A KR19990047342A KR 19990047342 A KR19990047342 A KR 19990047342A KR 1019970065703 A KR1019970065703 A KR 1019970065703A KR 19970065703 A KR19970065703 A KR 19970065703A KR 19990047342 A KR19990047342 A KR 19990047342A
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- 239000002184 metal Substances 0.000 title claims abstract description 130
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 24
- 230000008021 deposition Effects 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 51
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 11
- 230000000873 masking effect Effects 0.000 claims description 7
- 238000001465 metallisation Methods 0.000 claims description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 4
- 229910001111 Fine metal Inorganic materials 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 239000000470 constituent Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract description 7
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 5
- 238000010924 continuous production Methods 0.000 abstract 1
- 238000010292 electrical insulation Methods 0.000 abstract 1
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- 238000004519 manufacturing process Methods 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 229910016006 MoSi Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
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- 238000002844 melting Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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Abstract
금속 배선간의 연결을 금속비아 기둥을 이용하되, 여기에 금속비아 기둥이 연속되는 공정 과정중에 쓰러지는 문제점을 보완함으로써, 소자의 수율을 향상시킬 수 있는 반도체 소자의 다층 금속 배선방법이 개시되어 있다. 본 발명은, 금속배선 회로를 정의할때, 감광막 대신 금속 비아 기둥을 지지하는 절연막을 이용하여 금속식각을 수행하는 방법을 고안함으로써, 미세형상 형성을 용이하게 할 수 있도록 하였다. 금속 배선간의 전기적인 절연은 절연막 증착, SOG 갭-채움,절연막 증착을 통하여 이루어지며, CMP 공정기술을 이용하여 비아 기둥의 최상면이 드러나는 지점을 기준으로 평탄화를 수행한 후 2차 금속배선을 형성시킨다. 이후, 2차 금속배선 이전 까지의 단계를 반복 수행함으로써, 수율이 향상되고 공정이 용이한 다층 금속배선을 형성한다.Disclosed is a multi-layer metal wiring method of a semiconductor device which can improve the yield of a device by using a metal via pillar for connection between metal wires, and supplementing a problem in which the metal via pillar falls during a continuous process. The present invention, when defining a metal wiring circuit, by devising a method for performing metal etching by using an insulating film for supporting the metal via pillar instead of the photosensitive film, it is possible to facilitate the formation of fine shape. Electrical insulation between the metal wires is made through insulation film deposition, SOG gap-filling, and insulation film deposition, and after the planarization is performed based on the point where the top surface of the via pillar is exposed by using the CMP process technology, a second metal wiring is formed. . Thereafter, by repeating the steps before the secondary metal wiring, the yield of the multilayer metal wiring is improved and the process is easy.
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로서, 보다 상세하게는 다층의 금속 배선(multi-metal interconnection) 공정에서 금속 배선간의 연결을 위한 금속의 비아 기둥(Pillar)을 지지하는 수단을 구비하여 공정의 수율을 향상시킬 수 있는 다층 금속의 배선방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method of supporting a via pillar of metal for connection between metal wires in a multi-metal interconnection process. The present invention relates to a wiring method of a multilayer metal capable of improving yield.
일반적으로, 반도체 소자의 집적도는 제조공정이 가능한 설계 규칙(Design Rule)에 의해 결정된다. 특히, 이러한 디자인 룰은 금속배선 공정, 다시 말해, 소자간의 배선을 위한 금속의 피치(pitch)에 의해 결정된다고 해도 과언이 아닐 것이다.In general, the degree of integration of a semiconductor device is determined by a design rule capable of a manufacturing process. In particular, it would not be an exaggeration to say that this design rule is determined by the metal wiring process, that is, the pitch of the metal for wiring between the elements.
즉, 반도체 소자의 설계 규칙의 유연성을 찾고 집적도를 증가시키기 위한 제조 기술로서, 다층 금속 배선공정이 부각되고 있는 실정이다.In other words, as a manufacturing technology for increasing the degree of integration and flexibility of design rules of semiconductor devices, multilayer metal wiring processes are emerging.
이하, 종래의 다층 배선기술을 도 1 및 도 2를 참조하여 설명한다. 2층 이상의 다층인 경우 반복해서 수행되기 때문에, 2층 배선까지의 공정만 기술하기로 한다.Hereinafter, a conventional multilayer wiring technique will be described with reference to FIGS. 1 and 2. In the case of a multilayer of two or more layers, the process is repeatedly performed, and therefore only the process up to the two-layer wiring will be described.
도 1은 일반적인 종래 기술에 의해 형성된 MESFET 소자의 다층 금속 배선구조를 도시한 단면도로서, 먼저, Si 기판(1) 상에 격리(Isolation) 산화막(2-1)에 의해 소자를 분리하여 정의하고 , 소스-드레인 형성을 위한 n+층(2-3)과 케이트 층(2-2)을 형성하여 MOS 구조를 완성한다.1 is a cross-sectional view showing a multi-layered metal wiring structure of a MESFET device formed by a conventional prior art. First, a device is separated and defined by an isolation oxide film 2-1 on a Si substrate 1, The MOS structure is completed by forming an n + layer 2-3 and a gate layer 2-2 for source-drain formation.
이어, 층간절연막(2-4)를 증착한 후, 접촉 창(2-5)를 정의한다.Next, after the interlayer insulating film 2-4 is deposited, the contact window 2-5 is defined.
상기 접촉 홀(2-5) 내에 1차 금속배선(3)을 증착한다. 그리고, 1차 금속배선(3)을 사진식각 공정을 통하여 정의한 후, 금속간 절연막 (IMD; Inter-Metal Dielectric) (4)을 증착한 후, 비아 홀(5)을 사진 전사공정 및 식각 공정을 통하여 정의한다. 이어, 2차 금속배선(6)을 증착한 후, 그 2차 금속배선을 사진 전사공정 및 식각 공정을 통하여 정의하고 접합(alloy)공정을 수행하여 2차 금속 배선공정을 완료한다.The primary metal wiring 3 is deposited in the contact holes 2-5. After the primary metal wiring 3 is defined through a photolithography process, an inter-metal dielectric (IMD) 4 is deposited, and the via hole 5 is subjected to a photo transfer process and an etching process. Define through. Subsequently, after the secondary metal wiring 6 is deposited, the secondary metal wiring is defined through a photo transfer process and an etching process, and a bonding process is performed to complete the secondary metal wiring process.
그러나, 전술한 다층금속 배선공정은 여러가지 문제점을 갖고 있다.However, the multilayer metal wiring process described above has various problems.
먼저, 상기 1차 금속배선(3)과 2차 금속배선(6) 사이에 형성되는 층간 절연막(4)는 자연 발생적으로 생기는 기생 캐패시턴스(parasitic capacitance)를 줄이기 위해서 두껍게 해야하며, 이에 따라 상기 비아 홀(5)의 크기와 배선간의 층간 절연막(4)의 두께 비인 종횡비(aspect ratio)가 커지게 된다. 따라서, 종래의 물리적 금속 증착방법인 스퍼터(sputter) 방식을 사용하여 비아 홀(Via hole)(5)에 금속을 증착할 경우, 비아 홀(5) 벽면에 증착되는 금속의 두께가 얇아 전자 이동(electromigration) 등의 심각한 전기적 문제 및 비아 저항이 크게 되는 문제점이 있다.First, the interlayer insulating film 4 formed between the primary metal wiring 3 and the secondary metal wiring 6 should be thickened to reduce parasitic capacitance that occurs naturally. The aspect ratio, which is the ratio of the size of (5) and the thickness of the interlayer insulating film 4 between the wirings, becomes large. Therefore, when the metal is deposited in the via hole 5 using the sputter method, which is a conventional physical metal deposition method, the thickness of the metal deposited on the wall of the via hole 5 is thin and the electron transfer ( There are serious electrical problems such as electromigration and the like, and the via resistance becomes large.
또한, 상기 금속 배선막을 식각 시, 마스킹 역활을 하는 감광막(Photoresist)과 금속간의 낮은 식각 선택비로 인해 상대적으로 두꺼운 감광막이 불가피하게 된다. 이에 따라, 금속막 상에서 패턴(pattern) 형성 기술이 어려워지는 문제가 있다.In addition, when the metal wiring layer is etched, a relatively thick photoresist layer is inevitable due to the low etching selectivity between the photoresist and the metal. Accordingly, there is a problem that a technique for forming a pattern on the metal film becomes difficult.
근래에는, 이를 해결하기 위해 상기 비아 홀(Via hole, 5)에 금속막을 플러그(plug) 형성 등의 방법으로 채워넣는 제조기술이 이용되고 있으나, 이 역시 추가적인 장비의 도입이 불가피하며, 또한 불필요한 영역의 결함(defect)에 의한 수율(yield) 감소 등의 문제점이 있다.Recently, in order to solve this problem, a manufacturing technique of filling a metal film into a via hole 5 by a method of plugging is used, but this also introduces additional equipment, which is inevitable and unnecessary area. There is a problem such as a decrease in yield due to a defect.
도 2 는 종래의 다른 기술에 따른 다층 금속 배선방법을 도시한 것으로서, 전술한 문제점들을 해결하기 위해, 층간 금속 배선의 연결을 비아 홀에 금속막을 채워 넣은 종래 기술과는 다르게 비아 기둥(pillar)를 이용한 것이다.FIG. 2 illustrates a multi-layered metal wiring method according to another conventional technology. In order to solve the above-mentioned problems, a via pillar is different from a conventional technology in which a metal film is filled in a via hole by connecting an interlayer metal wiring. It is used.
도 2를 참조하면, 도 1의 방법과 동일하게 MOS 구조를 완성한 후, 층간절연막(2-4)를 증착한다. 이어서, 콘택 홀(2-5)을 정의한 후, 1차 금속배선(3)을 위한 금속층을 증착한다. 이어서, 비아 기둥(pillar) 형성을 위한 금속막을 증착한 후, pillar 형상을 감광막으로 정의한다.Referring to FIG. 2, after completing the MOS structure in the same manner as in the method of FIG. 1, an interlayer insulating film 2-4 is deposited. Subsequently, after defining the contact holes 2-5, the metal layer for the primary metal wiring 3 is deposited. Subsequently, after depositing a metal film for via pillar formation, the pillar shape is defined as a photosensitive film.
이어, 통상의 사진 식각 공정을 이용하여 상기 금속막을 패터닝한 후, 감광막을 제거하여 비아 기둥(pillar, 7)을 형성하고, 연이어 1차 금속배선(3) 영역을 정의하고, 금속식각을 수행한 다음, 감광막을 제거함으로써 1차 금속배선(3)이 완료된다.Subsequently, after the metal film is patterned using a conventional photolithography process, the photoresist film is removed to form via pillars 7, and subsequently, a region of the primary metal wiring 3 is defined and metal etching is performed. Next, the primary metal wiring 3 is completed by removing the photosensitive film.
이어, 층간 절연막(4))을 증착한 뒤, 기계화학적 연마(CMP; Chemical Mechanical Polishing)를 이용하여 상기 비아 기둥(7)의 최상단층이 드러날때 까지 절연막을 깍아내어 평탄화시킨다. 다음에는, 2차 금속막을 증착한 뒤, 2차 금속 미세 패턴 형성과 식각을 수행하여 2차 금속배선(6)을 형성하고, 이어서 금속 접합 (alloy)을 실시하여 다층 배선 형성을 완료한다.Subsequently, after the interlayer insulating film 4 is deposited, the insulating film is scraped and planarized using chemical mechanical polishing (CMP) until the uppermost layer of the via pillar 7 is exposed. Next, after depositing the secondary metal film, the secondary metal fine pattern is formed and etched to form the secondary metal wiring 6, and then metal bonding is performed to complete the multilayer wiring.
상기 방법은, 도 1을 참조한 종래 방법과는 다르게, 비아 기둥(pillar)(7)을 먼저 형성한 후, 1차 금속 배선공정을 나중에 수행함으로써, 비아저항 및 전자이동 (electromigration) 등의 제반 문제점을 해결할 수 있으나, 다음과 같은 치명적인 문제점을 안고 있다.Unlike the conventional method with reference to FIG. 1, the method is to form a via pillar 7 first, and then perform a primary metal wiring process later, thereby providing various problems such as via resistance and electromigration. It can solve the problem, but has the following fatal problem.
첫째, pillar(7)를 완성한 이후, IMD용 절연막(4)을 증착하는 공정 중에 비아기둥(7)이 쓰러짐으로 인해 소자의 수율을 저하시키는 치명적인 문제점이 있다. 즉, 집적도가 큰 소자일 수록 종횡비가 커지는 것을 고려할 때, 예를 들면, 64M DRAM의 경우, 대략 1um의 높이와 0.35um의 폭을 갖는 기둥(pillar)을 3개를 형성시켜야 하기 때문에, 상기 비아 기둥(4) 형성 후 이루어지는 일련의 공정들 -예컨데, 층간 절연막 증착, CMP 공정, 수차례의 사진식각 공정 등 - 로 인해 발생되는 물리적인 영향에 의해 비아기둥(7)이 쓰러지는 문제점이 대두될 수 있다. 집적회로 반도체 소자 제작 공정중에 형성되는 수천개 이상의 pillar중 단 1개의 pillar가 쓰러지더라도 불량(fail)이 되는 결과를 초래하므로, 상기의 방법은 소자의 수율에 치명적인 문제점을 갖고 있다.First, after completing the pillar 7, there is a fatal problem of lowering the yield of the device due to the falling down of the via pillar 7 during the process of depositing the insulating film 4 for the IMD. That is, considering that the greater the integration ratio, the larger the aspect ratio, for example, in the case of 64M DRAM, three vials having a height of approximately 1 μm and a width of 0.35 μm must be formed. The via pillar 7 may collapse due to physical effects caused by a series of processes after the pillar 4 is formed, for example, interlayer insulation film deposition, CMP process, and several photo etching processes. have. Since only one pillar out of thousands of pillars formed during the integrated circuit semiconductor device fabrication process is caused to fail, the above method has a fatal problem in yield of the device.
둘째, 전술한 1차 금속배선(3) 형성 과정은 먼저, 금속막위에 도포된 감광막상에 금속배선 형상을 형성시킨 후 이러한 감광막 패턴을 마스킹으로 하여 금속막을 식각하는 공정방법이 사용되고 있다. 이러한 공정방법은, 도 2(a)에 도시된 바와 같이, 비아 기둥(7) 상단부에 도포되는 감광막(PR) 두께 (a)가 pillar 이외의 지역에 도포되는 감광막 두께 (b)보다 얇게 도포되게 된다. 따라서, 감광막 패턴(PR)을 마스킹으로 하여 금속막을 식각하는 공정 과정에서 감광막과 금속막간의 식각 선택비가 2:1 정도로 작기 때문에, pillar 상단부에 도포되는 감광막 두께가 얇아 마스킹 역활에 문제가 대두된다. 이러한 문제를 해결하기 위해선 불가피하게 두껍게 감광막을 도포해야 하며 이로인해 미세패턴 형성이 어렵게 되는 단점이 있다.Second, in the above-described process of forming the primary metal wiring 3, a metal wire shape is first formed on the photoresist film coated on the metal film, and then a process method of etching the metal film by masking the photoresist pattern is used. This process method is such that, as shown in Fig. 2 (a), the thickness (a) of the photosensitive film (PR) applied to the upper end of the via pillar (7) is thinner than the photosensitive film thickness (b) applied to the region other than the pillar. do. Therefore, in the process of etching the metal film by masking the photoresist pattern PR, the etching selectivity between the photoresist film and the metal film is as small as about 2: 1. In order to solve such a problem, it is inevitably required to apply a thick photosensitive film, which has a disadvantage in that it is difficult to form a fine pattern.
셋째, 반사율이 높은 금속막(반사율 감소용 금속막 포함)위에서 도포된 감광막상에 금속배선 형상을 형성시켜야 하므로 미세패턴형성에 어려움이 있다.Third, since the metal wiring shape must be formed on the photoresist film coated on the metal film having a high reflectance (including a metal film for reducing reflectance), it is difficult to form a fine pattern.
따라서, 전술한 문제점들을 해소하기 위해 안출된 본 발명은 비아 기둥의 쓰러짐을 방지하여 수율을 향상시키면서 미세패턴 형성을 위한 공정 여유도를 증가시킬 수 있는 개선된 다층 금속 배선의 형성방법을 제공하는데 그 목적이 있다.Accordingly, the present invention devised to solve the above problems provides an improved method of forming a multi-layered metal wiring, which can increase the process margin for forming a fine pattern while preventing yield of the via pillar from falling. There is a purpose.
도 1 은 종래기술에 의해 형성된 반도체 소자의 다층 금속배선 구조를 도시한 단면도,1 is a cross-sectional view showing a multi-layered metal wiring structure of a semiconductor device formed by the prior art;
도 2 는 종래의 다른 기술에 의해 형성된 반도체 소자의 다층 금속배선 구조를 도시한 단면도,2 is a cross-sectional view showing a multilayer metallization structure of a semiconductor device formed by another conventional technique;
도 2(a) 는 도 2의 문제점을 설명하기 위한 공정 단면도,2 (a) is a cross-sectional view for explaining the problem of FIG.
도 3 은 본 발명의 바람직한 실시예에 의한 반도체 소자의 다층 금속배선 구조를 도시한 단면도,3 is a cross-sectional view illustrating a multilayer metallization structure of a semiconductor device according to a preferred embodiment of the present invention;
도 4(A)∼4(K) 도는 본 발명에 의한 다층 금속배선 방법을 순차적으로 설명하기 위한 공정 단면도이다.4 (A) to 4 (K) are cross-sectional views for sequentially explaining the multilayer metal wiring method according to the present invention.
〈 도면의 주요 부분에 대한 설명〉<Description of Main Parts of Drawings>
1 ; 실리콘 기판, 3 ; 1차 금속 배선One ; Silicon substrates; Primary metal wiring
4 ; 층간 절연막(IMD), 6 ; 2차 금속 배선4 ; Interlayer insulating film IMD 6; Secondary metal wiring
7 ; 비아 기둥(pillar), 8 ; 기둥 지지수단7; Via pillar, 8; Pillar support
상기 목적을 달성하기 위한 본 발명에 따른 다층 금속배선 형성방법은,Multi-layered metal wiring forming method according to the present invention for achieving the above object,
반도체 기판 상에 게이트, 소스/드레인 영역 및 이들의 활성영역을 격리시키기 위한 격리 절연막을 구비한 MOS 트랜지스터를 형성하는 단계; 상기 결과물 상에 층간 절연막을 형성한 후, 상기 소스/드레인 영역의 일부가 노출되도록 상기 층간절연막을 패터닝하여 콘택 홀을 형성하는 단계; 상기 콘택 홀이 충분히 도포될 수 있도록 1차 금속막과 금속층을 순차적으로 증착한 후, 상기 금속층을 패터닝하여 비아 기둥(pillar)을 형성하는 단계; 상기 결과물 전면에 균일한 두께의 기둥 지지물을 도포하는 단계; 1차 금속배선 형상을 정의하는 마스크를 사용하여 상기 기둥 지지물과 상기 1차 금속막을 식각하여 1차 금속배선을 형성함과 동시에 상기 비아기둥의 양측벽을 둘러싸는 기둥 지지층을 형성하는 단계; 결과물 전면에 금속 배선간 절연막을 증착한 후 상기 비아기둥을 연마 정지막으로 이용하여 평탄화시키는 단계; 및 상기 노출된 비아기둥과 금속접합으로 연결되는 2차 금속배선을 형성하는 단계를 포함함을 특징으로 한다.Forming a MOS transistor having an insulating insulating film for isolating gates, source / drain regions, and their active regions on a semiconductor substrate; Forming an interlayer insulating layer on the resultant, and then patterning the interlayer insulating layer to expose a portion of the source / drain region to form a contact hole; Depositing a first metal layer and a metal layer sequentially so that the contact hole is sufficiently coated, and then forming a via pillar by patterning the metal layer; Applying a pillar support having a uniform thickness to the entire surface of the resultant product; Etching the pillar support and the primary metal film using a mask defining a primary metal wiring shape to form a primary metal wiring and simultaneously forming a pillar support layer surrounding both sidewalls of the via pillar; Depositing an inter-wire insulating film on the entire surface of the resultant and then planarizing the via pillar as a polishing stop film; And forming a secondary metal wiring connected to the exposed via pillar by a metal junction.
바람직하게, 상기 비아기둥 지지층이,Preferably, the via pillar support layer,
금속 배선과의 절연성 및 식각 선택비가 크며, 반사율이 낮은 절연막으로서, 400℃ 이하의 온도에서 형성이 가능하며, PECVD(Plasma Enhanced Chemical Vapor Deposition)를 이용하여 증착된 산화막 또는 질화막(Si3N4)으로 이루어짐을 특징으로 한다.Insulation and etching selectivity with metal wiring, low reflectance insulating film, can be formed at a temperature below 400 ℃, oxide film or nitride film (Si 3 N 4 ) deposited using PECVD (Plasma Enhanced Chemical Vapor Deposition) Characterized in that made.
본 발명의 바람직한 실시예에 따르면, 전술한 전자 이동(electromigration) 및Via 저항이 큰 문제점은 금속 배선간의 연결을 비아기둥(pillar)를 이용하여 해결하였으며, 비아기둥이 공정과정 중에 쓰러지는 문제는 비아기둥 지지 수단을 구비함으로써 해결하고, 금속막 상에서의 미세패턴 형성 기술의 문제점은 고반사율을 가진 금속막 대신 저반사율을 갖는 절연막 상에서 감광막 패턴형성이 이루어지도록 함과 아울러, 금속 식각 시 금속막과 선택비가 낮은 감광막 패턴 대신 식각 선택비가 상대적으로 높은 비아기둥 지지층을 마스킹 층으로 이용함으로써, 금속막 상에서 패턴(pattern) 형성문제를 개선한다.According to a preferred embodiment of the present invention, the above-mentioned problems of high electromigration and via resistance have been solved by using via pillars to connect the metal wires, and the problem of falling down during the via pillar processing is via via pillars. The problem of the micropattern forming technique on the metal film is solved by providing the supporting means, so that the photoresist pattern is formed on the insulating film having the low reflectance instead of the metal film having the high reflectance. By using a via pillar support layer having a relatively high etch selectivity instead of a low photoresist pattern as a masking layer, the problem of pattern formation on the metal film is improved.
이하, 본 발명의 바람직한 실시예를 첨부도면을 참조하여 보다 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따라 MOSFET소자를 이용한 2차 금속배선 제조공정까지 이루어진 실시예를 도 4(a)∼4(k)의 공정단면도를 참조하여 설명한다.An embodiment up to a secondary metal wiring manufacturing process using a MOSFET device according to the present invention will be described with reference to the process cross-sectional views of FIGS. 4 (a) to 4 (k).
도 4(a)를 참조하면, 종래의 제조 방법과 동일하게, Si 기판(1) 상에 격리 산화막(2-1)에 의해 소자의 활성영역을 분리하여 정의한 후, 소스-드레인 형성을 위한 n+층(2-3)와 게이트(2-2)를 형성하여 MOS 구조의 트랜지스터를 완성한다. 이어, 층간절연막(2-4)를 증착한 후, 상기 소스/드레인 영역(2-3)의 일부 표면이 노출되도록 상기 층간절연막(2-4)을 패터닝하여 콘택 홀(2-5)을 정의한다. 이어, 결과물 상에 상기 콘택 홀(contact hole)(2-5)이 충분히 채워질 수 있도록 1차 금속배선을 위한 1차 금속막(3)을 증착한다.Referring to FIG. 4A, the active region of the device is separated and defined on the Si substrate 1 by the isolation oxide film 2-1 on the Si substrate 1, and then n + for source-drain formation. The layer 2-3 and the gate 2-2 are formed to complete the transistor of the MOS structure. Subsequently, after the interlayer insulating layer 2-4 is deposited, the interlayer insulating layer 2-4 is patterned to expose a part of the surface of the source / drain region 2-3 to define the contact hole 2-5. do. Subsequently, a primary metal film 3 for primary metal wiring is deposited to sufficiently fill the contact holes 2-5 on the resultant.
이때, 상기 1차 금속막(3)은 다층 구조를 갖는 것이 보다 바람직하다. 예컨데, 맨 밑층으로부터 Ti/TiN, TiW, 및 MoSix 등의 고융점 금속물질 중에서 선택된 금속 장벽층(barrier metal), 그 위에 1차 전도층으로서 Al, 또는 Cu 등을 증착하고, 후속 공정에서의 기둥(pillar) 형성 시 식각 end-point 감지(detection)용으로 사용하기 위한 도전체층을 순차적으로 증착한다.At this time, it is more preferable that the primary metal film 3 has a multilayer structure. For example, a metal barrier metal selected from high melting point metal materials such as Ti / TiN, TiW, and MoSix is deposited from the bottom layer, Al, Cu, or the like as a primary conductive layer is deposited thereon, and the pillar in a subsequent process. During the formation of pillars, conductor layers are sequentially deposited for use in etching end-point detection.
도 4(b)를 참조하면, 금속 배선간의 연결을 위한 비아 기둥(pillar) 형성용 금속막(7a)을 증착한다. 상기 금속막(7a) 역시, 다층구조가 바람직하며, 예를 들면, Al으로 이루어진 하층과 TiN, TiW 또는 MoSix등과 같은 장벽금속(barrier metal)의 상층으로 이루어진 2중층을 사용한다.Referring to FIG. 4B, a metal film 7a for forming via pillars for connecting metal wires is deposited. The metal film 7a is also preferably a multi-layered structure. For example, a double layer made of a lower layer made of Al and an upper layer made of a barrier metal such as TiN, TiW or MoSi x is used.
도 4(c) 및 도 4(d)를 참조하면, 비아 기둥형상을 형성하기 위한 감광막 패턴(9)을 정의한 후, 이를 마스크로 이용한 건식 식각으로 상기 금속막(7a)을 식각하여비아 기둥(7)을 형성한다. 이어, 상기 감광막 패턴(9)을 제거한다.Referring to FIGS. 4C and 4D, after defining the photoresist pattern 9 for forming the via pillar shape, the metal layer 7a is etched by dry etching using the mask to form the via pillar ( 7) form. Next, the photoresist pattern 9 is removed.
도 4(e)를 참조하면, 1차 금속배선 형상을 형성시키기 전에 상기 비아 기둥(7)이 쓰러지는 문제점을 해결하기 위해, 바이기둥을 지지하기 위한 지지수단(8a)을 수십 에서 수백 nm 두께로 형성시킨다. 이때, 상기 비아기둥 지지수단(8a)은 금속 배선과의 절연성 및 식각 선택비가 크며, 반사율이 낮으며, PECVD(Plasma Enhanced Chemical Vapor Deposition) 방법으로 400℃ 이하의 온도에서 저온 증착이 가능하며, 스텝 커버리지가 좋은 특성을 갖는 질화막(Si3N4) 또는 산화막을 사용한다.Referring to FIG. 4 (e), in order to solve the problem of the via pillar 7 falling down before forming the primary metallization shape, the support means 8a for supporting the bi-pillars have a thickness of several tens to hundreds of nm. To form. At this time, the via pillar support means 8a has a high insulation and etching selectivity with metal wiring, low reflectivity, and can be deposited at a temperature of 400 ° C. or lower by PECVD (Plasma Enhanced Chemical Vapor Deposition) method. A nitride film (Si 3 N 4 ) or oxide film having good coverage characteristics is used.
이어서, 도 4(f) 내지 4(h)를 참조하여, 1차 금속배선 형상을 정의하는 마스크를 사용하여 상기 기둥 지지물(8a)과 상기 1차 금속막을 식각하여 1차 금속배선(3)을 형성함과 동시에 상기 비아기둥(7)의 양측벽을 둘러싸는 기둥 지지층(8)을 형성한다.Next, referring to FIGS. 4 (f) to 4 (h), the pillar support 8a and the primary metal film are etched using a mask defining a primary metal wiring shape to form the primary metal wiring 3. At the same time, the pillar support layer 8 surrounding both side walls of the via pillar 7 is formed.
구체적으로, 미세형상의 금속배선을 용이하게 형성시키기 위해, 도 4(f)에 도시한 바와 같이, 상기 비아기둥 지지물(8a)에 1차 금속 배선형상의 감광막 패턴(10)을 형성한다. 이어, 도 4(g)에 도시한 바와 같이, 상기 감광막 패턴(10)을 마스크로 이용하여 상기 비아기둥 지지용 절연막(8a)을 1차로 식각한 후, 감광막 패턴(10)을 제거한다. 이때, 감광막과 절연막간에는 식각 선택비가 10:1 이상 가질 수 있으므로 pillar 상단부에 얇게 형성된 감광막일 지라도 절연막 상에 금속배선을 형성시킬 때 마스킹 역활을 충분히 수행할 수 있다. 그 결과, 미세 형상의 금속배선을 용이하게 형성할 수 있다.Specifically, in order to easily form a fine metal wiring, as shown in FIG. 4 (f), a photosensitive film pattern 10 having a primary metal wiring shape is formed on the via pillar support 8a. Subsequently, as shown in FIG. 4G, the via pillar support insulating layer 8a is first etched using the photoresist pattern 10 as a mask, and then the photoresist pattern 10 is removed. In this case, since the etching selectivity may be greater than or equal to 10: 1 between the photoresist and the insulating layer, even when the photoresist is thinly formed on the upper end of the pillar, a masking role may be sufficiently performed when the metal wiring is formed on the insulating layer. As a result, fine metal wiring can be easily formed.
이어, 금속과의 식각선택비가 큰 비아기둥 지지물(8a)을 마스킹층으로 활용하여 2차 금속식각을 통하여 도 4(h)에 도시한 바와 같은 1차 금속배선(3)을 형성한다.이때, 상기 2차 금속 식각시, 상기 비아기둥(7) 상단부의 비아기둥 지지물(8a)이 대부분 함께 식각될 수 있도록 식각 선택비를 고려하여 비아기둥 지지물의 증착두께를 조절함으로써, 기둥 상단부의 단차없이 1차 금속배선(3)과 비아기둥 지지층(8)을 동시에 형성시킨다.Subsequently, the via metal support 8a having a large etching selectivity with the metal is used as a masking layer to form a primary metal wiring 3 as shown in FIG. 4 (h) through secondary metal etching. During the secondary metal etching, by adjusting the deposition thickness of the via pillar support in consideration of the etching selectivity so that the via pillar support 8a at the upper end of the via pillar 7 can be etched together, without any step 1 The primary metal wiring 3 and the via pillar support layer 8 are formed at the same time.
도 4(i)를 참조하면, 상기 결과물 상에 금속 배선간 절연막(inter-metal dielectric; IMD)(4)을 형성한다. 이때, 상기 금속 배선간 절연막(4)은 다층 구조로 형성하는 것이 바람직하다. 예를 들어, 상, 하층으로 400℃ 이하의 온도에서 증착 가능한 절연막을 사용하며, 이들 절연막 사이에 갭 채움(gap-filling)을 위한 SOG(Spin-On-Glass)막을 개재한다.Referring to FIG. 4 (i), an inter-metal dielectric (IMD) 4 is formed on the resultant. At this time, the inter-wire insulating film 4 is preferably formed in a multi-layer structure. For example, an insulating film that can be deposited at a temperature of 400 ° C. or lower as an upper and a lower layer is used, and an SOG (Spin-On-Glass) film for gap-filling is interposed therebetween.
이어, 도 4(j)에 도시한 바와 같이, 상기 공정을 통하여 증착된 금속 배선간 절연막(4)을 CMP(Chemical Mechanical Polishing) 공정을 이용하여 평탄화한다. 이때, 상기 비아 기둥(7)의 최상층, 예컨데, 장벽금속(barrier metal)을 연마 정지막으로 사용한다.Subsequently, as shown in FIG. 4 (j), the inter-wire insulating film 4 deposited through the above process is planarized by using a chemical mechanical polishing (CMP) process. At this time, an uppermost layer of the via pillar 7, for example, a barrier metal, is used as the polishing stop film.
최종적으로, 도 4(k)에 도시한 바와 같이, 2차 금속을 증착한 뒤, 2차 금속 미세 패턴 형성과 식각을 수행하여 2차 금속배선(6)을 형성시킨 후, 금속 접합(alloy) 공정을 실시하여 2차 금속배선 공정을 완성한다.Finally, as shown in FIG. 4 (k), after depositing the secondary metal, the secondary metal fine pattern is formed and etched to form the secondary metal wiring 6, and then metal joining is performed. The process is completed to complete the secondary metallization process.
이상 설명한 바와 같이 본 발명에 의하면, 종래의 제조방법에서 문제점으로 부각된 전자이동(electromigration) 문제나, Via 저항이 큰 문제점들은 금속층간의 연결을 비아기둥(pillar)를 이용하여 해결하고 있을 뿐만아니라 비아기둥 지지층을 형성하는 방법을 고안하여 비아기둥이 공정과정중에 쓰러지는 치명적인 문제점을 해결할 수 있다. 더욱이, 금속 식각시 금속막과 선택비가 높은 비아기둥 지지층(절연막)을 마스킹층으로 적용하는 공정방법을 고안하여 미세패턴 형성이 용이한 얇은 감광막을 적용할 수 있게 함으로서, 감광막을 마스킹층으로 적용했던 종래의 공정방법에서 나타난 상대적으로 두꺼운 감광막에 미세패턴을 형성해야 하는 미새패턴 형성의 문제점을 개선하였다. 아울러, 1차 금속패턴 형성도 미세패턴 형성이 어려운 고반사율을 가진 금속막상이 아닌 저반사율의 비아기둥 지지층(절연막)상에서 이루어지도록 고안함으로써, 공정 여유도를 상대적으로 향상시킬 수 있다.As described above, according to the present invention, electromigration problems and problems with large via resistance, which are highlighted as problems in the conventional manufacturing method, are not only solved by using pillars to connect the metal layers. By devising a method for forming a via pillar support layer, a fatal problem of falling down during the via pillar processing can be solved. Furthermore, by devising a process method of applying a metal film and a highly selective via-column support layer (insulation film) as a masking layer during metal etching, a thin photoresist film, which is easy to form a fine pattern, can be applied. Improved the problem of the formation of the fine pattern to form a fine pattern on the relatively thick photosensitive film shown in the conventional process method. In addition, by forming the primary metal pattern to be formed on the via pillar support layer (insulation film) having a low reflectance rather than a metal film having a high reflectance, which is difficult to form a fine pattern, the process margin can be relatively improved.
결과적으로, 본 발명은 플러그(plug) 형성을 위한 추가적인 장비의 적용없이 초고집적 소자에 적용이 가능하고, 소자의 수율향상을 도모할 수 있을 뿐만아니라 미세패턴 형성기술의 공정 여유도를 증가시킬 수 있는 다층금속 배선 방법을 제공한다.As a result, the present invention can be applied to an ultra-high density device without applying additional equipment for forming a plug, and can improve the yield of the device as well as increase the process margin of the fine pattern forming technology. It provides a multi-layer metal wiring method.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100398046B1 (en) * | 2001-08-08 | 2003-09-19 | 한국전자통신연구원 | Method of forming a metal wiring in a semiconductor device |
| KR100430680B1 (en) * | 2001-06-30 | 2004-05-10 | 주식회사 하이닉스반도체 | A metal line of semiconductor device and A method for forming of the same |
| KR100906059B1 (en) * | 2007-11-05 | 2009-07-03 | 주식회사 동부하이텍 | Method for fabricating the mtcmos cell |
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1997
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100430680B1 (en) * | 2001-06-30 | 2004-05-10 | 주식회사 하이닉스반도체 | A metal line of semiconductor device and A method for forming of the same |
| KR100398046B1 (en) * | 2001-08-08 | 2003-09-19 | 한국전자통신연구원 | Method of forming a metal wiring in a semiconductor device |
| KR100906059B1 (en) * | 2007-11-05 | 2009-07-03 | 주식회사 동부하이텍 | Method for fabricating the mtcmos cell |
| US7884424B2 (en) | 2007-11-05 | 2011-02-08 | Dongbu Hitek Co., Ltd. | Structure of MTCMOS cell |
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