KR19990043011A - Lead frame manufacturing method - Google Patents
Lead frame manufacturing method Download PDFInfo
- Publication number
- KR19990043011A KR19990043011A KR1019970063975A KR19970063975A KR19990043011A KR 19990043011 A KR19990043011 A KR 19990043011A KR 1019970063975 A KR1019970063975 A KR 1019970063975A KR 19970063975 A KR19970063975 A KR 19970063975A KR 19990043011 A KR19990043011 A KR 19990043011A
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- lead frame
- barrier
- semi
- lead
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims abstract description 24
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 238000005554 pickling Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
리드프레임 제조방법이 개시된다. 개시된 리드프레임 제조방법은, 리드프레임 소재에 감광층을 형성하는 제1단계와, 상기 감광층을 노광, 현상하여 소정 패턴을 형성하며, 상기 리드프레임 소재에서 반에칭이 실시될 부위에 균일한 깊이로 에칭이 이루어질 수 있도록 에칭액의 흐름을 방해하는 배리어를 형성하는 제2단계와, 상기 배리어가 부위에 에칭액을 공급하여 반에칭하는 제3단계를 포함한다.A method for manufacturing a leadframe is disclosed. The disclosed leadframe manufacturing method includes a first step of forming a photosensitive layer on a leadframe material, and exposing and developing the photosensitive layer to form a predetermined pattern, and having a uniform depth at a portion where the semi-etching is to be performed in the leadframe material. And a third step of forming a barrier that prevents the flow of the etchant so that the etching can be performed, and a third step of supplying the etchant to the portion and semi-etching the barrier.
Description
본 발명은 리드프레임 제조방법에 관한 것으로서, 상세하게는 리드프레임 제조과정중 에칭공정이 개선된 리드프레임 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a lead frame, and more particularly, to a method of manufacturing a lead frame in which an etching process is improved during a lead frame manufacturing process.
일반적으로 반도체 장치에 사용되는 리드프레임은 반도체 패키지의 핵심 구성 재료의 하나로서, 반도체 패키지의 내부와 외부를 연결해 주는 도선(lead) 역할과, 반도체 칩을 지지해 주는 지지대 역할을 하는 것이다. 이러한 리드프레임은 반도체 패키지의 종류에 따라 여러 가지 형상으로 제작될 수 있다. 예를 들어, 도 1 및 도 2는 반도체 패키지를 각각 도시한 단면도로서, 도면에 도시된 바와 같이 반도체 패키지의 종류에 따라 이용되는 리드프레임은 구조적으로 다른 형상을 가진다. 이를 상세히 설명하면 다음과 같다.In general, a lead frame used in a semiconductor device is one of the core constituent materials of a semiconductor package, and serves as a lead connecting the inside and the outside of the semiconductor package and a support for supporting the semiconductor chip. The lead frame may be manufactured in various shapes according to the type of semiconductor package. For example, FIGS. 1 and 2 are cross-sectional views illustrating semiconductor packages, respectively, and the lead frames used according to the types of semiconductor packages have structurally different shapes as shown in the drawings. This will be described in detail as follows.
우선, 도 1에 도시된 바와 같은 반도체 패키지(10)에 이용되는 리드프레임은 반도체칩(11)이 탑재되는 패드부(12)와 반도체칩(11)과 와이어본딩되는 내부리드부(13) 및 외부와의 전기적 신호를 전달하기 위하여 내부리드부(13)로부터 연장되어 형성된 외부리드부(14)를 포함한다. 반면, 도 2에 도시된 바와 같은 반도체 패키지(20)는 도 1의 반도체패키지(10)에 비해 실장밀도가 증가된 형태로서, 이에 이용되는 리드프레임은 반도체칩(21)이 탑재되어 와이어본딩되는 리드부(22)와, 외부와 전기적 신호를 전달하기 위해 리드부(22)에 형성된 범프(23)를 포함한다. 도 3은 이러한 리드프레임의 일 예로서 예컨대, 씨에스피(CSP : Chip Scale Package) 패키지에 이용되는 리드프레임을 도시한 평면도이다. 도면에 도시된 바와 같이, 이 리드프레임은 소정 형상의 복수개의 리드부(31)와, 이 리드부(31)의 일단에 돌출 형성된 범프(32)를 포함하여 이루어진다. 통상적으로 이러한 리드프레임은 리드프레임의 소재인 기판에 감광층(PR; Photo resistor)을 형성한 후 노광 및 현상 공정을 거친 다음 에칭하여 소정 패턴의 형상으로 성형하는 에칭방법에 의해 제조된다.First, the lead frame used for the semiconductor package 10 as shown in FIG. 1 includes a pad part 12 on which the semiconductor chip 11 is mounted, an internal lead part 13 wire-bonded with the semiconductor chip 11, and It includes an outer lead portion 14 formed to extend from the inner lead portion 13 to transmit an electrical signal to the outside. On the other hand, the semiconductor package 20 as shown in FIG. 2 is a form in which the mounting density is increased compared to the semiconductor package 10 of FIG. 1, and the lead frame used therein is a semiconductor chip 21 mounted with wire bonding. The lead portion 22 and a bump 23 formed in the lead portion 22 to transmit an electrical signal to the outside. FIG. 3 is a plan view illustrating a lead frame used in, for example, a chip scale package (CSP) package as an example of such a lead frame. As shown in the figure, the lead frame includes a plurality of lead portions 31 having a predetermined shape and bumps 32 protruding from one end of the lead portion 31. Typically, such a lead frame is manufactured by an etching method of forming a photoresist layer (PR) on a substrate, which is a material of the lead frame, followed by an exposure and development process, followed by etching to form a predetermined pattern.
그리고, 상술한 바와 같은 리드프레임의 제조과정은 통상적으로 리드프레임의 소정 부위에 대해서 특수한 목적을 위하여 실시하는 반에칭공정이 포함된다. 예를 들어, 도 1에 도시된 바와 같은 리드프레임에서 패드부(12)에 딤플(dimple)이나 그루브(groove)를 형성할 경우 또는 도 4는 도 3의 Ⅳ-Ⅳ선의 단면도로서, 리드부(31)로부터 소정 높이로 돌출되게 범프(32)를 형성하기 위해서 반에칭이 실시된다. 하지만, 종래의 기술에서는 이러한 반에칭공정을 실시할 때, 에칭되는 깊이가 균일하게 형성되지 않는다는 문제점이 있었다. 특히 이러한 문제점으로 인해, 반도체패키지가 경박단소화됨에 따라 리드프레임은 직접화된 하이핀 리드프레임으로 제작되어야 하나, 이러한 하이핀 리드프레임에서는 리드가 미세한 폭으로 형성되기 때문에 정확한 반에칭공정이 실시되지 못할 경우 제품의 신뢰성이 나빠진다는 문제점이 있다.In addition, the manufacturing process of the lead frame as described above typically includes a semi-etching process for a specific purpose for a predetermined portion of the lead frame. For example, when dimples or grooves are formed in the pad part 12 in the lead frame as shown in FIG. 1 or FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. Semi-etching is carried out to form the bumps 32 to protrude from the height 31. However, in the prior art, there is a problem that the depth to be etched is not formed uniformly when such a semi-etching process is performed. In particular, due to this problem, as the semiconductor package is thin and short, the lead frame should be made of a direct high pin lead frame. However, in this high pin lead frame, the lead is formed to have a small width so that an accurate anti-etching process is not performed. If not, there is a problem that the reliability of the product worsens.
본 발명은 상기와 같은 문제점을 감안하여 창출된 것으로서, 반도체 패키지에 이용되는 리드프레임의 제조시 리드프레임 소재의 소정 부위에 균일하게 반에칭을 실시할 수 있도록 개선된 리드프레임 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides an improved leadframe manufacturing method capable of uniformly semi-etching a predetermined portion of a leadframe material during manufacture of a leadframe used in a semiconductor package. There is a purpose.
도 1 및 도 2는 반도체 패키지를 도시한 단면도,1 and 2 are cross-sectional views showing a semiconductor package;
도 3은 도 2의 반도체 패키지에 이용되는 리드프레임의 일예를 도시한 평면도,3 is a plan view illustrating an example of a lead frame used in the semiconductor package of FIG. 2;
도 4는 도 3의 Ⅳ-Ⅳ선의 단면도,4 is a cross-sectional view taken along the line IV-IV of FIG. 3;
도 5는 본 발명에 따른 리드프레임 제조방법 일 실시예를 도시한 공정흐름도,Figure 5 is a process flow diagram showing an embodiment of a lead frame manufacturing method according to the present invention,
도 6 내지 도 10은 본 발명에 따른 리드프레임 제조방법에 적용되는 배리어의 몇가지 실시예를 도시한 도면,6 to 10 are views showing some embodiments of a barrier applied to the lead frame manufacturing method according to the present invention,
그리고, 도 11 및 도 13은 본 발명에 따른 리드프레임 제조방법에 적용되는 패턴의 형상을 도시한 도면이다.11 and 13 illustrate the shape of a pattern applied to the method of manufacturing a lead frame according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of Symbols for Main Parts of Drawings>
11,21.반도체 칩 12.패드Semiconductor chip 12.Pad
13.내부리드 14.외부리드13.Inner Lead 14.Outer Lead
22,31.리드부 13,32.범프22,31 Leads 13,32.Bumps
61,71,81,91.장애물61,71,81,91 obstacles
상기와 같은 목적을 달성하기 위해 본 발명인 리드프레임 제조방법은, 리드프레임 소재에 감광층을 형성하는 제1단계와, 상기 감광층을 노광, 현상하여 소정 패턴을 형성하며, 상기 리드프레임 소재에서 반에칭이 실시될 부위에 균일한 깊이로 에칭이 이루어질 수 있도록 에칭액의 흐름을 방해하는 배리어를 형성하는 제2단계와, 상기 배리어가 부위에 에칭액을 공급하여 반에칭하는 제3단계를 포함한다.In order to achieve the above object, a method of manufacturing a lead frame according to the present invention includes a first step of forming a photosensitive layer on a lead frame material, and exposing and developing the photosensitive layer to form a predetermined pattern, which is half of the lead frame material. And a second step of forming a barrier that prevents the flow of the etching solution so that the etching can be performed at a uniform depth on the site to be etched, and the third step of supplying the etching solution to the site by half etching.
본 발명에 있어서, 상기 배리어는 에칭액의 속도를 감소시키고 균일한 흐름이 되도록 소정 형상의 장애물이 복수개 배열된 것이며, 상기 제2단계에서 에칭액이 집중되는 굴절부위나 교차부위에 형성된 패턴은 본래의 형상보다 소정 폭 넓게 형성하며, 반에칭이 실시되는 부위에 형성된 패턴 중 반에칭이 실시되는 경계면 부위는 반에칭이 실시되는 부위쪽으로 소정 폭 넓게 형성하는 것을 특징으로 한다.In the present invention, the barrier is a plurality of obstacles of a predetermined shape are arranged so as to reduce the speed of the etching solution and to ensure a uniform flow, the pattern formed at the refraction portion or the intersection portion where the etching solution is concentrated in the second step is the original shape It is formed to a predetermined width wider, and the interface portion where the semi-etching is performed among the patterns formed on the portion where the half etching is performed is characterized in that the predetermined width is formed toward the portion where the half etching is performed.
이하 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 5는 본 발명에 따른 리드프레임 제조방법의 일 실시예를 도시한 공정흐름도이다.5 is a process flow diagram showing an embodiment of a lead frame manufacturing method according to the present invention.
우선, 리드프레임 소재에 대하여 예컨대, 탈지나 산세처리 등 통상적인 소재 전처리를 실시하여 리드프레임 소재의 표면을 활성화시킨다(51). 이어서, 소재 전처리가 실시된 리드프레임 소재의 표면에 광조사에 의해 감광부분이 현상액에 녹거나 녹지 않게 되는 감광층(PR; Photo resistor)을 형성시킨다(52). 이어서, 소정 패턴을 가지는 마스크를 통하여 소정 광을 조사하여 마스크의 패턴을 감광층 상에 노광시키며, 현상공정을 거쳐서 감광층 상에 리드프레임의 형상에 대응하는 소정 패턴을 형성시킨다. 이때, 리드프레임 소재에서 반에칭이 실시될 부위에는 균일한 깊이로 에칭이 이루어질 수 있도록 에칭액의 흐름을 방해하는 배리어를 형성한다. 이러한 배리어는 에칭액의 속도를 감소시키고 균일한 흐름이 되도록 소정 형상의 장애물이 복수개 배열된 것으로, 도 6 내지 도 9에 배리어의 몇가지 실시예를 도시해 보였다.First, the lead frame material is subjected to normal material pretreatment such as degreasing or pickling to activate the surface of the lead frame material (51). Subsequently, a photoresist layer (PR; Photo resistor) is formed on the surface of the lead frame material subjected to the material pretreatment so that the photosensitive portion is not dissolved or dissolved in the developer by light irradiation (52). Subsequently, predetermined light is irradiated through a mask having a predetermined pattern to expose the pattern of the mask on the photosensitive layer, and a predetermined pattern corresponding to the shape of the lead frame is formed on the photosensitive layer through a developing process. In this case, a barrier is formed on the portion of the lead frame material to be etched to prevent the flow of the etching solution so that etching can be performed at a uniform depth. Such a barrier has a plurality of obstacles of a predetermined shape arranged so as to reduce the velocity of the etching solution and achieve a uniform flow. Some embodiments of the barrier are illustrated in FIGS. 6 to 9.
우선, 도 6내지 도 7에 도시된 바와 같이, 상술한 배리어는 소정 직경을 가지는 원형의 장애물(61)(71)이 리드프레임 소재에서 반에칭이 실시될 부위에 복수개 형성된다. 이러한 장애물(61)(71)은 감광층으로 형성되며, 그 형상은 원형뿐만 아니라 타원형 또는 삼각형, 사각형 등 다각형으로 형성될 수 있으며, 소정 간격 이격된 형태로 다양하게 배치될 수 있다. 그리고, 도 8 내지 도 9에 도시된 바와 같이, 배리어는 소정 폭으로 형성된 격벽 형태의 장애물((81)(91)로 에칭액의 흐름방향 또는 에칭액의 흐름방향에 대하여 수직한 방향 및 소정 각도로 다양하게 형성될 수 있다. 상술한 바와 같은 배리어의 역할은 리드프레임 소재의 반에칭 부위에 에칭액을 적용될 때 장애물에 의해 에칭액의 속도가 줄어들게 되며, 흐름을 균일하게 유지시켜서 균일한 깊이로 에칭이 실시될 수 있도록 한다.First, as shown in FIG. 6 to FIG. 7, in the above-described barrier, a plurality of circular obstacles 61 and 71 having a predetermined diameter are formed in a portion where semi-etching is to be performed in the lead frame material. The obstacles 61 and 71 may be formed of a photosensitive layer, and the shape of the obstacles 61 and 71 may be formed in a polygonal shape such as an oval or a triangle or a square as well as a circular shape. 8 to 9, the barriers are barrier rib-shaped obstacles 81 and 91 formed in a predetermined width in a direction perpendicular to the flow direction of the etchant or a predetermined angle with respect to the flow direction of the etchant. The role of the barrier as described above is to reduce the velocity of the etchant by obstacles when the etchant is applied to the semi-etched portion of the leadframe material, and to maintain the flow uniformly so that the etching can be performed at a uniform depth. To help.
또한, 도 3에 도시된 바와 같이 리드프레임을 제조시는 리드프레임 소재의 양면에 대하여 동시에 에칭이 실시되는데, 그 일측면에 대하여는 리드부(31)의 형상을 형성하기 위해서 리드프레임 소재를 관통하여 에칭이 이루어지며, 타측면은 반에칭이 이루어져서 리드부(31)로부터 돌출되게 범프(32)가 형성되게 된다. 이때, 리드부(31)로부터 범프(32)를 형성하기 위해서 반에칭을 실시할 때, 소재 두께의 60% 이상을 반에칭할 때는 도 및 도 에 도시된 바와 같이 리드부(31) 사이에 소정 형상의 배리어(110)만을 형성시킬 수 있다. 상술한 바와 같은 배리어는 에칭되는 과정에서 서서히 제거되게 된다.In addition, as shown in FIG. 3, when the lead frame is manufactured, etching is simultaneously performed on both surfaces of the lead frame material, and one side thereof penetrates the lead frame material to form a shape of the lead part 31. Etching is performed, and the other side is semi-etched so that the bump 32 is formed to protrude from the lead portion 31. At this time, when the semi-etching is performed to form the bumps 32 from the lead portion 31, when half-etching at least 60% of the thickness of the material, a predetermined distance between the lead portions 31 as shown in FIGS. Only the barrier 110 having a shape may be formed. The barrier as described above is gradually removed during the etching process.
그리고, 감광층에 소정 패턴을 형성시 도 11 내지 도 12에 도시된 바와 같이 에칭액이 집중되는 굴절부위나 교차부위에 형성된 패턴은 본래의 폭 A보다 소정 폭B만큼 넓게 형성한다. 통상적으로 리드프레임 소재에 대하여 굴절되거나 교차되는 형상으로 에칭을 실시하는 과정에서는 굴절부위나 교차부위에 에칭액이 집중되어 원래의 형상보다 과도하게 에칭이 실시되게 된다. 따라서, 이러한 에칭이 실시되는 부위에 형성된 패턴을 제작시 과도하게 에칭되는 양만큼 보정하여 소정 폭 B만큼 넓게 패턴을 형성한다.When forming a predetermined pattern on the photosensitive layer, as shown in FIGS. 11 to 12, the pattern formed at the refraction portion or the intersection portion where the etching solution is concentrated is formed to be wider by the predetermined width B than the original width A. In general, in the process of etching the lead frame material in a shape that is refracted or intersected, the etching solution is concentrated at the refraction or intersection part, and the etching is performed excessively than the original shape. Therefore, the pattern formed on the site where such etching is performed is corrected by the amount that is excessively etched during fabrication to form the pattern as wide as the predetermined width B.
또한, 감광층에 소정 패턴을 형성시 도 13에 도시된 바와 같이, 반에칭이 실시되는 부위(130)에 형성된 패턴 중 반에칭이 실시되는 경계면 부위는 반에칭이 실시되는 부위(130)쪽으로 원래의 폭 A 보다 소정 폭 B 만큼 넓게 형성한다. 예를 들어 도 4에 도시된 바와 같이 리드부(31) 일단에 범프(32)를 형성하기 위해서 반에칭을 실시할 때와 같이, 반에칭을 실시할 때 범프(32)의 일측면이 지속적으로 에칭액에 접촉되며, 에칭액의 흐름이 막히는 부위이므로 그만큼 과도하게 에칭이 이루어지게 된다. 따라서, 범프(31)를 형성하기 위해 반에칭을 실시할 때 과도하게 에칭되는 양만큼 보상할 수 있도록 원래의 범프의 형상보다 소정 폭 B 만큼 크게 형성시킨다(53).In addition, when forming a predetermined pattern on the photosensitive layer, as shown in FIG. 13, the interface portion where the half etching is performed among the patterns formed on the portion 130 where the half etching is performed is originally directed toward the portion 130 where the half etching is performed. It is formed to be wider by a predetermined width B than the width A of. For example, as shown in FIG. 4, one side of the bump 32 continuously remains when half etching is performed, such as when half etching is performed to form the bumps 32 at one end of the lead portion 31. In contact with the etching solution, since the flow of the etching solution is blocked, the etching is excessively performed. Thus, 53 is formed to be larger than the shape of the original bump by a predetermined width B so as to compensate for the amount etched excessively when half etching is performed to form the bump 31 (53).
그리고, 상술한 바와 같이 반에칭 부위에 배리어가 형성되며, 과도하게 에칭되는 부위가 보정된 패턴이 형성된 리드프레임 소재에 대해 통상적인 에칭, 반에칭 공정을 통해 리드프레임 형상을 제작한다(54).As described above, a lead frame shape is formed through a conventional etching and semi-etching process on a lead frame material having a barrier formed on the semi-etched portion and a pattern on which an excessively etched portion is corrected.
그리고, 에칭이 실시된 리드프레임 소재로부터 소정 패턴으로 형성된 감광층을 박리하며, 에칭 후처리를 통하여 리드프레임 제조공정이 완료된다(55).Then, the photosensitive layer formed in a predetermined pattern is peeled from the lead frame material subjected to the etching, and the lead frame manufacturing process is completed through the post-etching treatment (55).
본 발명에 따른 리드프레임 제조방법은, 리드프레임 소재에서 반에칭이 실시될 부위에 에칭액의 속도를 감소시키고 균일한 흐름이 되도록 소정 형상의 배리어를 형성한 상태로 반에칭을 실시함으로써, 에칭되는 깊이를 균일하게 유지시킬 수 있다는 장점이 있다. 또한, 에칭액이 집중되는 굴절부위나 교차부위에 형성된 패턴 및 반에칭이 실시되는 경계면 부위에 형성된 패턴을 소정 폭만큼 보정한 후 에칭함으로써, 정확한 규격으로 에칭이 이루어져서 제품의 신뢰성이 향상된다는 장점이 있다.The method for manufacturing a lead frame according to the present invention includes a depth of etching by performing a half etching in a state in which a barrier having a predetermined shape is formed to reduce the speed of the etching solution in the lead frame material to be subjected to the half etching and to achieve a uniform flow. There is an advantage that can be kept uniform. In addition, by correcting the pattern formed at the refractive or concentrated region where the etching solution is concentrated and the pattern formed at the interface portion where the semi-etching is performed by a predetermined width, the etching is performed to an accurate specification, thereby improving the reliability of the product. .
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970063975A KR100269235B1 (en) | 1997-11-28 | 1997-11-28 | Method of lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970063975A KR100269235B1 (en) | 1997-11-28 | 1997-11-28 | Method of lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990043011A true KR19990043011A (en) | 1999-06-15 |
| KR100269235B1 KR100269235B1 (en) | 2000-10-16 |
Family
ID=19525893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019970063975A KR100269235B1 (en) | 1997-11-28 | 1997-11-28 | Method of lead frame |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100269235B1 (en) |
-
1997
- 1997-11-28 KR KR1019970063975A patent/KR100269235B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR100269235B1 (en) | 2000-10-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6699782B2 (en) | Method of fabricating a wafer level package | |
| JP2803987B2 (en) | Method for manufacturing semiconductor chip bump | |
| KR950004464A (en) | Manufacturing method of chip bump | |
| US8426254B2 (en) | Leadless semiconductor package with routable leads, and method of manufacture | |
| KR100269235B1 (en) | Method of lead frame | |
| KR950034696A (en) | Ultra-thin semiconductor package and manufacturing method thereof | |
| KR101064754B1 (en) | Manufacturing method of Board of chip and Board of chip using the same | |
| KR100734250B1 (en) | Bonding pad of semiconductor memory device for improving adhesive strength bonding pad and bonding wire and method of manufacturing the same | |
| KR100246585B1 (en) | B.g.a semiconductor lead frame and fabrication method of it | |
| KR100384706B1 (en) | Metrod for manufacturing readframe | |
| KR960002693Y1 (en) | Photo etching mask | |
| KR960006959B1 (en) | Mask plate for photoetching process | |
| KR20050036464A (en) | Method for forming bump on wafer and semiconductor package with bump formed thereby | |
| JP3449047B2 (en) | Lead frame structure | |
| JPH02158160A (en) | Manufacture of lead frame | |
| KR19980030400A (en) | Bump formation method to remove the bonding pad of the abnormal bump | |
| KR200169007Y1 (en) | Apparatus over etching prevention of lead frame | |
| KR970000961B1 (en) | Fabricating method of semiconductor device | |
| KR0121882Y1 (en) | Photoetching disk for a lead frame manufacturing | |
| KR200200909Y1 (en) | Photo Etching Plate Structure For Forming The Lead Frame | |
| KR0179020B1 (en) | Confining method of metal interconnector in contact | |
| JPH0644550B2 (en) | Method for manufacturing semiconductor device | |
| JPH02246218A (en) | Manufacture of semiconductor device | |
| JPS5824020B2 (en) | semiconductor equipment | |
| KR20090054625A (en) | Method for fabricating semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20130703 Year of fee payment: 14 |
|
| FPAY | Annual fee payment |
Payment date: 20140709 Year of fee payment: 15 |
|
| FPAY | Annual fee payment |
Payment date: 20150701 Year of fee payment: 16 |
|
| FPAY | Annual fee payment |
Payment date: 20160701 Year of fee payment: 17 |
|
| FPAY | Annual fee payment |
Payment date: 20170703 Year of fee payment: 18 |
|
| EXPY | Expiration of term |