KR19990041751A - Trimming circuit for sequential fusing - Google Patents

Abstract

The present invention relates to a trimming circuit that performs sequential fusing to increase the accuracy of trimming by performing trimming sequentially and to reduce the circuit design area by reducing the instantaneous current of the voltage source applied to the fuse. The trimming circuit for fusing includes n fuse sections each having first and second input signal terminals and one selection input terminal, n first shift register sections for serially transmitting a serial data input signal in accordance with a clock signal, and the fuse unit. N second shift register sections for serially transmitting signals of the second input signal terminal using the signal of the first input signal terminal of the woods as a clock signal, and output values of the registers of the first and second shift registers N to receive the output of each register of the second shift register section and logically multiply to select the fuse section sequentially. And an digital gate and an analog / digital converter for converting and outputting the digital output values of the n fuse portions to analog current values.

Description

Trimming circuit for sequential fusing

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trimming circuit of a semiconductor circuit, and more particularly, to a trimming circuit that performs sequential fusing to sequentially trim to increase the accuracy of trimming and to reduce the instantaneous current of a voltage source applied to the fuse.

In general, when designing a semiconductor circuit, there is a need for a method for compensating for various variables in a process, that is, a threshold voltage of a transistor, and a variation of a resistor and a capacitor, which are passive elements implemented on a circuit. There is a circuit that compensates for the desired characteristics.

A conventional trimming circuit will be described with reference to the accompanying drawings.

1 is a block diagram of a conventional trimming circuit for fusing.

Conventional trimming circuits for compensating for various variables when designing a semiconductor circuit include first, second, and third serially receiving serial data as serial inputs when a clock rises as shown in FIG. Selects whether to operate by receiving the fourth D flip-flop (F / F) (1, 2, 3, 4) and the output signal of each flip-flop, and receives the VPGM and PGM signals as inputs. 1), 2nd, 3rd, and 4th fuses 5, 6, 7, and 8 outputted to the < RTI ID = 0.0 >), < / RTI > It consists of an analog converter 9. Here, the first, second, third, and fourth D flip-flops (1, 2, 3, and 4) output a signal of serial data (SIN) when the first D flip-flop (1) is a rising edge of the clock. The output signal of the first D flip-flop 1 is inputted to the second D flip-flop 2 when the clock reaches the rising edge again. Then, when the clock becomes the rising edge again, the output of the second D flip-flop 2 is input to the third D flip-flop 3, and when the clock reaches the rising edge, the third D flip-flop 3 Is a 4-bit shift register input to the fourth D flip-flop 4.

The first, second, third, and fourth fuse units 5, 6, 7, and 8 receive an output signal of each of the four D flip-flops constituting the four-bit shift register and select whether to operate the same. When the operation is selected, the digital signal is output to the digital / analog converter 9 according to the signals of the PGM and the VPGM, respectively.

The digital / analog converter 9 receives the digital signals of the first, second, third, and fourth fuse parts 5, 6, 7, and 8 as inputs, and the 4 according to the current difference between the output terminal p and the output terminal n. Generate an output current proportional to the digital input of the bit.

An operation of a conventional trimming circuit configured as described above will be described with reference to the drawings.

2 is a diagram illustrating an operation timing diagram of a conventional trimming circuit.

As shown in FIG. 2, when the PGM is 'high' and the clock SCLK is at the rising edge, the serial data SIN is applied to the first D flip-flop 1 and the first D flip-flop 1 is turned on. The output is connected to the second D flip-flop 2 and appears as the output of the second D flip-flop 2 when the next clock SCLK is rising edge. In this manner, when the clock reaches the fourth rising edge, the first serial data SIN is transmitted to the fourth D flip-flop 4, thereby completing the data input. Each output of the 4-bit shift register is then passed to the first, second, third, and fourth fuse portions 5, 6, 7, and 8 having a fuse.

If the PGM is 'high' and the VPGM is 'high' and the output of each bit of the 4-bit shift register is 'high', the fuse in each fuse section is cut off, and if the output of each bit is 'low' Do not break fuses. The fuse is usually implemented in polysilicon and is grounded to show 'low' as the output. When the fuse is cut off by applying voltage to the VPGM, the fuse unit outputs 'high'. As such, in order to output 'high' from the fuse unit, a voltage source having a large current capacity is required.

This fuse section data enters the digital input of the digital / analog converter 9, which generates an output current proportional to the digital input according to the current difference between the p output terminal and the n output terminal. The output current is applied to the semiconductor circuit to compensate for process variables.

The conventional trimming circuit as described above has the following problems.

In order to cut the fuse and output 'high' to the fuse section, a voltage must be applied to the VPGM to generate a current to cut the fuse. Therefore, when the shift register has a plurality of bit structures, a voltage source having a large current capacity is required to cut off the fuse, and the VPGM of the circuit must be wired wide so that this current can flow, thereby increasing the area occupied by the circuit design.

The present invention is to solve the above problems, in particular, by performing the sequential trimming to increase the accuracy of trimming, reducing the instantaneous current of the voltage source applied to the fuse sequential fusing to reduce the area when designing the circuit The purpose is to provide a trimming circuit.

1 is a block diagram of a conventional trimming circuit for fusing

2 is a conventional timing diagram according to FIG.

Figure 3 is a block diagram of a trimming circuit for sequential fusing of the present invention

4 is a timing diagram according to the present invention of FIG.

5 is a table illustrating an operation of the fuse of FIG. 3.

FIG. 6 is a table showing data of a digital / analog converter shown in FIG.

Explanation of symbols for the main parts of the drawings

21 to 28: first to eighth flip-flops 29 to 32: first to fourth end gates

33 to 36: first to fourth fuse portions 37: digital / analog converter

In order to achieve the above object, a sequential fusing trimming circuit of the present invention includes n fuse sections each having first and second input signal terminals and one selection input terminal, and serial transmission of serial data input signals according to a clock signal. N first shift registers, n second shift registers for serially transmitting a signal of a second input signal terminal using a signal of the first input signal terminal of the fuse unit as a clock signal, and the first, N output gates of the second shift register unit as two inputs, the outputs of the registers of the second shift register unit are logically multiplied, and the n and gates sequentially select the fuse unit, and the digital output values of the n fuse unit. It is characterized in that it comprises a digital / analog converter for converting the output to an analog current value.

A trimming circuit for sequential fusing of the present invention will be described with reference to the accompanying drawings.

Figure 3 is a block diagram of a trimming circuit for sequential fusing of the present invention.

In the trimming circuit for sequential fusing according to the present invention, as shown in FIG. 3, the first, second, third, and fourth D flip-flops that receive the PGM signal as an initial input and transmit the serial signal when the VPGM signal has a rising edge ( 21, 22, 23, 24, and the fifth, sixth, seventh, seventh, seventh, seventh, seventh, seventh, seventh, seventh, seventh, seventh and seventh exemplary embodiments. First and second gates 25 and 26, and the first AND gate 29 and the second and the second and the second output flip-flops 25, 26, 27 and 28 and the first and fifth D flip-flops 21 and 25 as two inputs. A second AND gate 30 outputting the logical AND of the sixth D flip-flops 22 and 26 as two inputs, and an output logical AND of the second AND gate 30 and the third and seventh D flip-flops 23 and 27 as two inputs. A fourth AND gate 32 for outputting the AND of the third AND gate 31 and the fourth and eighth D flip-flops 24 and 28 as two inputs, and the first AND gates 32 and 28 respectively. 4 End First, second, third, and fourth fuse sections 33, 34, wherein the operation is selected according to the signals of the dates 29, 30, 31, and 32, and the fusing is determined by receiving the PGM and VPGM signals. And digital input according to the current difference between the p output terminal and the n output terminal by receiving the digital output signals of the 35 output circuits (35,36) and the first, second, third, and fourth fuse parts (33, 34, 35, 36). It consists of a digital / analog converter 37 for generating an output current proportional to.

The fifth, sixth, seventh, and eighth D flip-flops 25, 26, 27, and 28 are shift registers for latching a digital signal to be applied to the digital-to-analog converter 37. The second, third, and fourth D flip-flops 21, 22, 23, and 24 are latched according to the value of the VPGM, which is a voltage source for breaking the fuse, and represent sequential output values such as E1, E2, E3, and E4. As such, the first, second, third, and fourth D flip-flops 21, 22, 23, and 24 may use the first, second, third, and fourth fuse parts 33, 34, 35, and 36. Shift register to select sequentially.

Referring to the operation of the trimming circuit for the sequential fusing operation of the present invention having the configuration as described above is as follows.

4 is a diagram illustrating the timing diagram of FIG. 3, FIG. 5 is a table illustrating the operation of the fuse unit of FIG. 3, and FIG. 6 is a table illustrating data of the digital / analog converter.

Before explaining the operation of the present invention will be described with reference to the operation of the fuse of the components of the present invention as follows.

The fuse of the fuse part of the present invention is composed of polysilicon, but when it is in a normal state as shown in Fig. 5, that is, when no PGM is input and thus no Sout value is input and the VPGM shows a 'low' value. The fuse section remains in its previous state without output.

With the PGM 'high', the outputs of the first, second, third and fourth end gates 29, 30, 31 and 32 are respectively the first, second, third and fourth fuses 33 It is delivered to the Sout stage of (34, 35, 36). At this time, when the Sout stage has a 'high' value, if the VPGM value that is the input value of each of the first, second, third, and fourth fuse parts 33, 34, 35, and 36 has a high value, The fuse section outputs 'high'. This means that the fuse of the fuse section is broken. If the fuse is cut once, the fuse cannot be used again and the value of the fuse is fixed to '1'.

If the Sout value is 'low' and the VPGM value is 'high', the fuse unit does not stop the fuse.

The digital / analog converter 37 converts the four digital values input to the digital / analog converter 37 into analog outputs and outputs the current value of the conversion ring to the p output terminal and the n output terminal as shown in FIG. 6. The value obtained by multiplying the offset current and the reference current Δ set to an arbitrary value becomes the output value of the final digital / analog converter 37.

Next, when the fusing operation described above, the operation of the present invention will be described. As shown in FIGS. 3 and 4, the first, second, third, and fourth D flip-flops 21, 22, 23, and 24 are described. When PGM, which is an initial input value of N, has a 'low' value, the output values E1, E2, E3, and E4 of the first, second, third, and fourth D flip-flops 21, 22, 23, and 24 are 'Low'.

In contrast, when the PGM has a high value and serial data is applied to the serial input signal SIN and four clock signals SCLK are applied, the fifth, sixth, seventh, and eighth D flip-flops 25, The outputs of 26, 27, 28 are applied to the inputs of the first, second, third, and fourth end gates 29, 30, 31, 32.

First, when the VPGM indicates the first 'high' value, the output E1 of the first D flip-flop 21 becomes 'high', where the second, third, and fourth D flip-flops 22, 23, and 24 The output signals E2, E3, and E4 represent a low state. The output value of the first AND gate 29 is determined according to the Q1 value that is the output value of the fifth D flip-flop 25. For example, when the Q1 value is 'high', the output of the first AND gate 29 indicates 'high', and this value allows the fuse of the first fuse part 33 to be cut off.

Next, when VPGM indicates the second 'high' value, E2, the output of the second D flip-flop 22, becomes 'high', in which case E1 and E2 represent the 'high' value and E3 and E4 represent the 'low' value. Indicates. As a result, the first and second AND gates 29 and 30 exhibit a 'high' value, and the first and second fuse parts 33 and 34 are selected. In this case, since the fuse of the first fuse part 33 is already cut off, only the fuse of the second fuse part 34 is selected. Subsequently, when the VPGM shows the third and fourth 'high' values, the fuses of the third fuse section 35 and the fourth fuse section 36 are selected. Next, the output of each fuse part enters the digital input of the digital / analog converter 37 and outputs a current proportional to the four input digital values according to the current difference between the p output terminal and the n output terminal.

The trimming circuit for sequential fusing of the present invention as described above has the following effects.

First, it is irrelevant to the current capacity of the voltage source to stop the fuse by fusing each bit of fuse by one bit. Therefore, it is possible to reduce the width of the metal layer for forming VPGM, which is a voltage source for breaking the fuse in the semiconductor circuit.

Second, the operation reliability is improved because the fuse is cut exactly one bit.

Claims (3)

N fuse sections each having a first input signal terminal and a second input signal terminal; N first shift registers for serially transmitting serial data input signals in accordance with a clock signal; N second shift register sections for serially transmitting signals of the second input signal terminal using the signals of the first input signal terminal of the fuse section as clock signals; N AND gates which select the fuse part sequentially by taking an output value of each register of the first and second shift register parts as two inputs, receiving and outputting the output of each register of the second shift register part, and And a digital / analog converter for converting and outputting the digital output values of the n fuse sections to analog current values. The trimming circuit of claim 1, wherein the first and second shift registers each include n D flip-flops. 2. The second input of claim 1, wherein the serial data input signal of the first shift register unit represents a 'high' value and the outputs of the respective registers of the n first shift register units represent a 'high' value, and the second input of the fuse unit And if the signal stage indicates a 'high' value, the n fuse sections are sequentially selected according to the output value of the second shift register, and the fuses of the selected fuse sections are cut off.