JP2639306B2 - Shift register circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit for realizing a simple data transfer method.

[0002]

2. Description of the Related Art Conventional data transfer is roughly divided.
As shown in FIG. 5, three methods are conceivable. Indicated by
In parallel transmission, two or more data signal lines and one
This is a transmission method using the above control lines.
The one indicated by, is called serial transmission.
The one shown excludes the clock signal for capturing data.
The clock signal is supplied from the
Generated internally.

[0003]

In the conventional data transmission, a complicated circuit for internally generating a clock is required in the internally generated clock serial transmission shown in FIG. Further, the parallel transmission shown in FIG. 5 requires a large number of signal lines to be supplied.

FIG. 6 shows a conventional shift register as a typical circuit in the external clock supply type serial transmission shown in FIG. This circuit has a feature that the configuration is simple and the number of signal lines is smaller than that of the parallel type. However, even in this case, at least two signal lines, a data line and a clock line, are required, and it is desired that the two signal lines be one in order to configure a simpler system.

SUMMARY OF THE INVENTION An object of the present invention is to realize transfer with one signal line using a simple receiving circuit.

[0006]

According to the shift register of the present invention, the output signal falls when the input signal changes.
In the falling process, when the output signal level is high, the fall speed is low, and when the output signal level is low, the fall speed is high, or the output signal is high.
In Chi up process, the level of the output signal is small time standing
Low rising velocity, time elevational level of the output signal is large
One of the delay circuits, which has a high rise speed
And connected to the circuit, the output terminal of the delay circuit to the data input terminal of the first flip-flop, is connected to the input terminal of the delay circuit to the clock input terminal of each stage, except the first stage Day
Flip-flop circuit of a plurality of stages connected to data input terminal to the output terminal of the previous stage, is configured by using a narrow pulse waveform and a pulse with a waveform width width as an input signal,
The delay time of the delay circuit is between the widths of these two types of pulse waveforms.

[0007]

FIG. 2 shows an example of a signal input to the shift register circuit of the present invention. Like this signal, a pulse having a narrow width and a pulse having a wide width represent data 1 and 0. In other words, a narrow pulse is sent when 1 is sent, and a wide pulse is sent when 0 is sent. By allocating data “1” and “0” to a narrow pulse and a wide pulse in this manner, data can be transferred by one signal line. For example, L
A pulse changing from ow → High → Low is input,
At this time, consider the case where the output changes from High to Low to High. Input of delay circuit is Low → High
, The output of the delay circuit changes from High to Low.
And changes with a delay of the fall delay time. If this input signal is high before this output signal changes to low,
→ If the pulse changes to low, that is, if a narrow pulse is input, the input signal is also connected to the clock terminal of the falling latch flip-flop of the next stage. 1 is latched.

On the other hand, when the input signal changes from High to Low after the output signal changes to Low, that is, when a wide pulse is input, the flip-flop of the next stage has the delay circuit of this time. Output signal 0 is latched. These operations are performed when a narrow pulse and a wide pulse are input, respectively.

[0009]

FIG. 1 shows a circuit example of the present invention. The delay circuit used in this circuit is a delay circuit described in the claims, wherein the falling speed is low when the level of the output signal is high, and the falling speed is high when the level of the output signal is low. Data of 1, 0 is given to this circuit by a pulse having a narrow width and a pulse having a wide width as shown in FIG. When the input (node 1) goes low, the pMOS transistor 2 turns on, and the node 3 changes to high level. However, even when the node 1 changes to the high level and the nMOS transistor 4 is turned on, the nMOS transistor 5 remains off while the node 3 is at the high level.
Since feedback is applied so that it becomes ff,
The nMOS transistor 5 remains off for a certain period of time until the potential of the node 3 slightly decreases due to the leakage current of the nMOS transistor 5. node 3 the nMOS transistor 5 is Chi straight and becomes on drops to Low level.

If the input signal (node 1) falls before the node 3 changes to the low level, this input signal is applied to the clock terminal of the falling latch flip-flop constituting the next stage shift register. The high level, which is the state of the node 3 at this time, is latched by the first flip-flop of the shift register, and the flip-flops other than the first latch the output data of the preceding flip-flop.
Similarly, if the input signal (node 1) falls after the node 3 has changed to the low level, the node 3
Is latched by the first-stage flip-flop of the shift register, and the flip-flops other than the first stage latch the output data of the preceding flip-flop.

These operations are performed when a narrow pulse and a wide pulse are input, respectively.

Next, the reason why feedback is used for the delay circuit 9 will be described. The delay circuit may be one in which a plurality of gate circuits are connected in series, or one using a CR time constant. In the shift register of the present invention, the distinction between 0 and 1 data is determined based on whether the pulse width is smaller or wider than the delay time of the delay circuit. In other words, the pulse width is set as 0 pulse width <delay time <1 pulse width. Therefore, a large delay time is required as much as possible in order to transfer data reliably.
A series connection of these gates requires a large number of gates to create a large delay, and a configuration using a CR time constant requires a large capacitance or a large resistance, which poses a problem in LSI mounting. In addition, if a large CR time constant is created, the output becomes an intermediate potential, which is a problem in transferring data reliably. Therefore, when the delay circuit used in the present invention is used, when the nMOS transistor 5 is off, the current flowing therethrough becomes a large resistance equivalent to the leakage current, thereby obtaining a large delay time. Also, once this transistor is turned on, it is completely turned on by feedback, the output is determined, and transfer can be performed reliably.

FIG. 3 shows an example of a delay circuit other than that of FIG.

The operation of this circuit is such that when the input goes low, the pMOS transistor 2 turns on and the output 3 goes high.
changes to the high level. However, the input is High
Even if the level changes to the level and the nMOS transistor 4 is turned on, when the voltage of the output 3 is higher than the voltage of the reference 20, the comparator 30 outputs a low level, so that the nMOS transistor 5 is turned off. During this time, the charge accumulated in the capacitor 11 flows through the nMOS transistor 4 and the resistor 10, but the current at this time is small and the falling speed of the output 3 is slow because of the resistor 8. When the voltage of the output 3 becomes smaller than the voltage of the reference 20, the comparator 30 outputs a high level, so that the nMOS transistor 5 is turned on, and the electric charge accumulated in the capacitor 9 is transferred to the nMOS transistor 4 and the nMOS transistor 4.
Since the current flows through the transistor 5 as a path, the current at this time is large, and the output 3 falls sharply. If the resistor 10 and the reference voltage 20 can be given with high accuracy, the delay time can be obtained with relatively high accuracy.

FIG. 4 shows an example of a delay circuit according to the present invention, in which the rising speed is low when the output signal level is low and the rising speed is high when the output signal level is high. This is because the nMOS and pMO of the delay circuit 9 in FIG.
S, the power supply and the ground are exchanged.

[0016]

As described above, when the shift register of the present invention is used, a simple circuit and one signal line can be used.
Data can be reliably transferred only with books.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a shift register circuit of the present invention.

FIG. 2 is a diagram illustrating an example of a signal input to a shift register circuit of the present invention.

FIG. 3 is a diagram showing another delay circuit of the present invention.

FIG. 4 is a diagram showing another delay circuit of the present invention.

FIG. 5 is a diagram showing a conventional signal transfer method.

FIG. 6 is a diagram showing a conventional shift register.

[Explanation of symbols]

 Reference Signs List 1 input terminal of delay circuit 2 pMOS transistor 3 output terminal of delay circuit 4, 5 nMOS transistor 6, 7, 8 flip-flop 9 delay circuit 10 resistor 11 capacitor 20 reference 30 comparator

Claims (1)

(57) [Claims] In a process in which an output signal falls due to a change in an input signal, a falling circuit has a low falling speed when the level of the output signal is high, and a delay circuit having a high falling speed when the level of the output signal is low, or In a process in which the output signal rises, one of a delay circuit having a low rising speed when the level of the output signal is low and a large rising speed when the level of the output signal is high, and an output terminal of the delay circuit being a first stage. A plurality of flip-flop circuits connected to the data input terminal of the flip-flop, the input terminal of the delay circuit is connected to the clock input terminal of each stage, and the data input terminals other than the first stage are connected to the output terminal of the preceding stage, And using a narrow pulse waveform and a wide pulse waveform as an input signal, A shift register circuit characterized in that the delay time of the circuit is between the widths of the two types of pulse waveforms.