JPH0714396A - Shift register circuit - Google Patents

Abstract

PURPOSE:To make it possible to transfer data with one signal line by a simple receiving circuit. CONSTITUTION:This circuit is provided with a delaying circuit 9 controlling the rising delay or the falling delay of the output signal of a gate circuit with its output and plural stages of FFs 6, 7, 8 in which the data input of the flip-flop (hereafter it is written as an FF) of a first stage is connected to the output 3 of the delaying circuit 9 and clock input terminals of each stage are connected to the input 1 of the delaying circuit and input terminals except the first stage are connected to the output terminal of a prestage. Data 1, 0 are given by pulses of a narrow width and a wide width respectively. A constant time is required before a node 3 is lowered to a LOW level by the delaying circuit 9 even though a node 1 goes to a HIGH level and an nMOS 4 becomes 'on'. When an input (a node 1) is fallen down before the node 3 is lowered to the LOW level, '1' is latched in the FF 6 and when the node 1 is fallen down after the node 3 is lowered to the LOW level, '0' is latched in the FF 6. Thus, data can be transferred with one signal line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register circuit which realizes a simple data transfer method.

[0002]

2. Description of the Related Art In conventional data transfer, there are roughly three methods shown in FIG. The parallel transmission indicated by 1 is a method of transmission using two or more data signal lines and one or more control lines. The one indicated by, is called serial transmission, the one indicated by is an externally supplied clock signal for capturing data, and the one indicated by is an internally generated clock signal.

[0003]

In the conventional data transmission, the clock internal generation type serial transmission shown in FIG. 5 requires a complicated circuit for internally generating the clock. In addition, the parallel transmission shown in FIG. 5 requires a large number of signal lines to be supplied.

FIG. 6 shows a conventional shift register as a typical circuit in the external clock supply type serial transmission shown in FIG. This circuit is characterized by its simple structure and the smaller number of signal lines compared to the parallel type. However, even in this case, at least two signal lines, that is, a data line and a clock line are required, and it is desirable to use these two signal lines as one in order to configure a simpler system.

An object of the present invention is to realize transfer with one signal line by a simple receiving circuit.

[0006]

In the shift register of the present invention, the falling speed is low when the level of the output signal is high, and the selection circuit or the output signal whose level is high is low when the level of the output signal is low. When the rise rate is low, the rise rate is low, and when the output signal level is high, the delay circuit has a high rise rate, and the output terminal of the delay circuit is connected to the data input terminal of the first-stage flip-flop.
The input terminal of the delay circuit is connected to the clock input terminal of each stage, the input terminal other than the first stage is connected to the output terminal of the preceding stage, it is composed of multiple stages of flip-flop circuit, and a narrow pulse waveform and A wide pulse waveform is used, and the delay time of the delay circuit is between the widths of these two types of pulse waveforms.

[0007]

FIG. 2 shows an example of signals input to the shift register circuit of the present invention. As in this signal, a narrow pulse and a wide pulse represent data 1 and 0. That is, a narrow pulse is sent when 1 is sent, and a wide pulse is sent when 0 is sent. In this way, by allocating 1 and 0 of the data with the narrow pulse and the wide pulse, the data can be transferred by one signal line. For example, in the delay circuit L
A pulse that changes from ow → High → Low is input,
At this time, consider a case where the output changes from High → Low → High. The input of the delay circuit is Low → High
Output changes from High to Low
Then, it changes with a fall delay time. If this input signal is High before the output signal changes to Low
If it changes to → Low, that is, if a narrow pulse is input, this input signal is also connected to the clock terminal of the falling latch flip-flop of the next stage, so the output signal of the delay circuit at this time 1 is latched.

On the other hand, when the input signal changes from High to Low after this output signal changes to Low, that is, when a wide pulse is input, the flip-flop of the next stage is provided with the delay circuit of this time. The output signal 0 is latched. These are operations when a narrow pulse and a wide pulse are input, respectively.

[0009]

FIG. 1 shows an example of the circuit of the present invention. The delay circuit used in this circuit is, in the claims, a delay circuit in which the falling speed is low when the level of the output signal is high, and the falling speed is high when the level of the output signal is low.
Data of 1 and 0 are given to this circuit by a narrow pulse and a wide pulse as shown in FIG. When the input (node 1) becomes low level, the pMOS transistor 2 is turned on, and the node 3 changes to high level. However, even when the node 1 is changed to the high level and the nMOS transistor 4 is turned on, the nMOS transistor 5 is turned off while the node 3 is at the high level.
Therefore, the nMOS transistor 5 remains off for a certain period of time until the potential of the node 3 drops slightly due to the leakage current of the nMOS transistor 5. As soon as the nMOS transistor 5 is turned on, the node 3 goes low.

If the input signal (node 1) falls before the node 3 changes to the low level, this input signal is the clock terminal of the falling latch flip-flop which constitutes the shift register of the next stage. Since it is also connected to, the High level which is the state of the node 3 at this time is latched by the first stage flip-flop of the shift register, and the flip-flops other than the first stage latch the output data of the preceding flip-flop.
Similarly, if the input signal (node 1) falls after the node 3 changes to the low level, the node 3
The Low level which is the state is latched by the first stage flip-flop of the shift register of the shift register, and the flip-flops other than the first stage latch the output data of the preceding flip-flop.

These show the operation when a narrow pulse and a wide pulse are input, respectively.

Next, the reason why feedback is used in the delay circuit 9 will be described. As the delay circuit, a gate circuit in which a plurality of stages are connected in series, or a CR time constant is used. In the shift register of the present invention, the distinction between 0 and 1 data is judged by the pulse width being narrower or wider than the delay time of the delay circuit. In other words, 0 pulse width <delay time <1 pulse width is set. Therefore, a delay time as large as possible is necessary to transfer the data reliably.
The serial connection of the gates requires a large number of gates to create a large delay, and the one using the CR time constant requires a large capacitance or a large resistance, which is a problem in mounting the LSI. Also, if a large CR time constant is created, the output becomes an intermediate potential, which is a problem in reliably transferring data. Therefore, when the delay circuit used in the present invention is used, when the nMOS transistor 5 is off, the flowing current becomes a large resistance such as a leakage current, so that a large delay time can be obtained. Further, once this transistor is turned on, it is completely turned on by feedback, the output is fixed, and the transfer can be reliably performed.

FIG. 3 shows an example of a delay circuit other than that shown in FIG.

The operation of this circuit is such that when the input becomes Low level, the pMOS transistor 2 is turned on and the output 3 is at H level.
It changes to the high level. However, the input is High
Even when the nMOS transistor 4 is turned on and the nMOS transistor 4 is turned on, the comparator 30 outputs a low level when the voltage of the output 3 is larger than the voltage of the reference 20, so that the nMOS transistor 5 is turned off. During this time, the charge accumulated in the capacitor 11 flows through the nMOS transistor 4 and the resistor 10 as a route, but the current at this time is small because of the resistor 8 and the falling speed of the output 3 is slow. When the voltage of the output 3 becomes lower than the voltage of the reference 20, the comparator 30 outputs a high level, so that the nMOS transistor 5 is turned on, and the charge accumulated in the capacitor 9 is stored in the nMOS transistor 4 and the nMOS.
Since the current flows through the transistor 5, the current at this time is large and the output 3 suddenly falls. If the resistor 10 and the reference voltage 20 can be applied with high precision, the delay time can be obtained with relatively high precision.

FIG. 4 shows an example of a delay circuit in the claims which has a small rising speed when the level of the output signal is small and a large rising speed when the level of the output signal is large. This is the nMOS and pMO of the delay circuit 9 of FIG.
S, the power supply and ground are exchanged.

[0016]

As described above, when the shift register of the present invention is used, the circuit is simple and the number of signal lines is 1.
Data can be reliably transferred only with books.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a shift register circuit of the present invention.

FIG. 2 is a diagram showing an example of signals input to a shift register circuit of the present invention.

FIG. 3 is a diagram showing another delay circuit of the present invention.

FIG. 4 is a diagram showing another delay circuit of the present invention.

FIG. 5 is a diagram showing a conventional signal transfer method.

FIG. 6 is a diagram showing a conventional shift register.

[Explanation of symbols]

 1 Delay Circuit Input Terminal 2 pMOS Transistor 3 Delay Circuit Output Terminal 4, 5 nMOS Transistor 6, 7, 8 Flip Flop 9 Delay Circuit 10 Resistor 11 Capacitor 20 Reference 30 Comparator

Claims (1)

[Claims] 1. A delay circuit in which the falling speed is low when the level of the output signal is high, and the falling speed is high when the level of the output signal is low, or the rising speed of the output signal is low when the level of the output signal is low. When the level is high, the delay circuit with a high rising speed and the output terminal of the delay circuit are connected to the data input terminal of the first stage flip-flop, the input terminal of the delay circuit is connected to the clock input terminal of each stage, and the input other than the first stage is input. A flip-flop circuit having a plurality of stages in which a terminal is connected to an output terminal of the preceding stage, a narrow pulse waveform and a wide pulse waveform are used as an input signal, and the delay time of the delay circuit is two types of pulses. A shift register circuit characterized by being located between waveform widths.