KR19990040587A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
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- KR19990040587A KR19990040587A KR1019970061038A KR19970061038A KR19990040587A KR 19990040587 A KR19990040587 A KR 19990040587A KR 1019970061038 A KR1019970061038 A KR 1019970061038A KR 19970061038 A KR19970061038 A KR 19970061038A KR 19990040587 A KR19990040587 A KR 19990040587A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 125000001475 halogen functional group Chemical group 0.000 claims abstract description 26
- 150000002500 ions Chemical class 0.000 claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 12
- 239000011574 phosphorus Substances 0.000 claims abstract description 12
- -1 phosphorus ions Chemical class 0.000 claims abstract description 12
- 229910052785 arsenic Inorganic materials 0.000 claims description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 종래에는 셀 트랜지스터의 저농도 소스/드레인과 할로영역의 접합부위에서 도핑 프로파일이 급격해져 접합 누설전류가 증가함으로써, 디램의 신뢰성이 저하되는 문제점이 있었다. 이와같은 문제점을 감안한 본 발명은 필드산화막을 통해 각기 분리된 웰의 상부에 셀 트랜지스터, 엔모스트랜지스터 및 피모스트랜지스터를 각각 형성하고, 각 트랜지스터의 상부에 필드산화막과 소정거리 이격되도록 게이트를 형성하는 단계와; 각 트랜지스터의 게이트를 셀프얼라인하여 저농도의 인이온을 주입하여 셀 트랜지스터 및 엔모스트랜지스터에 소스/드레인을 형성하는 단계와; 상기 셀 트랜지스터 및 피모스트랜지스터의 상부에 제1포토레지스트를 도포한 후, 이온주입공정을 통해 엔모스트랜지스터에 할로영역을 형성하는 단계와; 상기 제1포토레지스트를 제거하고, 셀 트랜지스터 및 엔모스트랜지스터의 상부에 제2포토레지스트를 도포한 후, 이온주입공정을 통해 피모스트랜지스터에 할로영역을 형성하는 단계와; 상기 피모스트랜지스터에 저농도의 피형불순물이온을 주입하여 피모스트랜지스터의 소스/드레인을 형성하는 단계로 이루어지는 반도체소자의 제조방법을 통해 도핑 프로파일이 완만한 인이온을 셀 트랜지스터에 주입하여 소스/드레인을 형성함으로써, 셀 트랜지스터의 누설전류를 최소화하여 빠른 리프레쉬 타임을 갖는 디램을 제조할 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In the related art, a doping profile sharply increases at a junction between a low concentration source / drain and a halo region of a cell transistor, thereby increasing a junction leakage current, thereby reducing the reliability of the DRAM. In view of the above problems, the present invention forms a cell transistor, an MOS transistor, and a PMOS transistor on top of each well separated through the field oxide film, and forms a gate on the transistor so as to be spaced apart from the field oxide film by a predetermined distance. Steps; Self-aligning the gates of each transistor to inject a low concentration of phosphorus ions to form a source / drain in the cell transistor and the enMOS transistor; Applying a first photoresist on the cell transistors and the PMOS transistors, and then forming a halo region in the NMOS transistors through an ion implantation process; Removing the first photoresist, applying a second photoresist on the cell transistor and the enMOS transistor, and then forming a halo region in the PMOS transistor through an ion implantation process; Injecting a low concentration of impurity ions into the PMOS transistor to form a source / drain of the PMOS transistor to form a source / drain of the PMOS transistor, and injecting a ions having a gentle doping profile into the cell transistor to form a source / drain In this way, the leakage current of the cell transistor can be minimized to produce a DRAM having a fast refresh time.
Description
본 발명은 반도체소자의 제조방법에 관한 것으로, 특히 셀 트랜지스터 및 엔/피모스 트랜지스터를 동시에 제조하는 디램(DRAM)의 성능 및 신뢰성을 향상시키고, 빠른 리프레쉬 타임(refresh time)에 대해 셀 트랜지스터의 누설전류를 억제하기에 적당하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, improves the performance and reliability of DRAMs for simultaneously manufacturing cell transistors and N / PMOS transistors, and leaks of cell transistors for fast refresh time The present invention relates to a method for manufacturing a semiconductor device suitable for suppressing a current.
최근들어 반도체소자의 고집적화를 실현하기 위해 소자들의 크기를 점차 줄임에 따라 채널의 길이도 줄어들어 펀치쓰루(punch through)가 소자의 신뢰성을 저하시키는 요인으로 대두되고 있다. 이러한 요인을 억제하기 위해 엘디디(lightly doped drain : LDD)구조의 저농도 소스/드레인영역 주위에 피형 불순물영역을 형성하는 할로(halo)공정을 도입하게 되었다. 이와같은 종래 반도체소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Recently, in order to realize high integration of semiconductor devices, as the sizes of devices are gradually reduced, the length of channels is also reduced, so that punch through becomes a factor deteriorating the reliability of devices. In order to suppress this factor, a halo process is introduced, which forms an impurity region around a low concentration source / drain region of a lightly doped drain (LDD) structure. If described in detail with reference to the accompanying drawings, a conventional method for manufacturing a semiconductor device as follows.
도1a 내지 도1e는 종래 반도체소자의 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 필드산화막(2)을 통해 분리된 각 웰(1)의 상부에 셀 트랜지스터, 엔모스트랜지스터 및 피모스트랜지스터를 형성하고, 각 트랜지스터의 상부에 필드산화막(2)과 소정거리 이격되도록 게이트(3)를 형성하는 단계(도1a)와; 그 피모스트랜지스터의 상부에 포토레지스트(PR1)를 도포하고, 셀 트랜지스터 및 엔모스트랜지스터의 게이트(3)를 셀프얼라인(self-align)하여 저농도의 불순물이온을 주입함으로써, 셀 트랜지스터 및 엔모스트랜지스터에 저농도의 소스/드레인(4)을 형성하는 단계(도1b)와; 이온주입공정을 통해 셀 트랜지스터 및 엔모스트랜지스터의 저농도 소스/드레인(4) 주위를 감싸도록 할로영역(5)을 형성하는 단계(도1c)와; 상기 포토레지스트(PR1)를 제거하고, 셀 트랜지스터 및 엔모스트랜지스터의 상부에 포토레지스트(PR2)를 도포한 후, 피모스트랜지스터의 게이트(3)를 셀프얼라인하여 저농도의 불순물이온을 주입함으로써, 피모스트랜지스터에 저농도의 소스/드레인(4)을 형성하는 단계(도1d)와; 이온주입공정을 통해 피모스트랜지스터의 저농도 소스/드레인(4) 주위를 감싸도록 할로영역(5)을 형성하는 단계(도1e)로 이루어진다. 이하, 상기한 바와같은 종래 반도체소자의 제조방법을 좀더 상세히 설명한다.1A through 1E are cross-sectional views showing a conventional method of manufacturing a semiconductor device, and as shown therein, a cell transistor, an MOS transistor, and a PMOS transistor are formed on top of each well 1 separated through a field oxide film 2. And forming a gate 3 on the transistor so as to be spaced apart from the field oxide film 2 by a predetermined distance (Fig. 1A); Applying photoresist PR1 on top of the PMOS transistor, self-aligning the cell transistors and gates of the NMOS transistors, and injecting low concentrations of impurity ions to inject the cell transistors and NMOS Forming a low concentration source / drain 4 in the transistor (FIG. 1B); Forming a halo region 5 to surround the low concentration source / drain 4 of the cell transistor and the enMOS transistor through an ion implantation process (FIG. 1C); The photoresist PR1 is removed, the photoresist PR2 is applied on the cell transistors and the enMOS transistors, and then the gate 3 of the PMOS transistor is self-aligned to inject a low concentration of impurity ions. Forming a low concentration source / drain 4 in the MOS transistor (FIG. 1D); Forming a hollow region 5 to surround the low concentration source / drain 4 of the PMOS transistor through the ion implantation process (Fig. 1E). Hereinafter, a method of manufacturing a conventional semiconductor device as described above will be described in more detail.
먼저, 도1a에 도시한 바와같이 필드산화막(2)을 통해 분리된 각 웰(1)의 상부에 셀 트랜지스터, 엔모스트랜지스터 및 피모스트랜지스터를 형성하고, 각 트랜지스터의 상부에 필드산화막(2)과 소정거리 이격되도록 게이트(3)를 형성한다. 이때, 필드산화막(2)은 반도체기판상에 형성되는 각 소자들을 전기적으로 절연시키며, 게이트(3)는 게이트산화막, 게이트전극. 절연막의 적층구조로 형성된다.First, as shown in FIG. 1A, a cell transistor, an MOS transistor, and a PMOS transistor are formed on each well 1 separated through the field oxide film 2, and the field oxide film 2 is formed on the top of each transistor. The gate 3 is formed to be spaced apart from the predetermined distance. At this time, the field oxide film 2 electrically insulates each element formed on the semiconductor substrate, and the gate 3 is a gate oxide film and a gate electrode. It is formed in a laminated structure of an insulating film.
그리고, 도1b에 도시한 바와같이 피모스트랜지스터의 상부에 포토레지스트(PR1)를 도포하고, 셀 트랜지스터 및 엔모스트랜지스터의 게이트(3)를 셀프얼라인하여 저농도의 불순물이온을 주입함으로써, 셀 트랜지스터 및 엔모스트랜지스터에 저농도의 소스/드레인(4)을 형성한다. 이때, 셀 트랜지스터 및 엔모스트랜지스터의 소스/드레인(4)에 주입되는 불순물은 엔형 불순물인 저농도의 비소(As) 또는 비소+인(As+P)이며, 소스/드레인(4)을 저농도로 형성하는 이유는 이후 게이트측벽을 형성하고, 상기 게이트(3)와 게이트측벽을 셀프얼라인하여 소스/드레인(4)에 고농도의 불순물이온을 주입함으로써, 엘디디구조를 형성하여 단채널로 인한 펀치쓰루를 억제하기 위해서이다.As shown in FIG. 1B, the photoresist PR1 is coated on the PMOS transistor, and the cell transistor and the gate of the NMOS transistor 3 are self-aligned to inject a low concentration of impurity ions. A low concentration source / drain 4 is formed in the NMOS transistor. At this time, the impurity injected into the source / drain 4 of the cell transistor and the enMOS transistor is low concentration of arsenic (As) or arsenic + phosphorus (As + P), which is an en-type impurity, and the source / drain 4 is formed at low concentration. The reason for this is to form a gate sidewall, and self-align the gate 3 and the gate sidewall to inject a high concentration of impurity ions into the source / drain 4, thereby forming an LED structure to form a punch-through due to a short channel. To suppress it.
그리고, 도1c에 도시한 바와같이 이온주입공정을 통해 셀 트랜지스터 및 엔모스트랜지스터의 저농도 소스/드레인(4) 주위를 감싸도록 할로영역(5)을 형성한다. 이때, 셀 트랜지스터 및 엔모스트랜지스터의 할로영역(5)에는 큰 편향각(large angle tilt : LAT)으로 피형 불순물인 고농도의 BF2또는 B 이온을 주입하며, 할로영역(5)을 형성하는 이유는 피/엔 접합에 의해 형성되는 공핍층을 셀 트랜지스터 및 엔모스트랜지스터의 저농도 소스/드레인(4)측으로 확장시켜 게이트(3)의 하부에 형성되는 채널의 길이를 최대한 확장함으로써, 펀치쓰루를 억제하기 위해서이다.As shown in FIG. 1C, a hollow region 5 is formed to surround the low concentration source / drain 4 of the cell transistor and the enMOS transistor through an ion implantation process. At this time, the halo region 5 of the cell transistor and the enMOS transistor is implanted with a high concentration of BF 2 or B ions, which is a type impurity, at a large angle tilt (LAT), and thus the halo region 5 is formed. Suppressing punchthrough by extending the depletion layer formed by the P / N junction to the side of the low concentration source / drain 4 of the cell transistors and the MOS transistors to maximize the length of the channel formed under the gate 3. For that.
그리고, 도1d에 도시한 바와같이 포토레지스트(PR1)를 제거하고, 셀 트랜지스터 및 엔모스트랜지스터의 상부에 포토레지스트(PR2)를 도포한 후, 피모스트랜지스터의 게이트(3)를 셀프얼라인하여 저농도의 불순물이온을 주입함으로써, 피모스트랜지스터에 저농도의 소스/드레인(4)을 형성한다. 이때, 피모스트랜지스터의 소스/드레인(4)에 주입되는 불순물은 피형 불순물인 저농도의 BF2또는 B 이온이며, 소스/드레인(4)을 저농도로 형성하는 이유는 상기 셀 트랜지스터 및 엔모스트랜지스터의 소스/드레인(4)과 동일하게 엘디디구조를 형성하여 단채널로 인한 펀치쓰루를 억제하기 위해서이다.Then, as shown in Fig. 1D, the photoresist PR1 is removed, the photoresist PR2 is applied on the cell transistors and the enMOS transistors, and then the gate 3 of the PMOS transistor is self-aligned to have a low concentration. By implanting impurity ions of, a low concentration source / drain 4 is formed in the MOS transistor. At this time, the impurities injected into the source / drain 4 of the PMOS transistor are low concentrations of BF 2 or B ions, which are the type impurities, and the reason for forming the source / drain 4 at low concentrations is that of the cell transistors and the enMOS transistors. The purpose is to form an LED structure similarly to the source / drain 4 to suppress punch through caused by the short channel.
그리고, 도1e에 도시한 바와같이 이온주입공정을 통해 피모스트랜지스터의 저농도 소스/드레인(4) 주위를 감싸도록 할로영역(5)을 형성한다. 이때, 피모스트랜지스터의 할로영역(5)에는 큰 편향각으로 엔형 불순물인 고농도의 비소(As) 또는 비소+인(As+P) 이온을 주입하며, 할로영역(5)을 형성하는 이유는 상기 셀 트랜지스터 및 엔모스트랜지스터의 할로영역(5)과 동일하게 피/엔 접합에 의해 형성되는 공핍층을 피모스트랜지스터의 저농도 소스/드레인(4)측으로 확장시켜 게이트(3)의 하부에 형성되는 채널의 길이를 최대한 확장함으로써, 펀치쓰루를 억제하기 위해서이다.As shown in FIG. 1E, a hollow region 5 is formed to surround the low concentration source / drain 4 of the PMOS transistor through an ion implantation process. In this case, the high concentration of arsenic (As) or arsenic + phosphorus (As + P) ions, which are en-type impurities, is implanted into the halo region 5 of the PMOS transistor at a large deflection angle, and the reason for forming the halo region 5 is described above. A channel formed under the gate 3 by extending the depletion layer formed by the P / N junction to the low concentration source / drain 4 side of the PMOS transistor in the same manner as the halo region 5 of the cell transistor and the MOS transistor. This is to suppress the punch through by extending the length of.
그러나, 상기한 바와같은 종래 반도체소자의 제조방법은 셀 트랜지스터의 저농도 소스/드레인과 할로영역의 접합부위에서 도핑 프로파일(doping profile)이 급격해져 접합 누설전류가 증가함으로써, 디램의 신뢰성이 저하되는 문제점이 있었다.However, the conventional method of manufacturing a semiconductor device as described above has a problem in that the reliability of the DRAM is deteriorated because the doping profile is sharply increased at the junction of the low concentration source / drain and the halo region of the cell transistor, thereby increasing the junction leakage current. there was.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 셀 트랜지스터의 누설전류를 최소화하여 디램의 신뢰성을 향상시킬수 있는 반도체소자의 제조방법을 제공하는데 있다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device that can improve the reliability of the DRAM by minimizing the leakage current of the cell transistor.
도1은 종래 반도체소자의 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
1:웰 2:필드산화막1: Well 2: Field oxide
3:게이트 4:소스/드레인3: gate 4: source / drain
5:할로영역 PR1,PR2:포토레지스트5: Halo area PR1, PR2: photoresist
상기한 바와같은 본 발명의 목적은 필드산화막을 통해 각기 분리된 웰의 상부에 셀 트랜지스터, 엔모스트랜지스터 및 피모스트랜지스터를 각각 형성하고, 각 트랜지스터의 상부에 필드산화막과 소정거리 이격되도록 게이트를 형성하는 단계와; 각 트랜지스터의 게이트를 셀프얼라인하여 저농도의 인이온을 주입하여 셀 트랜지스터 및 엔모스트랜지스터에 소스/드레인을 형성하는 단계와; 상기 셀 트랜지스터 및 피모스트랜지스터의 상부에 제1포토레지스트를 도포한 후, 이온주입공정을 통해 엔모스트랜지스터에 할로영역을 형성하는 단계와; 상기 제1포토레지스트를 제거하고, 셀 트랜지스터 및 엔모스트랜지스터의 상부에 제2포토레지스트를 도포한 후, 이온주입공정을 통해 피모스트랜지스터에 할로영역을 형성하는 단계와; 상기 피모스트랜지스터에 저농도의 피형불순물이온을 주입하여 피모스트랜지스터의 소스/드레인을 형성하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.As described above, an object of the present invention is to form a cell transistor, an MOS transistor, and a PMOS transistor on top of each well separated through a field oxide film, and to form a gate spaced apart from the field oxide film by a predetermined distance on top of each transistor. Making a step; Self-aligning the gates of each transistor to inject a low concentration of phosphorus ions to form a source / drain in the cell transistor and the enMOS transistor; Applying a first photoresist on the cell transistors and the PMOS transistors, and then forming a halo region in the NMOS transistors through an ion implantation process; Removing the first photoresist, applying a second photoresist on the cell transistor and the enMOS transistor, and then forming a halo region in the PMOS transistor through an ion implantation process; It is achieved by the step of forming a source / drain of the PMOS transistor by injecting a low concentration of the form impurity ions into the PMOS transistor, it will be described in detail with reference to the accompanying drawings, a method for manufacturing a semiconductor device according to the present invention. As follows.
도2a 내지 도2e는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 필드산화막(2)을 통해 분리된 각 웰(1)의 상부에 셀 트랜지스터, 엔모스트랜지스터 및 피모스트랜지스터를 형성하고, 각 트랜지스터의 상부에 필드산화막(2)과 소정거리 이격되도록 게이트(3)를 형성하는 단계(도2a)와; 각 트랜지스터의 게이트(3)를 셀프얼라인하여 저농도의 인이온을 주입함으로써, 셀 트랜지스터 및 엔모스트랜지스터에 소스/드레인(4)을 형성하는 단계(도2b)와; 셀 트랜지스터 및 피모스트랜지스터의 상부에 포토레지스트(PR1)를 도포한 후, 이온주입공정을 통해 엔모스트랜지스터에 할로영역(5)을 형성하는 단계(도2c)와; 그 포토레지스트(PR1)를 제거하고, 셀 트랜지스터 및 엔모스트랜지스터의 상부에 포토레지스트(PR2)를 도포한 후, 이온주입공정을 통해 피모스트랜지스터에 할로영역(5)을 형성하는 단계(도2d)와; 상기 피모스트랜지스터에 저농도의 피형불순물이온을 주입하여 소스/드레인(4)을 형성하는 단계(도2e)로 이루어진다. 이하, 상기한 바와같은 본 발명의 실시예에 대해 좀더 상세히 설명한다.2A to 2E are cross-sectional views showing an embodiment of the present invention. As shown therein, a cell transistor, an MOS transistor, and a PMOS transistor are formed on top of each well 1 separated through the field oxide film 2. And forming a gate 3 on the transistor so as to be spaced apart from the field oxide film 2 by a predetermined distance (Fig. 2A); Forming a source / drain 4 in the cell transistor and the enMOS transistor by self-aligning the gate 3 of each transistor to inject a low concentration of in ions (FIG. 2B); After applying photoresist PR1 on the cell transistor and the PMOS transistor, forming a halo region 5 in the NMOS transistor through an ion implantation process (FIG. 2C); The photoresist PR1 is removed, the photoresist PR2 is applied on the cell transistors and the enMOS transistors, and then a halo region 5 is formed in the PMOS transistor through an ion implantation process (FIG. 2D). )Wow; Injecting a low concentration of impurity ions into the PMOS transistor to form a source / drain (4) (Fig. 2e). Hereinafter, embodiments of the present invention as described above will be described in more detail.
먼저, 도2a에 도시한 바와같이 필드산화막(2)을 통해 분리된 각 웰(1)의 상부에 셀 트랜지스터, 엔모스트랜지스터 및 피모스트랜지스터를 형성하고, 각 트랜지스터의 상부에 필드산화막(2)과 소정거리 이격되도록 게이트(3)를 형성한다. 종래와 동일하게 필드산화막(2)은 소자들을 전기적으로 분리시키고, 게이트(3)는 게이트산화막, 게이트전극, 절연막의 적층구조로 형성된다.First, as shown in FIG. 2A, a cell transistor, an MOS transistor, and a PMOS transistor are formed on each well 1 separated through the field oxide film 2, and the field oxide film 2 is formed on each transistor. The gate 3 is formed to be spaced apart from the predetermined distance. As in the prior art, the field oxide film 2 electrically separates the elements, and the gate 3 is formed of a stacked structure of a gate oxide film, a gate electrode, and an insulating film.
그리고, 도2b에 도시한 바와같이 각 트랜지스터의 게이트(3)를 셀프얼라인하여 저농도의 인이온을 주입함으로써, 셀 트랜지스터 및 엔모스트랜지스터에 소스/드레인(4)을 형성한다. 이때, 인이온은 5KeV∼50KeV의 에너지로 0.5×1012∼5.0×1013cm-2개를 주입한다.As shown in Fig. 2B, the gate 3 of each transistor is self-aligned to inject a low concentration of phosphorus ions to form a source / drain 4 in the cell transistor and the enMOS transistor. In this case, 0.5 × 10 12 to 5.0 × 10 13 cm -2 pieces of phosphorus ions are injected at an energy of 5 KeV to 50 KeV.
그리고, 도2c에 도시한 바와같이 셀 트랜지스터 및 피모스트랜지스터의 상부에 포토레지스트(PR1)를 도포한 후, 이온주입공정을 통해 엔모스트랜지스터에 할로영역(5)을 형성한다. 이때 이온주입공정은 엔모스트랜지스터의 소스/드레인(4)에 비소(As)이온을 주입한 후, 할로영역(5)에 BF2또는 B 이온을 주입하며, 비소이온은 5KeV∼100KeV의 에너지로 0.5×1012∼5.0×1013cm-2개를 주입하고, BF2는 20KeV∼150KeV의 에너지로 0.5×1012∼5.0×1013cm-2개를 편향각 5°∼90°로 주입하며, B는 5KeV∼50KeV의 에너지로 0.5×1012∼5.0×1013cm-2개를 편향각 5°∼90°로 주입한다.As shown in FIG. 2C, the photoresist PR1 is coated on the cell transistor and the PMOS transistor, and then the halo region 5 is formed in the NMOS transistor through an ion implantation process. At this time, the ion implantation process injects arsenic (As) ions into the source / drain (4) of the NMOS transistor, and then injects BF 2 or B ions into the halo region (5), the arsenic ion is energy of 5KeV ~ 100KeV 0.5 × 10 12 to 5.0 × 10 13 cm -2 are injected, and BF 2 is injected at a deflection angle of 5 ° to 90 ° with 0.5K10 12 to 5.0 × 10 13 cm -2 at an energy of 20KeV to 150KV. , B is injected at a deflection angle of 5 ° to 90 ° with 0.5 × 10 12 to 5.0 × 10 13 cm −2 with energy of 5KeV to 50KV.
그리고, 도2d에 도시한 바와같이 포토레지스트(PR1)를 제거하고, 셀 트랜지스터 및 엔모스트랜지스터의 상부에 포토레지스트(PR2)를 도포한 후, 이온주입공정을 통해 피모스트랜지스터에 할로영역(5)을 형성한다. 이때, 피모스트랜지스터의 할로영역(5)에 주입되는 불순물은 인 또는 비소이온이며, 이미 피모스트랜지스터의 소스/드레인영역에 주입된 인이온을 고려하여 인이온은 10KeV∼120KeV의 에너지로 0.5×1012∼5.0×1013cm-2개를 편향각 5°∼90°로 주입하고, 비소이온은 10KeV∼200KeV의 에너지로 0.5×1012∼5.0×1013cm-2개를 편향각 5°∼90°로 주입한다.As shown in FIG. 2D, the photoresist PR1 is removed, the photoresist PR2 is applied on the cell transistors and the enMOS transistors, and then the halo region 5 is applied to the PMOS transistor through an ion implantation process. ). At this time, the impurity implanted into the halo region 5 of the PMOS transistor is phosphorus or arsenic ion, and the phosphorus ion is 0.5 × with an energy of 10 KeV to 120 KeV in consideration of the phosphorus ion already injected into the source / drain region of the PMOS transistor. 10 12 to 5.0 × 10 13 cm -2 pieces are injected at a deflection angle of 5 ° to 90 °, and arsenic ions are 0.5 × 10 12 to 5.0 × 10 13 cm -2 pieces to a deflection angle of 5 ° for energy of 10 KeV to 200 KeV. Inject at ˜90 °.
그리고, 도2e에 도시한 바와같이 피모스트랜지스터에 저농도의 피형불순물이온을 주입하여 소스/드레인(4)을 형성한다. 이때, 피모스트랜지스터의 소스/드레인(4)에 주입되는 불순물은 BF2또는 B 이온이며, BF2는 10KeV∼60KeV의 에너지로 0.5×1012∼5.0×1013cm-2개를 주입하고, B는 5KeV∼20KeV의 에너지로 0.5×1012∼5.0×1013cm-2개를 주입하며, 상기 피모스트랜지스터의 할로영역(5)은 소스/드레인(4)의 하부로 매립된다.As shown in Fig. 2E, a low concentration of impurity ions is injected into the PMOS transistor to form a source / drain (4). At this time, the impurity injected into the source / drain 4 of the PMOS transistor is BF 2 or B ions, and BF 2 is injected with 0.5 × 10 12 to 5.0 × 10 13 cm −2 with energy of 10 KeV to 60 KeV, B is injected with 0.5 × 10 12 to 5.0 × 10 13 cm −2 with energy of 5 KeV to 20 KeV, and the halo region 5 of the PMOS transistor is buried under the source / drain 4.
상기한 바와같은 본 발명에 의한 반도체소자의 제조방법은 도핑 프로파일이 완만한 인이온을 셀 트랜지스터에 주입하여 소스/드레인을 형성함으로써, 셀 트랜지스터의 누설전류를 최소화하여 빠른 리프레쉬 타임을 갖는 디램을 제조할 수 있는 효과가 있다.In the method of manufacturing a semiconductor device according to the present invention as described above, a source / drain is formed by injecting ions having a slow doping profile into a cell transistor, thereby minimizing leakage current of the cell transistor to manufacture a DRAM having a fast refresh time. It can work.
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