KR19990034521A - Liquid crystal display device and its manufacturing method and manufacturing equipment for producing the liquid crystal display device - Google Patents
Liquid crystal display device and its manufacturing method and manufacturing equipment for producing the liquid crystal display device Download PDFInfo
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- KR19990034521A KR19990034521A KR1019970056141A KR19970056141A KR19990034521A KR 19990034521 A KR19990034521 A KR 19990034521A KR 1019970056141 A KR1019970056141 A KR 1019970056141A KR 19970056141 A KR19970056141 A KR 19970056141A KR 19990034521 A KR19990034521 A KR 19990034521A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 38
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 110
- 239000004065 semiconductor Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims description 44
- 238000000206 photolithography Methods 0.000 claims description 31
- 239000010408 film Substances 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 15
- 239000010409 thin film Substances 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 claims 1
- 238000004140 cleaning Methods 0.000 abstract description 25
- 238000000151 deposition Methods 0.000 abstract description 21
- 230000008021 deposition Effects 0.000 abstract description 19
- 230000015572 biosynthetic process Effects 0.000 abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 238000000926 separation method Methods 0.000 abstract description 2
- 229910052710 silicon Inorganic materials 0.000 abstract description 2
- 239000010703 silicon Substances 0.000 abstract description 2
- 230000035515 penetration Effects 0.000 abstract 1
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
본 발명은 액정표시장치 및 그 제조방법과 이 액정표시장치를 생산하는 제조장비에 관한 것으로, 도핑된 실리콘층을 형성한 후, 세정공정을 거치지 않고 진공조건을 유지한 상태로 소오스/드레인 형성용 금속층을 형성하기 위하여, 오믹콘택층을 형성하기 위한 도핑된 반도체층을 형성하는 공정과 소오스/드레인 전극을 형성하기 위한 도전층을 형성하는 공정을 진공을 유지한 상태에서 연속적으로 진행하고, 도전층을 패터닝하여 소오스/드레인 전극을 형성한 후, 소오스/드레인 전극을 마스크로하여 도핑된 반도체층을 식각하여 오믹콘택층을 형성하며, 도전층을 형성하기 위한 증착전세정작업과, 채널영역 상단의 오믹콘택층 부분을 분리하는 작업을 생략함으로써, 제조공정을 단순화하고, 오믹콘택층과 소오스/드레인 전극의 경계에 자연산화막이 형성되거나 이물질이 침투하는 것을 방지한다.The present invention relates to a liquid crystal display device and a method for manufacturing the same, and to a manufacturing equipment for producing the liquid crystal display device, wherein after forming a doped silicon layer, for source / drain formation under vacuum conditions without undergoing a cleaning process In order to form a metal layer, the process of forming a doped semiconductor layer for forming an ohmic contact layer and the process of forming a conductive layer for forming a source / drain electrode are continuously performed in a vacuum state, and the conductive layer Patterned to form a source / drain electrode, and then a doped semiconductor layer is etched using the source / drain electrode as a mask to form an ohmic contact layer, and a pre-deposition cleaning operation for forming a conductive layer, By omitting the separation of the ohmic contact layer, the manufacturing process is simplified, and a natural oxide film is formed at the boundary between the ohmic contact layer and the source / drain electrodes. Prevents the formation or penetration of foreign objects.
Description
본 발명은 액정표시장치 및 그 제조방법과 이 액정표시장치를 생산하는 제조장비에 관한 것으로, 특히 도핑된 실리콘층을 형성한 후, 세정공정을 거치지 않고 진공조건을 유지한 상태에서 소오스/드레인 형성용 금속층을 형성하는 액정표시장치 및 그 제조방법과, 이 액정표시장치를 생산하는 제조장비에 관한 것이다.The present invention relates to a liquid crystal display device and a method for manufacturing the same, and to a manufacturing equipment for producing the liquid crystal display device. In particular, after the doped silicon layer is formed, source / drain formation is maintained under vacuum without a cleaning process. A liquid crystal display device for forming a metal layer for use, a method for manufacturing the same, and a manufacturing equipment for producing the liquid crystal display device.
액정표시장치의 제조를 위한 제조장비는 일반적인 반도체 제조장비와 같이, 증착, 식각 혹은, 세정 등을 위한 각각의 체임버(chamber)가 연관을 가지고 위치하여 있고, 자동제어장치에 의해 체임버에서 체임버로의 기판 유입 및 반출이 이루어지도록 하고 있다.The manufacturing equipment for manufacturing the liquid crystal display device, like the general semiconductor manufacturing equipment, is located in relation to each chamber (chamber) for deposition, etching, cleaning, etc., from the chamber to the chamber by the automatic control device Substrate inflow and outflow is made.
액정표시장치에서의 세정은 유리기판 위의 이물질 및 파티클을 제거하는 공정으로서, TFT의 결함을 최소화하여 수율을 향상시키는데 목적이 있다. 이에는 순유리기판을 클리닝하는 초기세정(initial cleaning)과, 증착 전후에 발생하는 이물질 및 파티클을 제거하기 위하여 클리닝하는 증착전세정(pre-depo cleaning)이 있다. 세정은 순수를 사용하여 물리적인 힘. 초음파, 자외선 등을 이용하여 유리기판 혹은 기판위에 형성된 유기물이나 무기물을 제거하거나 분해하는 것이다.Cleaning in a liquid crystal display is a process of removing foreign matter and particles on a glass substrate, and aims to improve yield by minimizing defects of TFTs. This includes initial cleaning to clean the pure glass substrate and pre-depo cleaning to remove foreign substances and particles generated before and after deposition. Cleaning is pure physical force using pure water. Ultrasonic or ultraviolet rays are used to remove or decompose organic or inorganic substances formed on the glass substrate or the substrate.
도 1a부터 도 1d는 종래의 제 1 기술을 설명하기 위한 도면으로, BCE(Back Channel Etch)형 액정표시장치의 제조공정 단면도를 나타낸 것이다.1A to 1D are cross-sectional views illustrating a conventional first technology, and illustrate a cross-sectional view of a manufacturing process of a BCE liquid crystal display.
도 1a를 참조하면, 세정공정에 의하여 클리닝된 절연기판(100)에 제 1 도전층을 형성한 후, 제 1 도전층을 사진식각공정에 의하여 패터닝하여 게이트전극(11)을 형성한다. 이어서, 노출된 기판 전면에 증착전세정을 한 후, 제 1 절연막(12)과 반도체층과 도핑된 반도체층을 연속적으로 형성한다. 그 다음, 도핑된 반도체층을 사진식각공정에 의하여 패터닝하여 오믹콘택층(14)을 형성한다. 이어서, 오믹콘택층(14)을 마스크로하여 그 하단에 있는 반도체층을 식각하여 활성층(13)을 형성한다.Referring to FIG. 1A, after the first conductive layer is formed on the insulating substrate 100 cleaned by the cleaning process, the first conductive layer is patterned by a photolithography process to form the gate electrode 11. Subsequently, after deposition is performed on the entire exposed substrate, the first insulating layer 12, the semiconductor layer, and the doped semiconductor layer are successively formed. Next, the doped semiconductor layer is patterned by a photolithography process to form an ohmic contact layer 14. Subsequently, the active layer 13 is formed by etching the semiconductor layer at the bottom thereof using the ohmic contact layer 14 as a mask.
도 1b를 참조하면, 노출된 기판 전면에 증착전세정을 진행한 후, 소오스/드레인 전극을 형성하기 위한 제 2 도전층(15ℓ)을 형성한다.Referring to FIG. 1B, after the deposition pretreatment is performed on the entire surface of the exposed substrate, a second conductive layer 15L for forming the source / drain electrodes is formed.
도 1c를 참조하면, 제 2 도전층을 사진식각공정에 의하여 패터닝하여 소오스전극(15S)과 드레인전극(15D)을 형성한다. 이후, 소오스전극(15S)과 드레인전극(15D)을 마스크로하여 그 하단에 있는 오믹콘택층(14)을 식각하여 소오스전극(15S)과 드레인전극(15D)의 사이에 위치하는 오믹콘택층(14) 부분을 제거한다.Referring to FIG. 1C, the second conductive layer is patterned by a photolithography process to form a source electrode 15S and a drain electrode 15D. Subsequently, the ohmic contact layer 14 at the bottom thereof is etched using the source electrode 15S and the drain electrode 15D as a mask, and the ohmic contact layer positioned between the source electrode 15S and the drain electrode 15D ( 14) Remove the part.
도 1d를 참조하면, 노출된 기판 전면에 증착전세전을 실시한 후, 제 2 절연막(16)을 형성한다. 이어서, 제 2 절연막을 사진식각공정에 의하여 패터닝하여 드레인전극(15D)의 일부를 노출시키는 콘택홀(H)을 형성한다. 이후, 노출된 기판 전면에 증착전세정을 진행한 후, 투명도전층을 형성하고, 투명도전층을 사진식각공정에 의하여 패터닝하여 화소전극(17)을 형성한다.Referring to FIG. 1D, after the deposition pretreatment is performed on the exposed substrate, the second insulating layer 16 is formed. Subsequently, the second insulating film is patterned by a photolithography process to form a contact hole H exposing a part of the drain electrode 15D. Subsequently, after the deposition pre-cleaning is performed on the entire surface of the exposed substrate, a transparent conductive layer is formed, and the transparent conductive layer is patterned by a photolithography process to form the pixel electrode 17.
도 2a부터 도 2d는 종래의 제 2 기술을 설명하기 위한 도면으로, ES(Etch Sopper)형 액정표시장치의 제조공정 단면도를 나타낸 것이다.2A to 2D are diagrams for explaining a second technology, which is a cross-sectional view of a manufacturing process of an ES (Etch Sopper) type liquid crystal display device.
도 2a를 참조하면, 세정공정에 의하여 클리닝된 절연기판(200)에 제 1 도전층을 형성한 후, 제 1 도전층을 사진식각공정에 의하여 패터닝하여 게이트전극(21)을 형성한다. 이어서, 노출된 기판 전면에 증착전세정(pre-depo cleaning)을 한 후, 제 1 절연막(22)과 반도체층(23ℓ)과 실리콘 질화막을 연속적으로 형성한다. 그 다음, 실리콘 질화막을 사진식각공정에 의하여 패터닝하여 에치스토퍼(29)를 형성한다.Referring to FIG. 2A, after forming a first conductive layer on the insulating substrate 200 cleaned by the cleaning process, the first conductive layer is patterned by a photolithography process to form the gate electrode 21. Subsequently, after pre-depo cleaning is performed on the entire exposed substrate, the first insulating film 22, the semiconductor layer 23 L and the silicon nitride film are successively formed. Next, the silicon nitride film is patterned by a photolithography process to form an etch stopper 29.
도 2b를 참조하면, 노출된 기판 전면에 증착전세정을 진행한 후, 도핑된 반도체층을 형성한다. 이 후, 도핑된 반도체층을 사진식각공정에 의하여 패터닝하여 오믹콘택층(24)을 형성하고, 다시, 오믹콘택층(24)을 마스크로하여 그 하단에 있는 반도체층을 식각하여 활성층(23)을 형성한다.Referring to FIG. 2B, pre-deposition cleaning is performed on the entire surface of the exposed substrate to form a doped semiconductor layer. Thereafter, the doped semiconductor layer is patterned by a photolithography process to form an ohmic contact layer 24, and then the semiconductor layer at the bottom thereof is etched using the ohmic contact layer 24 as a mask to form an active layer 23. To form.
도 2c를 참조하면, 노출된 기판 전면에 증착전세정을 진행한 후, 소오스/드레인 전극을 형성하기 위한 제 2 도전층(25ℓ)을 형성한다.Referring to FIG. 2C, after the deposition pretreatment is performed on the entire surface of the exposed substrate, a second conductive layer 25 L for forming the source / drain electrodes is formed.
도 2d를 참조하면, 제 2 도전층(25ℓ)을 사진식각공정에 의하여 패터닝하여 소오스전극(25S)과 드레인전극(25D)을 형성한다. 이후, 소오스전극(25S)과 드레인전극(25D)을 마스크로하여 그 하단에 있는 오믹콘택층을 식각하여 소오스전극(25S)과 드레인전극(25D)의 사이에 위치하는 오믹콘택층 부분을 제거한다.Referring to FIG. 2D, the second conductive layer 25 L is patterned by a photolithography process to form a source electrode 25S and a drain electrode 25D. Subsequently, the ohmic contact layer at the bottom thereof is etched using the source electrode 25S and the drain electrode 25D as a mask to remove a portion of the ohmic contact layer positioned between the source electrode 25S and the drain electrode 25D. .
도 2e를 참조하면, 노출된 기판 전면에 증착전세전을 실시한 후, 제 2 절연막(26)을 형성한다. 이어서, 제 2 절연막(26)을 사진식각공정에 의하여 패터닝하여 드레인전극(25D)의 일부를 노출시키는 콘택홀(H)을 형성한다. 이후, 노출된 기판 전면에 증착전세정을 진행한 후, 투명도전층을 형성하고, 투명도전층을 사진식각공정에 의하여 패터닝하여 화소전극(27)을 형성한다.Referring to FIG. 2E, after the deposition pretreatment is performed on the entire exposed substrate, the second insulating layer 26 is formed. Subsequently, the second insulating layer 26 is patterned by a photolithography process to form a contact hole H exposing a part of the drain electrode 25D. Subsequently, after the deposition pre-cleaning is performed on the entire surface of the exposed substrate, a transparent conductive layer is formed, and the transparent conductive layer is patterned by a photolithography process to form a pixel electrode 27.
상술한 종래의 기술들에서는 도핑된 반도체층으로 이루어진 오믹콘택층을 형성하고, 기판에 증착전세정작업을 진행한 후, 다시 오믹콘택층 상단에 소오스/드레인 전극을 형성하기 위한 제 2 도전층을 형성한다. 그런데 오믹콘택층을 형성하기 위한 공정 및 제 2 도전층을 형성하기 위한 도전물질 증착작업은 각각 별도의 체임버에서 진행되기 때문에 기판을 운반하는 과정 중에 진공상태의 공정조건이 깨지게 되어 외부환경에 기판이 노출되게 된다. 그 결과, 오믹콘택층의 표면에 자연산화막이 형성됨으로써, 오믹콘택층과 제 2 도전층으로 형성되는 소오스/드레인 전극의 경계에 접촉저항의 크기를 증가시킨다. 또한, 도 3을 참조한 바와 같이, 제 2 도전층(35ℓ)을 형성하기 전과정에서 기판을 운반하는 도중에 혹은, 세정공정중에 오믹콘택층(34)의 상단에 이물질(40)이 기판에 위치하게 됨으로써, 제 2 도전층(35ℓ)을 사진식각하는 과정에서 미스얼라인을 유발시켜 소오스전극(35S) 혹은, 신호선(35L) 등의 오픈 혹은 단선을 야기시킨다.In the above-described conventional techniques, an ohmic contact layer including a doped semiconductor layer is formed, a deposition pretreatment is performed on a substrate, and a second conductive layer for forming a source / drain electrode is formed on the ohmic contact layer. Form. However, since the process of forming the ohmic contact layer and the conducting material deposition process for forming the second conductive layer are performed in separate chambers, the vacuum processing conditions are broken during the process of transporting the substrate. Exposed. As a result, a natural oxide film is formed on the surface of the ohmic contact layer, thereby increasing the size of contact resistance at the boundary between the source / drain electrodes formed of the ohmic contact layer and the second conductive layer. In addition, as shown in FIG. 3, the foreign material 40 is positioned on the substrate during the transport of the substrate in the process of forming the second conductive layer 35L or at the top of the ohmic contact layer 34 during the cleaning process. In the process of photoetching the second conductive layer 35L, a misalignment is caused to cause open or disconnection of the source electrode 35S or the signal line 35L.
본 발명은 오믹콘택층을 형성하기 위한 도핑된 반도체층을 형성하는 공정과 소오스/드레인 전극을 형성하기 위한 도전층을 형성하는 공정을 진공을 깨뜨리지 않는 조건에서 연속적으로 진행함으로써, 오믹콘택층과 소오스/드레인 전극의 경계에 자연산화막이 형성되거나, 이물질이 침투하는 것을 방지하기 위한 액정표시장치와 그 제조방법을 제공하고자 하는 것이다.According to the present invention, a process of forming a doped semiconductor layer for forming an ohmic contact layer and a process of forming a conductive layer for forming a source / drain electrode are continuously performed under conditions that do not break a vacuum, thereby providing an ohmic contact layer and a source. It is an object of the present invention to provide a liquid crystal display device and a method of manufacturing the same to prevent a natural oxide film from being formed at a boundary between a drain electrode and a foreign material.
또한, 오믹콘택층을 형성하기 위한 도핑된 반도체층을 형성하는 공정과 소오스/드레인 전극을 형성하기 위한 도전층을 형성하는 공정을 연속적으로 진행하고, 도전층을 패터닝하여 소오스/드레인 전극을 형성한 후, 소오스/드레인 전극을 마스크로하여 도핑된 반도체층을 식각하여 오믹콘택층을 형성함으로써, 도전층을 형성하기 위한 증착전세정작업과, 채널영역 상단의 오믹콘택층 부분을 분리하는 작업이 생략하여 제조공정이 단순화된 액정표시장치와 그 제조방법을 제공하고자 하는 것이다.In addition, a process of forming a doped semiconductor layer for forming an ohmic contact layer and a process of forming a conductive layer for forming a source / drain electrode are successively performed, and the conductive layer is patterned to form a source / drain electrode. After that, the doped semiconductor layer is etched using the source / drain electrodes as a mask to form an ohmic contact layer, thereby eliminating the pre-deposition cleaning operation for forming the conductive layer and separating the ohmic contact layer portion at the upper end of the channel region. It is to provide a liquid crystal display device and a method of manufacturing the simplified manufacturing process.
또한, 본 발명은 상기 액정표시장치의 제조방법이 실현될 수 있도록, 도핑된 반도체층을 형성하기 위한 체임버와 도전층을 형성하기 위한 체임버를 진공상태로 연결함으로써, 진공조건이 깨지지 않는 조건하에서 상기 공정들을 실시할 수 있는 액정표시장치 제조장비를 제공하고자 한다.In addition, the present invention provides a method of manufacturing the liquid crystal display device, by connecting the chamber for forming the doped semiconductor layer and the chamber for forming the conductive layer in a vacuum state, so that the vacuum conditions are not broken. An object of the present invention is to provide an LCD manufacturing apparatus capable of performing the processes.
본 발명은 절연기판에 제 1 방향으로 연장되는 주사선과, 상기 제 1 방향에 교차하는 제 2 방향으로 연장되는 신호선과, 상기 신호선과 상기 주사선의 교차부에 위치하되, 상기 주사선에 연장되는 게이트전극과, 상기 신호선에 연장되는 소오스전극과, 상기 소오스전극에 대응되는 드레인전극과, 상기 게이트전극에 중첩되어 상기 소오스전극과 드레인전극에 연결되는 활성층을 구비하는 박막트랜지스터와, 상기 박막트랜지스터의 드레인전극에 연결되는 화소전극을 포함하는 액정표시장치에 있어서, 상기 활성층은 상기 신호선, 소오스전극, 드레인전극 및 게이트전극에 중첩되도록 형성되는 것이 특징인 액정표시장치이다.According to an embodiment of the present invention, a scan line extending in a first direction on a insulating substrate, a signal line extending in a second direction crossing the first direction, and a gate electrode positioned at an intersection of the signal line and the scan line, and extending on the scan line And a thin film transistor including a source electrode extending over the signal line, a drain electrode corresponding to the source electrode, an active layer overlapping the gate electrode and connected to the source electrode and the drain electrode, and a drain electrode of the thin film transistor. The liquid crystal display device comprising a pixel electrode connected to the liquid crystal display device, wherein the active layer is formed to overlap the signal line, the source electrode, the drain electrode, and the gate electrode.
본 발명은 절연기판에 주사선 및 주사선에 연장되는 게이트전극을 형성하는 공정과, 상기 주사선 및 게이트전극을 덮는 제 1 절연막, 도핑된 반도체층, 도전층을 순차적으로 형성하는 공정과, 상기 도전층에 사진식각공정을 진행하여 신호선, 소오스전극 및 드레인전극을 형성하는공정과, 상기 도핑된 반도체층에 상기 신호선, 소오스전극 및 드레인전극을 마스크로하는 식각공정을 진행하여 오믹콘택층을 형성하는 공정과, 상기 반도체층에 사진식각공정을 진행하여 활성층을 형성하는 공정과, 상기 노출된 기판 전면을 덮되, 상기 드레인전극의 일부를 노출시키는 제 2 절연막을 형성하는 공정과, 상기 드레인전극에 연결되는 화소전극을 형성하는 공정을 포함하는 액정표시장치의 제조방법이다. 이 때, 본 발명은 상기 도핑된 반도체층을 형성한 후, 진공상태를 유지한 상태에서 상기 도전층을 형성하는 것을 특징으로 하고 있다.The present invention provides a process for forming a scan line and a gate electrode extending in the scan line on an insulating substrate, a step of sequentially forming a first insulating film, a doped semiconductor layer, and a conductive layer covering the scan line and the gate electrode; Forming a ohmic contact layer by performing a photolithography process to form a signal line, a source electrode, and a drain electrode; and an etching process using the signal line, a source electrode, and a drain electrode as a mask on the doped semiconductor layer; Forming an active layer by performing a photolithography process on the semiconductor layer, forming a second insulating layer covering the entire surface of the exposed substrate and exposing a part of the drain electrode, and a pixel connected to the drain electrode; It is a manufacturing method of a liquid crystal display device including the process of forming an electrode. In this case, the present invention is characterized in that after forming the doped semiconductor layer, the conductive layer is formed in a vacuum state.
본 발명은 절연기판에 주사선 및 주사선에 연장되는 게이트전극을 형성하는 공정과, 상기 주사선 및 게이트전극을 덮는 제 1 절연막, 반도체층, 도핑된 반도체층, 도전층을 순차적으로 형성하는 공정과, 상기 도전층에 사진식각공정을 진행하여 신호선, 소오스전극 및 드레인전극을 형성하는공정과, 상기 도핑된 반도체층에 상기 신호선, 소오스전극 및 드레인전극을 마스크로하는 식각공정을 진행하여 오믹콘택층을 형성하는 공정과, 상기 반도체층에 사진식각공정을 진행하여 활성층을 형성하는 공정과, 상기 노출된 기판 전면을 덮되, 상기 드레인전극의 일부를 노출시키는 제 2 절연막을 형성하는 공정과, 상기 드레인전극에 연결되는 화소전극을 형성하는 공정을 포함하는 액정표시장치의 제조공정을 진행하기 위한 액정표시장치 제조장비에 있어서, 상기 도핑된 반도체층을 형성하기 위한 제 1 체임버와 상기 도전층을 형성하기 위한 제 2 체임버를 진공상태로 연결하는 것을 특징으로 한다.The present invention provides a process of forming a scan line and a gate electrode extending in the scan line on an insulating substrate, sequentially forming a first insulating film, a semiconductor layer, a doped semiconductor layer, and a conductive layer covering the scan line and the gate electrode; A photolithography process is performed on the conductive layer to form a signal line, a source electrode, and a drain electrode, and an etch process using the signal line, the source electrode, and a drain electrode as a mask is performed on the doped semiconductor layer to form an ohmic contact layer. Forming an active layer by performing a photolithography process on the semiconductor layer, forming a second insulating film covering the entire surface of the exposed substrate and exposing a part of the drain electrode; In the liquid crystal display device manufacturing equipment for proceeding the manufacturing process of the liquid crystal display device comprising the step of forming a pixel electrode connected to Characterized in that for connecting the second chamber for forming the conductive layer and the first chamber for forming the doped semiconductor layer in a vacuum state.
도 1a부터 도 1d는 종래의 제 1 기술에 의한 액정표시장치의 제조공정 단면도1A through 1D are cross-sectional views of a manufacturing process of a liquid crystal display device according to a conventional first technique.
도 2a부터 도 2e는 종래의 제 2 기술에 의한 액정표시장치의 제조공정 단면도2A through 2E are cross-sectional views of a manufacturing process of a liquid crystal display device according to a second conventional technology.
도 3은 종래 기술의 문제점을 설명하기 위한 도면3 is a view for explaining the problems of the prior art.
도 4a부터 도 4d는 본 발명의 제 1 실시예에 따른 액정표시장치의 제조공정 단면도4A through 4D are cross-sectional views illustrating a manufacturing process of a liquid crystal display device according to a first embodiment of the present invention.
도 5a부터 도 5e는 본 발명의 제 2 실시예에 따른 액정표시장치의 제조공정 단면도5A through 5E are cross-sectional views of a manufacturing process of a liquid crystal display according to a second exemplary embodiment of the present invention.
도 6은 본 발명에 따른 액정표시장치의 평면도6 is a plan view of a liquid crystal display according to the present invention.
도 7a와 도 7b는 본 발명에 따른 액정표시 제조장비에서 체임버의 진공연결상태를 설명하기 위한 개략도7A and 7B are schematic views for explaining a vacuum connection state of a chamber in a liquid crystal display manufacturing apparatus according to the present invention.
도 4a부터 도 4d는 본 발명에 따른 액정표시장치의 제조공정의 제 1 실시예를 설명하기 위하여 BCE(Back Channel Etch)형 액정표시장치의 제조공정 단면도를 나타낸 것이다. 본 발명의 제조공정을 평면도인 도 6을 참조하여 설명한다.4A through 4D are cross-sectional views illustrating a manufacturing process of a back channel etching (BCE) type liquid crystal display device in order to explain a first embodiment of the manufacturing process of the liquid crystal display device according to the present invention. The manufacturing process of this invention is demonstrated with reference to FIG.
도 4a를 참조하면, 세정공정에 의하여 클리닝된 절연기판(400)에 제 1 도전층을 형성한 후, 제 1 도전층을 사진식각공정에 의하여 패터닝하여 게이트전극(41)을 형성한다. 이어서, 노출된 기판 전면에 증착전세정(pre-depo cleaning)을 한 후, 제 1 절연막(42)과 반도체층(43ℓ)과 도핑된 반도체층(44ℓ)을 연속적으로 형성(이하 "A"공정이라 함)한다. 이 층들의 형성공정은 PECVD 체임버에서 이루어지므로, 공정중에는 진공상태가 유지된다.Referring to FIG. 4A, after the first conductive layer is formed on the insulating substrate 400 cleaned by the cleaning process, the first conductive layer is patterned by a photolithography process to form the gate electrode 41. Subsequently, after the pre-depo cleaning is performed on the entire surface of the exposed substrate, the first insulating film 42, the semiconductor layer 43L, and the doped semiconductor layer 44L are successively formed (hereinafter, referred to as "A" process). Is called). The formation of these layers takes place in a PECVD chamber, so that vacuum is maintained during the process.
이 후, 상기 증착공정공정이 진행되었던 공정환경인 진공상태를 깨뜨리지 않는 조건하에서 공정중인 기판을 스퍼터링 체임버로 이동시켜, 스퍼터링 체임버에서 도전물질을 증착하여 제 2 도전층(45ℓ)을 형성(이하 "B"공정이라 함)한다.Subsequently, the substrate under process is moved to a sputtering chamber under conditions that do not break the vacuum state, which is the process environment in which the deposition process was performed, and a second conductive layer 45L is formed by depositing a conductive material in the sputtering chamber (hereinafter referred to as " B "process).
언급한 바와 같이, 상기 "A"공정과 "B"공정은 다른 구비조건을 만족시키는 별도의 체임버에서 진공상태로 진행된다. 그런데 두 체임버를 이와 같이, 진공상태로 연결할 경우, 상기 "A"공정과 "B"공정은 진공을 유지한 상태로 연속적으로 진행할 수 있다. 따라서, 도핑된 반도체층(44ℓ)과 제 2 도전층(45ℓ)을 형성할 때, 체임버와 체임버의 변경으로 인하여 외부에 노출됨으로써 야기되는 두 층 사이의 자연산화막 형성을 방지할 수 있다.As mentioned, the " A " process and the " B " process are carried out in vacuum in separate chambers that satisfy different preconditions. However, when the two chambers are connected in a vacuum state as described above, the "A" process and the "B" process may be continuously performed while maintaining the vacuum. Therefore, when forming the doped semiconductor layer 44L and the second conductive layer 45L, it is possible to prevent the formation of a natural oxide film between two layers caused by exposure to the outside due to the change of the chamber and the chamber.
이 때, 도 7a에 보인 바와 같이, "A"공정을 위한 "A" 체임버(CHAMBER A)와 "B"공정을 위한 "B" 체임버(CHAMBER B)를 진공조건을 유지한 상태에서 인라인(in-line) 방식으로 연결하고, "A" 체임버(CHAMBER A)에서 "A"공정을 진행한 후, 진공상태에서 기판을 "B" 체임버(CHAMBER B)로 옮긴 후, "B"공정을 진행할 수 있다. 따라서, "A"공정과 "B"공정은 진공상태에서 연속적으로 진행될 수 있다. 또한, 도 7b에 보인 바와 같이, "A"공정과 "B"공정을 위한 체임버, 예를 들어, "A" 체임버(CHAMBER A)와 "B" 체임버(CHAMBER B)와 로드부(LOAD)와 언로드부(UNLOAD)를 클러스터(cluster) 방식으로 배열하되, 이들 체임버들을 연결하는 내부공간을 진공상태로 만들어줌으로써, "A"공정과 "B"공정을 진공상태에서 연속적으로 진행할 수 있다.In this case, as shown in FIG. 7A, the "A" chamber (CHAMBER A) for the "A" process and the "B" chamber (CHAMBER B) for the "B" process are inlined while maintaining a vacuum condition. -line) method, process "A" in "A" chamber (CHAMBER A), transfer substrate to "B" chamber (CHAMBER B) under vacuum, and proceed with process "B". have. Therefore, the "A" process and the "B" process can proceed continuously in a vacuum state. In addition, as shown in FIG. 7B, the chambers for the "A" process and the "B" process, for example, the "A" chamber (CHAMBER A) and the "B" chamber (CHAMBER B) and the load unit (LOAD) and By arranging the unload unit UNLOAD in a cluster manner, by making the internal spaces connecting these chambers into a vacuum state, the "A" process and the "B" process can be continuously performed in a vacuum state.
도 4b를 참조하면, 제 2 도전층을 사진식각공정에 의하여 패터닝하여 신호선(45L), 소오스전극(45S) 및 드레인전극(45D)을 형성한다. 그 다음, 이 신호선(45L), 소오스전극(45S) 및 드레인전극(45D)을 마스크로하여 그 하단에 있는 도핑된 반도체층을 식각하여 오믹콘택층(44)을 형성한다. 이 경우, 종래의 액정표시장치 제조방법에서는 채널영역의 상단에 위치하는 오믹콘택층 부분을 제거하기 위한 별도의 식각공정을 실시하였지만, 본 발명에서는 한 번의 식각공정으로 오믹콘택층(44)의 분리작업을 실행할 수 있다. 따라서 식각공정을 한단계 줄일 수 있다.Referring to FIG. 4B, the second conductive layer is patterned by a photolithography process to form a signal line 45L, a source electrode 45S, and a drain electrode 45D. Next, the ohmic contact layer 44 is formed by etching the doped semiconductor layer at the bottom using the signal line 45L, the source electrode 45S and the drain electrode 45D as a mask. In this case, the conventional liquid crystal display device manufacturing method performed a separate etching process to remove the ohmic contact layer located on the upper end of the channel region, in the present invention, the ohmic contact layer 44 is separated in one etching process. You can run the job. Therefore, the etching process can be reduced by one step.
도 4c를 참조하면, 노출된 반도체층을 사진식각공정에 의하여 패터닝하여 활성층(43)을 형성한다. 이 때, 활성층(43)은 도 6에 보인 평면도와 같이, 소오스전극(45S)과 드레인전극(45D) 사이에 해당하는 부분인 채널영역이 잔존할 수 있도록 패터닝한다. 이 때, 신호선(45L), 소오스전극(45S) 및 드레인전극(45D)에 중첩되는 부분도 활성층(43)으로 잔류된다.Referring to FIG. 4C, the exposed semiconductor layer is patterned by a photolithography process to form an active layer 43. At this time, the active layer 43 is patterned such that the channel region, which is a portion corresponding to the source electrode 45S and the drain electrode 45D, remains as shown in the plan view shown in FIG. 6. At this time, the portion overlapping the signal line 45L, the source electrode 45S and the drain electrode 45D also remains in the active layer 43.
도 4d를 참조하면, 노출된 기판 전면에 증착전세정을 실시한 후, 제 2 절연막(46)을 형성한다. 이어서, 제 2 절연막을 사진식각공정에 의하여 패터닝하여 드레인전극(45D)의 일부를 노출시키는 콘택홀(H)을 형성한다. 이 후, 노출된 기판 전면에 증착전세정을 진행한 후, 투명도전층을 형성하고, 투명도전층을 사진식각공정에 의하여 패터닝하여 화소전극(47)을 형성한다.Referring to FIG. 4D, after the deposition pre-cleaning is performed on the exposed substrate, the second insulating layer 46 is formed. Subsequently, the second insulating film is patterned by a photolithography process to form a contact hole H exposing a part of the drain electrode 45D. Subsequently, after the deposition pretreatment is performed on the entire surface of the exposed substrate, a transparent conductive layer is formed, and the transparent conductive layer is patterned by a photolithography process to form the pixel electrode 47.
도 5a부터 도 5e는 본 발명에 따른 액정표시장치의 제조공정의 제 2 실시예를 나타낸 것이다. 본 발명의 제조공정을 평면도인 도 6을 참조하여 설명한다.5A to 5E illustrate a second embodiment of the manufacturing process of the liquid crystal display according to the present invention. The manufacturing process of this invention is demonstrated with reference to FIG.
도 5a를 참조하면, 세정공정에 의하여 클리닝된 절연기판(500)에 제 1 도전층을 형성한 후, 제 1 도전층을 사진식각공정에 의하여 패터닝하여 게이트전극(51)을 형성한다. 이어서, 노출된 기판 전면에 증착전세정(pre-depo cleaning)을 한 후, 제 1 절연막(52)과 반도체층(53ℓ)과 제 2 절연막을 연속적으로 형성한다. 이어서, 제 2 절연막을 사진식각공정에 의하여 패터닝하여 에치스토퍼(59)를 형성한다.Referring to FIG. 5A, after forming a first conductive layer on the insulating substrate 500 cleaned by the cleaning process, the first conductive layer is patterned by a photolithography process to form the gate electrode 51. Subsequently, after pre-depo cleaning is performed on the entire surface of the exposed substrate, the first insulating film 52, the semiconductor layer 53L and the second insulating film are successively formed. Subsequently, the second insulating film is patterned by a photolithography process to form an etch stopper 59.
도 5b를 참조하면, 노출된 기판 전면에 증착전세정을 실시한 후, 도핑된 반도체층(54ℓ)을 형성(이하 "A"공정이라 함)한다. 도핑된 반도체층의 형성은 PECVD 체임버에서 이루어지므로, 공정중에는 진공상태가 유지된다.Referring to FIG. 5B, after pre-deposition cleaning is performed on the entire surface of the exposed substrate, a doped semiconductor layer 54 L is formed (hereinafter referred to as “A” process). The formation of the doped semiconductor layer takes place in the PECVD chamber, so that vacuum is maintained during the process.
이 후, 상기 증착공정공정이 진행되었던 공정환경인 진공상태를 깨뜨리지 않는 조건하에서 공정중인 기판을 스퍼터링 체임버로 이동시켜, 스퍼터링 체임버에서 도전물질을 증착하여 제 2 도전층(55ℓ)을 증착(이하 "B"공정이하 함)한다.Subsequently, the substrate being processed is moved to a sputtering chamber under conditions that do not break the vacuum state, which is the process environment in which the deposition process has been performed, and the second conductive layer 55L is deposited by depositing a conductive material in the sputtering chamber (hereinafter, referred to as ""). B "process or below).
언급한 바와 같이, 상기 "A"공정과 "B"공정은 다른 구비조건을 만족시키는 별도의 체임버에서 진공상태로 진행된다. 그런데 두 체임버를 이와 같이, 진공상태로 연결할 경우, 상기 "A"공정과 "B"공정은 진공을 유지한 상태로 연속적으로 진행할 수 있다. 따라서, 도핑된 반도체층(54ℓ)과 제 2 도전층(55ℓ)을 형성할 때, 체임버와 체임버의 변경으로 인하여 외부에 노출됨으로써 야기되는 두 층 사이의 자연산화막 형성을 방지할 수 있다.As mentioned, the " A " process and the " B " process are carried out in vacuum in separate chambers that satisfy different preconditions. However, when the two chambers are connected in a vacuum state as described above, the "A" process and the "B" process may be continuously performed while maintaining the vacuum. Therefore, when forming the doped semiconductor layer 54L and the second conductive layer 55L, it is possible to prevent the formation of a natural oxide film between the two layers caused by exposure to the outside due to the change of the chamber and the chamber.
"A"공정과 "B"공정을 위한 제조장비의 구성은 본 발명의 제 1 실시예에서 이미 언급했으므로 이에 대한 상술은 생략한다.Since the construction of the manufacturing equipment for the "A" process and the "B" process has already been mentioned in the first embodiment of the present invention, the description thereof is omitted.
도 5c를 참조하면, 제 2 도전층을 사진식각공정에 의하여 패터닝하여 신호선(55L), 소오스전극(55S) 및 드레인전극(55D)을 형성한 후, 이 신호선(55L), 소오스전극(55S) 및 드레인전극(55D)을 마스크로하여 그 하단에 있는 도핑된 반도체층을 식각하여 오믹콘택층(54)을 형성한다. 이 때, 소오스전극(55S)과 드레인전극(55D)의 사이에 위치하는 오믹콘택층 부분도 함게 제거되며, 에치스토퍼(59)의 존재로 반도체층의 손상을 방지할 수 있다. 이 경우, 종래의 액정표시장치 제조방법에서는 채널영역의 상단에 위치하는 오믹콘택층 부분을 제거하기 위한 별도의 식각공정을 실시하지만, 이 실시예에서는 언급한 바와 같이, 한 번의 식각공정으로 오믹콘택층의 분리작업을 실행할 수 있다. 따라서 식각공정을 한단계 줄일 수 있다.Referring to FIG. 5C, the second conductive layer is patterned by a photolithography process to form a signal line 55L, a source electrode 55S, and a drain electrode 55D, and then the signal line 55L and the source electrode 55S. The ohmic contact layer 54 is formed by etching the doped semiconductor layer at the bottom thereof using the drain electrode 55D as a mask. At this time, the portion of the ohmic contact layer positioned between the source electrode 55S and the drain electrode 55D is also removed, and damage to the semiconductor layer can be prevented due to the presence of the etch stopper 59. In this case, the conventional liquid crystal display device manufacturing method performs a separate etching process to remove the ohmic contact layer portion located on the upper end of the channel region, but as mentioned in this embodiment, the ohmic contact in one etching process Separation of layers can be performed. Therefore, the etching process can be reduced by one step.
도 5d를 참조하면, 노출된 반도체층을 사진식각공정에 의하여 패터닝하여 활성층(53)을 형성한다. 이 때, 활성층(53)은 도 6에 보인 평면도와 같이, 소오스전극(55S)과 드레인전극(55D) 사이에 해당하는 부분인 채널영역이 잔존할 수 있도록 패터닝한다. 이 때, 신호선(55L), 소오스전극(55S) 및 드레인전극(55D)에 중첩되는 부분도 활성층(53)으로 잔류된다.Referring to FIG. 5D, the exposed semiconductor layer is patterned by a photolithography process to form an active layer 53. At this time, the active layer 53 is patterned such that the channel region, which is a portion corresponding to the source electrode 55S and the drain electrode 55D, remains as shown in the plan view shown in FIG. 6. At this time, the portion overlapping the signal line 55L, the source electrode 55S and the drain electrode 55D also remains in the active layer 53.
도 5e를 참조하면, 노출된 기판 전면에 증착전세정을 실시한 후, 제 2 절연막(56)을 형성한다. 이어서, 제 2 절연막을 사진식각공정에 의하여 패터닝하여 드레인전극(55D)의 일부를 노출시키는 콘택홀(H)을 형성한다. 이 후, 노출된 기판 전면에 증착전세정을 진행한 후, 투명도전층을 형성하고, 투명도전층을 사진식각공정에 의하여 패터닝하여 화소전극(57)을 형성한다.Referring to FIG. 5E, after the deposition pre-cleaning is performed on the exposed substrate, the second insulating layer 56 is formed. Subsequently, the second insulating film is patterned by a photolithography process to form a contact hole H exposing a part of the drain electrode 55D. Subsequently, after the deposition pre-cleaning is performed on the entire surface of the exposed substrate, a transparent conductive layer is formed, and the transparent conductive layer is patterned by a photolithography process to form a pixel electrode 57.
도 6은 상술한 본 발명에 따라 구현된 액정표시장치의 평면도이다.6 is a plan view of a liquid crystal display device implemented according to the present invention described above.
도면을 보면 알수 있듯이, 절연기판(도면 미표시)에 제 1 방향으로 연장된 신호선(65L)과 제 2 방향으로 연장된 주사선(61L)이 교차하여 화소를 이루고 있다. 주사선(61L)은 게이트전극(61G)이 연장되어 돌출되어 있고, 신호선(65L)은 소오스전극(65S) 부분이 돌출되어 있다. 또한, 드레인전극(65D)이 소오스전극(65S)에 대응되어 형성되어 있다. 활성층(63)은 채널영역을 이루는 부분이 게이트전극(65G)에 중첩되고, 소오스/드레인 전극(65S)(65D)에 중첩되어 있으며, 제조공정에서도 알 수 있듯이 신호선(65L) 및 소오스/드레인 전극(65S)(65D)을 형성하고 나서, 그 하단에 위치하는 반도체층을 사진식각공정에 의하여 형성하는 것이기 때문에 이들을 따라서도 패턴이 형성된다. 그리고, 드레인전극(65D)에 연결된 화소전극(67)이 화소의 전 부분에 형성되어 있다.As can be seen from the drawing, the signal line 65L extending in the first direction and the scanning line 61L extending in the second direction cross the insulating substrate (not shown) to form a pixel. The gate line 61G extends and protrudes from the scan line 61L, and the source electrode 65S protrudes from the signal line 65L. Further, the drain electrode 65D is formed corresponding to the source electrode 65S. The active layer 63 has a portion of the channel region overlapping the gate electrode 65G and the source / drain electrodes 65S and 65D, and as can be seen from the manufacturing process, the signal line 65L and the source / drain electrode Since the semiconductor layer located at the lower end after the formation of the (65S) and the 65D is formed by a photolithography process, a pattern is also formed along these. And the pixel electrode 67 connected to the drain electrode 65D is formed in the whole part of a pixel.
본 발명은 오믹콘택층을 위한 반도체층을 형성하기 위한 공정과 소오스/드레인을 위한 도전층을 형성하기 위한 공정을 진공상태에서 연속적으로 진행한다. 따라서 체임버의 변경으로 인하여 기판이 외부에 노출됨으로써 오믹콘택층과 소오스/드레인 전극의 경계에 형성되는 자연산화막의 생성을 방지함으로써, 오믹콘택층과 도전층의 접촉저항을 감소시킬 수 있으며, 도전층의 형성공정 전에 실시되는 증착전세정 작업을 생략할 수 있다. 또한, 채널영역의 상단의 오믹콘택층 부분을 제거하기 위한 별도의 식각공정을 생략할 수 있다.In the present invention, a process for forming a semiconductor layer for an ohmic contact layer and a process for forming a conductive layer for a source / drain are continuously performed in a vacuum. Therefore, by changing the chamber, the substrate is exposed to the outside, thereby preventing the formation of a natural oxide film formed at the boundary between the ohmic contact layer and the source / drain electrodes, thereby reducing the contact resistance between the ohmic contact layer and the conductive layer. It is possible to omit the pre-deposition cleaning work carried out before the formation process. In addition, a separate etching process for removing the ohmic contact layer portion of the upper portion of the channel region may be omitted.
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US7683996B2 (en) | 1999-09-07 | 2010-03-23 | Hitachi, Ltd. | Liquid crystal display device |
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TWI550071B (en) | 2011-03-25 | 2016-09-21 | 捷恩智股份有限公司 | Orthoester compound,liquid crystal composition and liquid crystal display device |
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Cited By (17)
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US7683996B2 (en) | 1999-09-07 | 2010-03-23 | Hitachi, Ltd. | Liquid crystal display device |
US7692748B2 (en) | 1999-09-07 | 2010-04-06 | Hitachi, Ltd. | Liquid crystal display device |
US7697100B2 (en) | 1999-09-07 | 2010-04-13 | Hitachi, Ltd. | Liquid crystal display device |
US7705949B2 (en) | 1999-09-07 | 2010-04-27 | Hitachi, Ltd. | Liquid crystal display device |
US7733455B2 (en) | 1999-09-07 | 2010-06-08 | Hitachi, Ltd. | Liquid crystal display device |
US7936429B2 (en) | 1999-09-07 | 2011-05-03 | Hitachi, Ltd. | Liquid crystal display device |
US8035786B2 (en) | 1999-09-07 | 2011-10-11 | Hitachi, Ltd. | Liquid crystal display device |
US8045116B2 (en) | 1999-09-07 | 2011-10-25 | Hitachi, Ltd. | Liquid crystal display device |
US8218119B2 (en) | 1999-09-07 | 2012-07-10 | Hitachi Displays, Ltd. | Liquid crystal display device |
US8218118B2 (en) | 1999-09-07 | 2012-07-10 | Hitachi Displays, Ltd. | Liquid crystal display device |
US8345205B2 (en) | 1999-09-07 | 2013-01-01 | Hitachi Displays, Ltd. | Liquid Crystal display device |
US8493537B2 (en) | 1999-09-07 | 2013-07-23 | Hitachi Displays, Ltd. | Liquid crystal display device |
US8564752B2 (en) | 1999-09-07 | 2013-10-22 | Hitachi Displays, Ltd. | Liquid crystal display device |
US8964155B2 (en) | 1999-09-07 | 2015-02-24 | Japan Display Inc. | Liquid crystal display device |
US9488883B2 (en) | 1999-09-07 | 2016-11-08 | Japan Display Inc. | Liquid crystal display device |
US10139687B2 (en) | 1999-09-07 | 2018-11-27 | Japan Display Inc. | Liquid crystal display device |
US10634961B2 (en) | 1999-09-07 | 2020-04-28 | Japan Display Inc. | Liquid crystal display device |
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