KR101121988B1 - Method Of Fabricating Thin Film Transistor Substrate And Method of Fabricating Flat Display Panel Using The Same - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor substrate capable of simplifying the process in a three mask process and a method of manufacturing a flat panel display panel using the same.

A method of manufacturing a thin film transistor substrate of the present invention includes a first mask process of forming a gate pattern group including a gate line and a gate electrode on a substrate; After forming the gate insulating film on the substrate after the first mask process, a second mask for forming a source / drain pattern group including a data line, a source electrode and a drain electrode, and a semiconductor layer including an active layer and an ohmic contact layer Process; And forming a pixel hole on the substrate after the second mask process, and forming a pixel electrode in the pixel hole, wherein the third mask process includes a passivation layer on the substrate after the second mask process. Forming a front surface; Forming a photoresist pattern on the protective film; Etching the passivation layer and gate insulating layer of the pixel region exposed through the photoresist pattern to form the pixel hole; Cleaning the substrate on which the pixel hole is formed; Forming a transparent conductive film on the protective film having the photoresist pattern; And removing the photoresist pattern and the transparent conductive layer thereon to form a pixel electrode by a lift-off process.

Description

Method of manufacturing a thin film transistor substrate and a method of manufacturing a flat panel display panel using the same {Method Of Fabricating Thin Film Transistor Substrate And Method of Fabricating Flat Display Panel Using The Same}             

1 is a perspective view illustrating a conventional liquid crystal display panel.

2 is a plan view partially illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention.

FIG. 3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 2 taken along lines II ′, II-II ′, and III-III ′.

4A and 4B are plan views and cross-sectional views illustrating a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

5A and 5B are plan and cross-sectional views illustrating a second mask process in the method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention.

6A to 6D are cross-sectional views for describing a second mask process of the present invention in detail.

7A and 7B are plan and cross-sectional views illustrating a third mask process in the method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention.                 

8A and 8E are cross-sectional views for describing a third mask process of the present invention in detail.

9A and 9B are diagrams for describing the presence or absence of defects according to the presence or absence of the cleaning process before the lift-off process.

 <Description of Symbols for Main Parts of Drawings>

102: gate line 104: data line

106: thin film transistor 108: gate electrode

110: source electrode 112: drain electrode

114: active layer 118: pixel electrode

126: gate pad portion 128: gate pad lower electrode

130 and 138: contact hole 132: gate pad upper electrode

134: data pad 136: data pad lower electrode

140: data pad upper electrode 142: substrate

144 gate insulating film 148 ohmic contact layer

150: protective film 152: photoresist pattern

160: pixel hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor substrate and a method of manufacturing a flat panel display panel using the same, and more particularly, to a method of manufacturing a thin film transistor substrate that can simplify the process and a method of manufacturing a flat panel display panel using the same.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

As shown in FIG. 1, the liquid crystal panel includes a thin film transistor substrate 70 and a color filter substrate 80 that face each other with the liquid crystal 16 therebetween.

The thin film transistor substrate 70 includes a gate line 2 and a data line 4, a thin film transistor 30 formed of a switch element at each intersection of the gate lines 2 and the data lines 4, and And pixel electrodes 32 and the like formed in liquid crystal cell units connected to the thin film transistors 30 and the alignment films coated thereon. The gate lines 2 and the data lines 4 are supplied with signals from the driving circuits through the pads 50 and 60, respectively. The thin film transistor supplies a pixel signal supplied to the data line 4 to the pixel electrode in response to a scan signal supplied to the gate line 2.

In the liquid crystal panel, the thin film transistor substrate includes a semiconductor process and also requires a plurality of mask processes, and thus, the manufacturing process is complicated, which is an important cause of an increase in the manufacturing cost of the liquid crystal panel. In order to solve this problem, the thin film transistor substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, recently, there is a need for a thin film transistor substrate and a method of manufacturing the same, which can reduce a manufacturing cost by reducing a manufacturing process of a thin film transistor substrate.

Accordingly, an object of the present invention is to provide a method for manufacturing a thin film transistor substrate which can simplify the process and a method for manufacturing a flat panel display panel using the same.

In order to achieve the above object, a method of manufacturing a thin film transistor substrate according to the present invention includes a first mask process for forming a gate pattern group including a gate line and a gate electrode on the substrate; After forming the gate insulating film on the substrate after the first mask process, a second mask for forming a source / drain pattern group including a data line, a source electrode and a drain electrode, and a semiconductor layer including an active layer and an ohmic contact layer Process; And forming a pixel hole on the substrate after the second mask process, and forming a pixel electrode in the pixel hole, wherein the third mask process includes a passivation layer on the substrate after the second mask process. Forming a front surface; Forming a photoresist pattern on the protective film; Etching the passivation layer and gate insulating layer of the pixel region exposed through the photoresist pattern to form the pixel hole; Cleaning the substrate on which the pixel hole is formed; Forming a transparent conductive film on the protective film having the photoresist pattern; And removing the photoresist pattern and the transparent conductive layer thereon to form a pixel electrode by a lift-off process.

The cleaning of the substrate on which the pixel hole is formed may include cleaning the substrate on which the pixel hole is formed using ultrapure water.

The cleaning of the substrate on which the pixel hole is formed may include cleaning the substrate on which the pixel hole is formed by plasma treatment using He.

The protective layer and the gate insulating layer are etched with an etching gas including at least one of SF ₆ , Cl ₂ , HCl, CF ₄ , C ₃ H ₅ , and the like.

The cleaning of the substrate on which the pixel hole is formed may include removing F and Cl based ionic components remaining on the substrate on which the pixel hole is formed.

The first mask process may include forming a gate pad lower electrode connected to the gate line, and the third mask process may include a contact hole penetrating through the passivation layer and the gate insulating layer to expose the gate pad lower electrode, and the contact thereof. And forming a gate pad upper electrode bordering the passivation layer and connected to the gate pad lower electrode in a hole.

The third mask process may include forming a data pad lower electrode connected to a data line, and the fourth mask process may include a contact hole penetrating through the passivation layer and a data pad lower electrode, and the protective layer in the contact hole. And forming a data pad upper electrode that forms a boundary and is connected to a side of the data pad lower electrode.

In order to achieve the above object, a method of manufacturing a flat panel display panel according to the present invention comprises the steps of forming a first thin film on the entire surface; Forming a photoresist pattern on the first thin film; Etching the first thin film using the photoresist pattern to form a first thin film pattern; Cleaning the substrate on which the first thin film pattern is formed; Forming a second thin film on the photoresist pattern remaining on the cleaned substrate; And removing the photoresist pattern and the second thin film thereon by a lift-off process to form a second thin film pattern.

Cleaning the substrate on which the first thin film pattern is formed includes cleaning the substrate on which the first thin film pattern is formed using ultrapure water.

The cleaning of the substrate on which the first thin film pattern is formed may include cleaning the substrate on which the first thin film pattern is formed by plasma treatment using He.

The forming of the first thin film pattern by etching the first thin film using the photoresist pattern includes at least one of SF ₆ , Cl ₂ , HCl, CF ₄ , C ₃ H ₅ , and the like. And etching the etching gas to form the first thin film pattern.

The cleaning of the substrate on which the first thin film pattern is formed may include removing F and Cl based ionic components remaining on the substrate on which the first thin film pattern is formed.

Other objects and advantages of the present invention will become apparent from the following description of preferred embodiments of the present invention with reference to the accompanying drawings.

2 is a plan view illustrating a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIG. 3 is a line along the lines I-I ', II-II', and III-III 'of the thin film transistor substrate shown in FIG. It is sectional drawing cut out.

2 and 3 include a gate line 102 and a data line 104 formed to intersect a gate insulating layer 144 therebetween on a lower substrate 142, and a thin film transistor adjacent to an intersection thereof. 106 and the pixel electrode 118 formed in the pixel area provided by the crossing structure. The thin film transistor substrate includes a gate pad 126 connected to the gate line 102 and a data pad 134 connected to the data line 104.

The thin film transistor 106 keeps the pixel signal supplied to the data line 104 charged to the pixel electrode 118 in response to the scan signal supplied to the gate line 102. For this purpose, the thin film transistor 106 is positioned to face the gate electrode 108 connected to the gate line 102, the source electrode 110 connected to the data line 104, and the source electrode 110 to face the pixel electrode ( An active layer 114 formed to overlap the gate electrode 108 with the drain electrode 112 and the gate insulating layer 144 connected to the 118 interposed therebetween to form a channel between the source electrode 110 and the drain electrode 112. ) And an ohmic contact layer 146 formed on the active layer 114 except for the channel portion for ohmic contact with the source electrode 110 and the drain electrode 112.

The active layer 114 and the ohmic contact layer 146 are also formed to overlap the data line 104 and the data pad lower electrode 136.

The pixel hole 160 penetrating the passivation layer 150 and the gate insulating layer 144 is formed in the pixel region defined by the intersection of the gate line 102 and the data line 104. The pixel electrode 118 is formed bordering the passivation layer 150 in the pixel hole 160. The pixel electrode 118 is laterally connected to the drain electrode 112 partially etched when the pixel hole 160 is formed. In this case, the pixel electrode 118 overlaps a portion of the active layer 114 exposed by the etched drain electrode 122 or a portion of the gate insulating layer 144. The pixel electrode 118 charges the pixel signal supplied from the thin film transistor 106 to generate a potential difference with a common electrode formed on a color filter substrate (not shown). Due to the potential difference, the liquid crystals positioned on the thin film transistor substrate and the color filter substrate are rotated by dielectric anisotropy, and the amount of light incident through the pixel electrode 118 from a light source (not shown) is controlled to be transmitted to the color filter substrate.

The gate line 102 is connected to a gate driver (not shown) through the gate pad 126. The gate pad 126 includes a gate pad lower electrode 128 extending from the gate line 102 and a gate pad upper electrode 132 connected over the gate pad lower electrode 128. Here, the gate pad upper electrode 132 is formed in the first contact hole 130 penetrating the passivation layer 150 and the gate insulating layer 144 and is connected to the gate pad lower electrode 128.

The data line 104 is connected to a data driver (not shown) through the data pad 134. The data pad 134 includes a data pad lower electrode 136 extending from the data line 104 and a data pad upper electrode 140 connected to the data pad lower electrode 136. Here, the data pad upper electrode 140 is formed in the second contact hole 138 penetrating the passivation layer 150 and the data pad lower electrode 136 and is connected to the side surface of the data pad lower electrode 136. In addition, when the second contact hole 138 is formed, the ohmic contact layer 146 and the active layer 114 under the data pad lower electrode 136 are etched so that the data pad upper electrode 140 is in contact with the gate insulating layer 144. , The remaining active layer 114 is contacted.

In the thin film transistor substrate having the structure, the transparent conductive pattern including the pixel electrode 118, the second storage upper electrode 124, the gate pad upper electrode 132, and the data pad upper electrode 140 may include a protective film 150 and The photoresist pattern used during patterning of the gate insulating layer 144 is removed by a lift-off process. Accordingly, the transparent conductive pattern forms a boundary with the passivation layer 150. By applying such a lift-off process, the thin film transistor substrate according to the present invention can reduce the number of mask processes by a three mask process as follows.

4A and 4B illustrate a plan view and a cross-sectional view for describing a first mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.                     

In the first mask process, a gate metal pattern including a gate line 102, a gate electrode 108 connected to the gate line 102, and a gate pad lower electrode 128 is formed on the lower substrate 142.

In detail, the gate metal layer is formed on the lower substrate 142 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a gate metal pattern including the gate line 102, the gate electrode 108, and the gate pad lower electrode 128. Here, as the gate metal, Cr, MoW, Cr / Al, Cu, Al (Nd), Mo / Al, Mo / Al (Nd), Cr / Al (Nd) and the like are used.

5A and 5B illustrate a plan view and a cross-sectional view for describing a second mask process in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 6A to 6D illustrate the second mask process in detail. Figures below are shown.

First, the entire gate insulating layer 144 is formed on the lower substrate 142 on which the gate metal pattern is formed through a deposition method such as PECVD or sputtering. As the material of the gate insulating film 144, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used.

A semiconductor pattern including an active layer 114 and an ohmic contact layer 146 stacked on the gate insulating layer 144 by a second mask process; A source / drain metal pattern including a data line 104, a source electrode 110, a drain electrode 112, and a data pad lower electrode 136 is formed.

In detail, as shown in FIG. 6A, an amorphous silicon layer 114A, an n + amorphous silicon layer 146A, and a source / drain metal layer 105 are sequentially formed on the gate insulating layer 144 through a deposition method such as PECVD or sputtering. . The source / drain metal 105 may be a metal in which the exposed portions of the passivation layer 150 may be etched together in a subsequent process, for example, Mo, Cu, Al, and Cr that may be etched by a dry etching process. Series and the like are used.

 Subsequently, a photoresist pattern 148 having a step is formed by a photolithography process using a second mask, which is a partial exposure mask, after the photoresist is entirely coated on the source / drain metal layer 105. In this case, as the second mask, a partial exposure mask having a diffractive exposure portion (or semi-transmissive portion) at a portion where a channel of the thin film transistor is to be formed is used. Accordingly, the photoresist pattern 148 corresponding to the diffractive exposure portion (or transflective portion) of the second mask has a lower height than the photoresist pattern 148 corresponding to the transmission portion (or blocking portion) of the second mask. . In other words, the photoresist pattern 148 of the channel portion has a lower height than the photoresist pattern 148 of the other source / drain metal pattern portions.

As the source / drain metal layer 105 is patterned by a wet etching process using the photoresist pattern 148, as shown in FIG. 6B, the data electrode 104, the source electrode 110 of the thin film transistor unit, and the drain integrated therewith. A source / drain metal pattern is formed that includes the electrode 112. In addition, the n + amorphous silicon layer 114A and the amorphous silicon layer 146A are simultaneously patterned by a dry etching process using the same photoresist pattern 148 so that the ohmic contact layer 146 and the active layer 114 become the source / drain. It has a structure formed along the metal pattern.

Then, the ashing process using an oxygen (O ₂ ) plasma, the photoresist pattern 148 of the channel portion having a relatively low height is removed as shown in Fig. 6c, the other source / drain metal pattern portion The photoresist pattern 148 is lowered in height.

The source / drain metal pattern and the ohmic contact layer 146 are etched at the portion where the channel is to be formed by the dry etching process using the remaining photoresist pattern 148, so that the source electrode 110 and the drain electrode 112 are separated from each other. And the active layer 114 is exposed. Accordingly, a channel formed of the active layer 154 is formed between the source electrode 110 and the drain electrode 112. Then, the photoresist pattern 148 remaining in the source / drain metal pattern portion by the stripping process is removed as shown in FIG. 6D.

7A and 7B illustrate a plan view and a cross-sectional view for describing a third mask process in a method of manufacturing a thin film transistor array substrate according to an embodiment of the present invention, and FIGS. 8A to 8E illustrate the third mask process in detail. Cross-sectional views are shown below.

The entire passivation layer 150 and the gate insulating layer 144 are patterned by a third mask process, and a transparent conductive pattern including the pixel electrode 118, the gate pad upper electrode 132, and the data pad upper electrode 140 is formed. do. Here, the transparent conductive pattern is formed to form a boundary without overlapping the patterned protective layer 150.

In detail, as shown in FIG. 8A, the entire passivation layer 150 is formed on the entire gate insulating layer 144 on which the source / drain metal pattern is formed. As the material of the protective film 150, an inorganic insulating material similar to the gate insulating film 144 or an organic insulating material is used. The photoresist pattern 152 is formed on the entire surface of the passivation layer 150 by a photolithography process using a third mask.

Subsequently, the entire passivation layer 150 and the gate insulating layer 144 are patterned by an etching process using the photoresist pattern 152, that is, a dry etching process, so that the pixel holes 160 and the first holes are as shown in FIG. 8B. And second contact holes 130 and 138. At this time, a portion of the source / drain metal pattern not overlapping the photoresist pattern 152 is etched like the ohmic contact layer 146 and the active layer 114 below. As a result, the active layer 114, which has overlapped with a portion of the etched source / drain metal pattern, remains or is exposed, or the gate insulating layer 144 below it is exposed. A portion of the source / drain metal pattern not overlapping the photoresist pattern 152 includes a portion of the drain electrode 112 and a portion of the data pad upper electrode 136.

In detail, the pixel hole 160 is formed in the pixel area where the pixel electrode 118 is to be formed to expose the substrate 142, and the side surface of the drain electrode 112 which is etched when the pixel hole 160 is formed. . Meanwhile, when the drain electrode 112 is partially etched, the ohmic contact layer 146 and the active layer 114 below are also etched to expose the remaining active layer 114 or the gate insulating layer 144. The first contact hole 130 is formed in the gate pad 126 on which the gate pad upper electrode 132 is to be formed to expose the gate pad lower electrode 128. Since the second contact hole 138 is formed through the data pad lower electrode 136 in the data pad 134 on which the data pad upper electrode 140 is to be formed, the side surface of the data pad lower electrode 136 is exposed. do. At this time, the ohmic contact layer 146 and the active layer 114 under the data pad lower electrode 136 are also etched together to expose the remaining active layer 114 through the second contact hole 138, or the gate insulating layer 144. Is exposed.

Subsequently, the thin film transistor substrate on which the photoresist pattern 152 is present is cleaned using Deionized Water (DI) as shown in FIG. 8C or using He plasma treatment. This cleaning process removes contaminants remaining on the thin film transistor substrate. The contaminant may be an etching gas (eg, SF ₆ , Cl ₂ , HCl, CF ₄ , C ₃ H used in the dry etching process for forming the pixel hole 160, the first and second contact holes 130 and 138). ₅ , mixed gases thereof), residues of photoresist patterns, residues of etched protective films and gate insulating films, combinations thereof, and the like.

Subsequently, as shown in FIG. 8D, the transparent conductive film 154 is formed on the entire surface of the thin film transistor substrate on which the photoresist pattern 152 is present by a deposition method such as sputtering. As the transparent conductive film 154, indium tin oxide (ITO), tin oxide (TO), indium zinc oxide (IZO), SnO _2, or the like is used.

In addition, the photoresist pattern 152 and the transparent conductive film 154 thereon are removed together in a lift-off process to pattern the transparent conductive film 154. Accordingly, as shown in FIG. 8E, a transparent conductive pattern including the pixel electrode 118, the gate pad upper electrode 132, and the data pad upper electrode 140 is formed. The transparent conductive pattern forms a boundary without overlapping the patterned passivation layer 150.

In detail, the pixel electrode 118 is formed to form a boundary with the patterned passivation layer 150 in the pixel hole 160 and is connected to the side surface of the drain electrode 112. The gate pad upper electrode 132 is formed bordering the patterned passivation layer 150 in the first contact hole 130 and is connected to the gate pad lower electrode 128. The data pad upper electrode 132 is formed in a boundary with the patterned passivation layer 150 in the second contact hole 138 and is laterally connected to the data pad lower electrode 136.

9A and 9B are diagrams for describing the presence or absence of defects according to the presence or absence of the cleaning process before the lift-off process.

After forming the pixel holes 160, the first and second contact holes 130 and 138 shown in FIG. 8B by an etching process, and depositing the transparent conductive film 154 without the cleaning process, as shown in FIG. Lifting of the transparent conductive film occurs due to the remaining contaminants. That is, the etching gas (eg, SF ₆ , Cl ₂ , HCl, CF ₄ , C ₃ H ₅ , mixed gas thereof) remaining at the interface of the thin film transistor substrate after the etching process, and the remaining of the photoresist pattern 152 The adhesion between the transparent conductive film 154 and the thin film transistor substrate is reduced by water, residues of the protective film 150 and the gate insulating film 144, and combinations thereof. The transparent conductive film 154 floats during the lift-off process due to the reduced adhesive force. The stripped liquid penetrates into the empty space between the substrate 142 and the transparent conductive film 154 during the lift-off process by the excited transparent conductive film 154 to form the pixel electrode 118 and the gate pad upper electrode on the substrate 142. A peeling phenomenon (A) is generated in which the transparent conductive layer 154 that should remain in the region 132 and the data pad upper electrode 140 is removed. In addition, the F- and Cl-based ionic components remaining on the substrate 142 after the etching process generate an afterimage for a long time, for example, 1000 seconds or more when the image is formed after the panel is completed.

On the other hand, when the cleaning process is performed after the dry etching process, contaminants and the like remaining on the interface of the thin film transistor substrate are removed, thereby improving adhesion between the transparent conductive film 154 and the thin film transistor substrate. Accordingly, the floating phenomenon of the transparent conductive film 154 and the peeling phenomenon of removing the transparent conductive film 154 that must remain on the substrate are prevented as shown in FIG. 9B. In addition, after the etching process, the after-image inducing factor remaining at the interface of the substrate 142 is removed by the cleaning process. As a result, afterimage generation may occur for a short time, for example, 2 seconds or less during image realization, thereby reducing an afterimage defect.

As such, the cleaning process removes contaminants and the like that contaminate the interface of the thin film transistor substrate after the dry etching process as shown in Tables 1 and 2. In particular, when the thin film transistor substrate is cleaned with DI or the thin film transistor substrate is cleaned by using He plasma treatment, F-based and Cl-based ions that cause residual image defects are removed. Here, DI has high solubility of F-based and Cl-based ionic components.                     

pollutant F Cl NO ₂ NO ₃ SO ₄ Pollutant content after etching process [ppm] 697.15 73.02 9.49 6.49 11.33

washing
matter washing
time Pollutant content after cleaning process [ppm] F Cl NO ₂ NO ₃ SO ₄ DI 40 [sec] 25.94 18.50 8.80 3.03 6.68 80 [sec] 24.89 74.14 10.35 9.51 15.50 UV 15 [sec] 959.35 7.12 16.63 4.74 4.95 30 [sec] 909.81 19.21 11.80 1.62 7.29 O ₂ 30 [sec] 259.19 0.35 24.49 1.25 75.96 60 [sec] 379.92 1.61 28.51 3.38 110.88 He 30 [sec] 98.64 9.15 25.39 2.47 10.33 60 [sec] 127.32 1.79 24.29 2.85 5.08 H ₂ 30 [sec] 972.42 2.63 20.15 2.57 2.52 60 [sec] 821.39 0.63 18.70 3.61 1.02

As described above, the method of manufacturing the thin film transistor substrate and the method of manufacturing the flat panel display panel using the same according to the present invention clean the substrate before the deposition process of the transparent conductive film patterned by the lift-off process. Accordingly, contaminants remaining on the substrate after the etching process are removed. Adhesion between the substrate and the transparent conductive film is improved to prevent the lifting of the transparent conductive film and the afterimage defect.

In addition, the method of manufacturing the thin film transistor substrate and the method of manufacturing the flat panel display panel using the same according to the present invention can reduce the manufacturing cost and improve the manufacturing yield by applying a lift-off process to simplify the process in a three mask process. You can do it.                     

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (12)

Forming a gate pattern group including a gate line and a gate electrode on the substrate; After forming the gate insulating film on the substrate after the first mask process, a second mask for forming a source / drain pattern group including a data line, a source electrode and a drain electrode, and a semiconductor layer including an active layer and an ohmic contact layer Process; A third mask process of forming a pixel hole on the substrate after the second mask process and forming a pixel electrode in the pixel hole; The third mask process is Forming a passivation film on the entire surface of the substrate after the second mask process; Forming a photoresist pattern on the protective film; Etching the passivation layer and gate insulating layer of the pixel region exposed through the photoresist pattern to form the pixel hole; Cleaning the substrate on which the pixel hole is formed; Forming a transparent conductive film on the protective film having the photoresist pattern; And removing the photoresist pattern and the transparent conductive layer thereon by a lift-off process to form the pixel electrode. The method of claim 1, The cleaning of the substrate on which the pixel holes are formed And cleaning the substrate on which the pixel hole is formed using ultrapure water. The method of claim 1, The cleaning of the substrate on which the pixel holes are formed And cleaning the substrate on which the pixel hole is formed by plasma treatment using He. The method of claim 1, The protective film and the gate insulating film is a method of manufacturing a thin film transistor substrate, characterized in that the etching with an etching gas containing at least one of SF ₆ , Cl ₂ , HCl, CF ₄ , C ₃ H ₅ . The method of claim 4, wherein The cleaning of the substrate on which the pixel holes are formed And removing the F and Cl-based ionic components remaining on the substrate on which the pixel hole is formed. The method of claim 1, The first mask process may include forming a gate pad lower electrode connected to the gate line. The third mask process includes a contact hole penetrating through the passivation layer and a gate insulating layer to expose the gate pad lower electrode, and a gate pad upper electrode connected to the gate pad lower electrode bordering the passivation layer in the contact hole. The method of manufacturing a thin film transistor substrate further comprising the step of forming. The method of claim 1, The second mask process may include forming a data pad lower electrode connected to a data line. The third mask process may include forming a contact hole penetrating through the passivation layer and the data pad lower electrode, and a data pad upper electrode connected to a side of the data pad lower electrode and bordering the passivation layer in the contact hole. Method of manufacturing a thin film transistor substrate further comprises. Forming an entire first thin film on the substrate; Forming a photoresist pattern on the first thin film; Etching the first thin film using the photoresist pattern to form a first thin film pattern; Cleaning the substrate on which the first thin film pattern is formed; Forming a second thin film on the photoresist pattern remaining on the cleaned substrate; And removing the photoresist pattern and the second thin film thereon by a lift-off process to form a second thin film pattern. The method of claim 8, Cleaning the substrate on which the first thin film pattern is formed And cleaning the substrate on which the first thin film pattern is formed using ultrapure water. The method of claim 8, Cleaning the substrate on which the first thin film pattern is formed And cleaning the substrate on which the first thin film pattern is formed by plasma treatment using He. The method of claim 8, Etching the first thin film using the photoresist pattern to form a first thin film pattern And etching the first thin film using an etching gas including at least one of SF ₆ , Cl ₂ , HCl, CF ₄ , and C ₃ H ₅ , to form the first thin film pattern. A manufacturing method of a flat panel display panel. The method of claim 11, Cleaning the substrate on which the first thin film pattern is formed And removing the F and Cl based ionic components remaining on the substrate on which the first thin film pattern is formed.

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