KR19990031079A - Power-on reset circuit - Google Patents

Abstract

The present invention relates to a power-on reset circuit, and more particularly, to a power-on reset circuit that initializes each internal node at power-off and immediately resets internal nodes to output a power-on reset signal when the power-on state is immediately turned on. A power supply sensing circuit for detecting a level of a power supply voltage applied from the outside and outputting a detection signal; And a latch circuit receiving a signal of a first voltage level in response to the sensing signal at power on and receiving a signal of a second voltage level in response to the sensing signal at power off.

Description

Power on reset circuit

TECHNICAL FIELD The present invention relates to a power on reset circuit, and more particularly, to a power on reset circuit for stably operating a semiconductor device.

FIG. 1A is a circuit diagram showing the configuration of a power on reset circuit, and FIG. 1B is an output timing diagram of each node in the power on reset circuit.

Referring to FIG. 1A, the first node N1 ′ and the second node N2 ′, which are output terminals of the inverters I1 and I2 latching at the initial power-on, are each ″ H ″. In order to keep ″ L ″, the size of NMOS transistors and PMOS transistors, which are the components of the inverter, are designed. Therefore, by the initial value ″ L ″ of the second node N2 ', the third node N3' through the inverter I3 becomes ″ H ″ and is charged in the capacitor C1. When the capacitor C1 is charged to the power supply voltage level, when the fourth node N4 'falls to the low level, it is transferred to the gate of the PMOS transistor MP1 having a drain connected to the second node N2'. do. Due to the ″ L ″ of the fourth node N4 ', the PMOS transistor MP1 is turned on so that the first node N1' and the second node N2 'of the inverters I1 and I2, which are latched, are initialized. In this case, the second node N2 'maintains ″ H ″ according to the input of new data.

As a result, the charged charge is discharged in the capacitor C1 connected between the third node N3 'and the ground, so that the third node N3' maintains ″ L ″. The signal is inverted via inverters I4 and I5 and finally the power on reset signal The width is from the time when the capacitor (C1) is charged to the moment of discharge. If power is continuously supplied in this state, the second node N2 'becomes ″ H ″ and the third node N3' becomes ″ L ″, thereby maintaining a normal state. Power-on reset signal Is output when the initial latch values of the first node N1 'and the second node N2' at the initial power-on have a new initial value. When the power of the power-on reset circuit is turned off from the power-on state, the second node N2 'of the ″ H ″ is discharged to maintain the ″ L ″, and the power-on again. When in the state, the second node N2 'is charged to power on reset signal. Is output.

A power on reset circuit operating with the above configuration is used in an intermittent type system in which power on and off of a power source is repeated repeatedly.

According to the prior art, when the power is turned off and then turned on again, the following problem occurs according to the timing diagram of FIG.

When the power-on reset circuit as described above is driven in an intermittance type in which power on / off is repeated, when the power-on time of the power supply voltage is short and the second node is powered on without being discharged, the latch circuit The first node and the second node maintain a state when the power is off, causing a problem that the initialization is not set for new data. If the power on / off time is sufficient, the initial state of each node of the latch circuit is poor because the power on / off time is short enough for each node of the latch circuit to discharge. No output at all

Accordingly, an object of the present invention is to newly initialize each node of the latch circuit when the power on / off is intermittently repeated, when switching from the power off state to the power on state, and outputs a power on reset signal whenever power on. This is to provide a power-on reset circuit.

1A is a circuit diagram showing the configuration of a power-on reset circuit according to the prior art:

1b is an output timing diagram according to FIG. 1a:

2A is a circuit diagram showing in detail the configuration of a power-on reset circuit according to an embodiment of the present invention;

2b is an output timing diagram according to FIG. 2a:

* Explanation of symbols on main parts of the drawings

10: power detection circuit 20: voltage distribution circuit

30: drive circuit 40: latch circuit

(Configuration)

According to one aspect for achieving the above object, a power supply sensing circuit for detecting the level of the power supply voltage applied from the outside and outputting a detection signal; And a latch circuit configured to receive a signal of a first voltage level in response to the sensing signal at power-on and to receive a signal of a second voltage level in response to the sensing signal at power-off.

In a preferred embodiment, the first voltage level is a power supply voltage level and the second voltage level is a ground voltage level.

In a preferred embodiment, the power sensing circuit includes a voltage distribution circuit for receiving a power supply voltage from the outside and distributing it according to a resistance ratio; And a driving circuit configured to receive the division voltage and generate a detection signal.

In a preferred embodiment, the voltage distribution circuit comprises: a first power supply terminal to which a power supply voltage is applied; A second power supply terminal to which a ground voltage is applied; And resistors connected in series between the first power supply terminal and the second power supply terminal.

In a preferred embodiment, the driving circuit comprises: a PMOS transistor having a gate grounded and a power supply voltage applied to the source; A gate is connected to the junction of the resistors, a drain is connected to the train of the PMOS transistor and the source comprises an NMOS transistor grounded.

In a preferred embodiment, the latch circuit receives a signal of ground voltage level at power off in response to the sense signal.

In a preferred embodiment, the latch circuit includes NAND gates.

Such a circuit can sufficiently initialize each node of the internal latch circuit even when the power-off time is short when the power-off state is switched to the power-on state.

(Example)

Hereinafter, the present invention will be described in detail with reference to FIGS. 2A to 2B according to a preferred embodiment of the present invention.

Referring to FIG. 2A, the power sense circuit at power off detects a level and completely discharges the input node of the latch circuit maintained at the full state, and then the node of the latch circuit completely discharged when powered on The new initialization can output a power-on reset signal.

2A is a circuit diagram showing in detail a power-on reset circuit according to a preferred embodiment of the present invention.

Referring to FIG. 2A, the power on reset circuit stores data according to a power sensing circuit 10 for sensing a level of a power voltage VDD applied from the outside and a sensing signal generated from the power sensing circuit 10. The latch circuit 40 is included. The power sensing circuit 10 includes a voltage distribution circuit 20 and a driving circuit 30, and the voltage distribution circuit 20 is connected to a power supply terminal 1 to which a power supply voltage VDD is applied and a ground. It comprises a first resistor (R1) and a second resistor (R2) connected in series between the ground terminal (2). In addition, the driving circuit 30 includes a MOS transistor MP2 having a P-channel between a gate that is grounded and a power supply terminal 1 and a first node N1, which is an interconnection point of the resistors, and the first node. And a MOS transistor MN1 having a gate connected to N1 and an N channel formed in series with the P channel. The latch circuit 40 includes NAND gates ND1 and ND2.

2B is a timing diagram showing the output of each node of a power on reset circuit according to an embodiment of the present invention.

2A to 2B, first, when power-on, the voltage distribution circuit 20 distributes a power supply voltage applied from the outside according to a ratio of resistors and transfers it to the first node. This is applied to the NMOS transistor NM1 having a gate connected to the first node N1, which rises from the threshold voltage of the transistor until the transistor NM1 is turned on as shown in FIG. 2B. As the NMOS transistor NM1 is turned on, the charge of the second node N2 is discharged to ground, thereby becoming ″ L ″, which is the third node N3 which is the data input terminal of the latch circuit 40 via the inverter I7. Is delivered to. At this time, if the power supply VDD is continuously applied from the outside, the fifth node N5 of the latch circuit 40 becomes ″ L ″, and the first inverter I7 which inputs it as ″ H ″ represents the sixth node. The charge is charged to the capacitor C2 by being transferred to N6.

Subsequently, ″ H ″ of the sixth node C2 passes through the second inverter I8, which is a schmitt trigger, and the seventh node N7, which is an output terminal thereof, is characterized in that the capacitor C2 is During the initial period of charging, it rises to ″ H ″ and then falls to ″ L ″. The signal of the seventh node N7 is applied to the third inverter I9 and the fourth inverter I10 to finally power on the reset signal. Is output. The power on reset signal The width of corresponds to a section in which the seventh node N7 is ″ L ″ after the capacitor C2 is charged.

Subsequently, when the power-off state is turned off, the power supply voltage VDD applied to the power supply sensing circuit 10 is lowered, and the voltage distributed to the resistors R1 and R2 turns off the NMOS transistor NM1. Therefore, the PMOS transistor PM1, which is always turned on, causes the second node N2 to be ″ H ″, which is connected to the third node N3 which is an input terminal of the latch circuit 40 via the first inverter I7. Discharge from "H" to "L". This is followed by the latch circuit 40 whereby the fourth node N4 becomes " H " at the beginning of the power off, and the capacitor C2 begins to discharge the charged charge to ground, which continues during power off. do. Since power supply from the outside is interrupted, all other nodes will keep ″ L ″. Then, in the power-on state, the power sensing circuit 10 detects this to initialize the third node N3 of ″ L ″ to ″ H ″, where the third node N3 senses power when powered off. Since the circuit 10 is initialized to a completely discharged state, the power-off time is short, so that it is possible to prevent the power-on from being discharged.

In addition, since the resistors R1 and R2 of the voltage distribution circuit 20 in the power sensing circuit 10 may sense the level of the power supply voltage by adjusting the ratio of their values, the power-on reset signal due to lack of power-off time. Can be prevented from occurring at all.

Such a power-on reset circuit can be applied to various fields, but in particular, the efficiency can be improved when applied to an intermittent type system that repeats power-on-off regularly or irregularly.

Therefore, the present invention has the effect that a power-on reset signal can be obtained whenever power-on after initializing each node in the power-on reset circuit in the power-off state.

Claims (7)

Power detection means for detecting a level of a power supply voltage applied from the outside and outputting a detection signal; And a latch means for receiving a signal of a first voltage level in response to the detection signal at power on and receiving a signal of a second voltage level in response to the detection signal at power off. The method of claim 1, And the first voltage level is a power supply voltage level, and the second voltage level is a ground voltage level. The method of claim 1, The power sensing means includes voltage distribution means for distributing a power voltage applied from the outside; And a drive means for receiving the divided voltage to generate a sense signal. The method of claim 2, The voltage distribution means includes a first power supply terminal to which a power supply voltage is applied; A second power supply terminal to which a ground voltage is applied; And a resistor connected in series between said first power supply terminal and said second power supply terminal. The method of claim 2 or 3, The drive means A PMOS transistor whose gate is grounded and a power supply voltage is applied to the source; And an NMOS transistor having a gate connected to a connection point of the resistors, a drain connected to a train of the PMOS transistor, and a source grounded. The method of claim 1, And the latch means receives a signal of a ground voltage level upon power-off in response to the detection signal. The method of claim 5, And said latch means comprises NAND gates.