KR19990029439A - Method of manufacturing thin film transistor, liquid crystal display and TFT array substrate having same - Google Patents
Method of manufacturing thin film transistor, liquid crystal display and TFT array substrate having same Download PDFInfo
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- KR19990029439A KR19990029439A KR1019980036039A KR19980036039A KR19990029439A KR 19990029439 A KR19990029439 A KR 19990029439A KR 1019980036039 A KR1019980036039 A KR 1019980036039A KR 19980036039 A KR19980036039 A KR 19980036039A KR 19990029439 A KR19990029439 A KR 19990029439A
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- 239000000758 substrate Substances 0.000 title claims abstract description 42
- 239000010409 thin film Substances 0.000 title claims abstract description 33
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000010408 film Substances 0.000 claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 44
- 238000005530 etching Methods 0.000 claims description 12
- 230000007261 regionalization Effects 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 6
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 56
- 239000011521 glass Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Abstract
액정표시장치에 사용하는 박막 트랜지스터 및 TFT어레이기판의 제조방법에 관한 것으로서, 온특성이 우수한 박막 트랜지스터 및 이 박막 트랜지스터를 사용한 큰 화면이고 고선명도인 액정표시장치와 박막 트랜지스터를 구비한 TFT어레이기판의 제조방법을 제공하기 위해, 투명절연성기판상에 형성된 게이트전극, 게이트전극상에 게이트절연막을 거쳐서 마련된 채널부로 되는 i-a-Si층과 이 i-a-Si층상의 소스/드레인 접촉부에 마련된 n-a-Si층으로 이루어지는 반도체층 및 반도체층과 함께 반도체소자를 형성하는 소스 및 드레인전극을 구비하고, 소스/드레인 접촉부의 i-a-Si층의 막두께를 80㎚이상 120㎚이하로 하였다.A method for manufacturing a thin film transistor and a TFT array substrate for use in a liquid crystal display device, comprising: a thin film transistor having excellent on characteristics and a large screen and high definition liquid crystal display device and a TFT array substrate having a thin film transistor. To provide a fabrication method, a gate electrode formed on a transparent insulating substrate, an ia-Si layer serving as a channel portion provided on the gate electrode via a gate insulating film, and a na-Si layer provided on a source / drain contact portion on the ia-Si layer. A source and drain electrode for forming a semiconductor element together with the semiconductor layer and the semiconductor layer formed thereon were provided, and the film thickness of the ia-Si layer of the source / drain contact portion was 80 nm or more and 120 nm or less.
이와 같이 하는 것에 의해, i-a-Si층의 막두께를 80㎚이상 120㎚이하로 박막화했으므로 소스/드레인 접촉부분에 있어서의 i-a-Si층에 기인하는 기생저항을 저감할 수 있고, 온특성이 우수한 박막 트랜지스터가 얻어지고, 또 이 박막 트랜지스터를 구비하는 것에 의해 큰 면적이고 고선명도인 액정표시장치의 실현이 가능하게 된다는 효과가 얻어진다.In this way, the film thickness of the ia-Si layer is thinned to 80 nm or more and 120 nm or less, so that the parasitic resistance caused by the ia-Si layer in the source / drain contact portion can be reduced, and the temperature characteristic is excellent. A thin film transistor is obtained, and the provision of this thin film transistor brings about the effect that the liquid crystal display device of large area and high definition can be realized.
Description
본 발명은 액정표시장치에 사용하는 박막 트랜지스터 및 TFT어레이기판의 제조방법에 관한 것이다,The present invention relates to a method for manufacturing a thin film transistor and a TFT array substrate for use in a liquid crystal display device.
액정표시장치는 통상, 박막 트랜지스터(TFT)를 포함하는 스위칭소자 및 이 스위칭소자를 거쳐서 각각 제어되는 표시소자를 갖는 TFT어레이기판, 컬러필터, 블랙매트릭스 및 대향전극 등을 갖고 TFT어레이기판과의 사이에 액정을 끼워 유지하는 대향전극기판 및 스위칭소자의 구동회로를 구비하고 있으며, 액정에 선택적으로 전압이 인가되도록 구성되어 있다.A liquid crystal display device usually has a TFT array substrate having a switching element including a thin film transistor (TFT) and a display element controlled through the switching element, a color filter, a black matrix, an opposing electrode, and the like, and a TFT array substrate. The counter electrode substrate and the driving circuit of the switching element for holding the liquid crystal are provided on the substrate, and a voltage is selectively applied to the liquid crystal.
도 5는 종래의 역스태거형 TFT어레이기판의 화소부의 구조를 도시한 단면도이다. 도면에 있어서, (1)은 투명절연성기판으로서 예를 들면 유리기판, (2)는 게이트전극선, (3)은 게이트절연막, (4)는 채널로 되는 i-a-Si(논도프(non-doped) 비정질 실리콘)층, (5)는 i-a-Si층(4)상의 소스/드레인 접촉부에 마련된 n-a-Si(인(P)도프 비정질 실리콘)층, (6)은 소스전극선, (7)은 드레인전극, (8)은 투명도전막으로 이루어지는 화소전극, (9)는 보호막을 각각 나타낸다.5 is a cross-sectional view showing the structure of a pixel portion of a conventional reverse staggered TFT array substrate. In the figure, reference numeral 1 denotes a transparent insulating substrate, for example, a glass substrate, (2) a gate electrode line, (3) a gate insulating film, and (4) a channel, ia-Si (non-doped). An amorphous silicon) layer, (5) a na-Si (phosphorus (P) dope amorphous silicon) layer provided on the source / drain contact portion on the ia-Si layer (4), (6) a source electrode line, (7) a drain electrode (8) denotes a pixel electrode made of a transparent conductive film, and (9) denotes a protective film, respectively.
이상과 같이 구성된 역스태거형 TFT어레이기판에 있어서는 프로세스가 간이(簡易)하기 때문에 백채널 에치형 TFT가 사용되는 경우가 많다. 종래의 백채널 에치형 TFT의 제조방법을 도면에 따라서 설명한다. 우선, 유리기판(1)상에 게이트전극선(2)를 Cr등으로 형성한 후, 게이트절연막(3), 200㎚이상의 i-a-Si층(4) 및 50㎚이상의 n-a-Si층(5)를 형성한다. 그 후, i-a-Si층(4) 및 n-a-Si층(5)를 섬형상으로 패터닝하고, 투명도전막으로 이루어지는 화소전극(8)을 형성한다. 또, 소스전극선(6) 및 드레인전극(7)을 형성하고, 이들을 마스크로 해서 채널상의 불필요한 n-a-Si층(5)를 드라이에칭 등으로 제거(BCE : 백 채널 에칭)한 후, 보호막(9)를 형성하고 TFT어레이를 제작한다.In the reverse staggered TFT array substrate constructed as described above, the back channel etch type TFT is often used because the process is simple. A conventional method for manufacturing a back channel etch type TFT will be described with reference to the drawings. First, the gate electrode line 2 is formed of Cr on the glass substrate 1, and then the gate insulating film 3, the ia-Si layer 4 of 200 nm or more and the na-Si layer 5 of 50 nm or more are formed. Form. Thereafter, the i-a-Si layer 4 and the n-a-Si layer 5 are patterned in an island shape to form a pixel electrode 8 made of a transparent conductive film. The source electrode line 6 and the drain electrode 7 are formed, and the undesired na-Si layer 5 on the channel is removed by dry etching or the like (BCE: back channel etching) using these as a mask, and then the protective film 9 ) To form a TFT array.
이상과 같이 백채널 에치형 TFT에서는 n-a-Si층(5)를 에칭 등으로 제거해서 채널영역을 형성하지만, 이 때 오버에칭에 의해 i-a-Si층(4)까지 에칭이 실행된다. 그래서, 종래는 채널부의 i-a-Si층을 프로세스의 변동에 관계없이 항상 충분한 막두께를 확보하기 위해 i-a-Si층(4)를 200㎚이상의 막두께로 형성하고 있었다. 이 때문에, 소스/드레인 접촉부분에 있어서의 i-a-Si층(4)에 기인하는 기생저항(이하, 시리즈저항이라 한다)이 커지고, TFT의 특성, 특히 온특성을 저하시켜 큰 면적이고 고정밀도인 유리기판(1)의 구동에 있어서 라이트특성이 부족하고 표시특성이 저하한다는 문제가 있었다.As described above, in the back channel etch type TFT, the n-a-Si layer 5 is removed by etching or the like to form a channel region. At this time, etching is performed to the i-a-Si layer 4 by over etching. Therefore, conventionally, the i-a-Si layer 4 has been formed with a film thickness of 200 nm or more so that the i-a-Si layer of the channel portion always has a sufficient film thickness regardless of the process variation. For this reason, the parasitic resistance (hereinafter referred to as series resistance) caused by the ia-Si layer 4 in the source / drain contact portion becomes large, and the TFT properties, in particular, the on-state characteristics are lowered, which results in large area and high precision. In driving the glass substrate 1, there is a problem that the light characteristics are insufficient and the display characteristics are lowered.
또, 시리즈저항을 저감시키기 위해 소스전극 및 드레인전극과 게이트전극의 중첩부분(접촉부분)의 면적을 크게 할 필요가 있으며, 그 때문에 TFT의 기생용량이 증대하여 표시특성이 저하한다는 문제가 있었다.In addition, in order to reduce the series resistance, it is necessary to increase the area of the overlapping portion (contact portion) of the source electrode, the drain electrode, and the gate electrode, which causes a problem that the parasitic capacitance of the TFT increases and the display characteristics deteriorate.
본 발명의 목적은 상기와 같은 문제점을 해소하기 위해 이루어진 것으로서, 온특성이 우수한 박막 트랜지스터 및 이 박막 트랜지스터를 사용한 큰 화면이고 고선명도인 액정표시장치를 제공하고, 또 상기 박막 트랜지스터를 구비한 TFT어레이기판의 제조방법을 제공하는 것이다.DISCLOSURE OF THE INVENTION An object of the present invention is to solve the above problems, to provide a thin film transistor having excellent on characteristics and a large screen and high definition liquid crystal display device using the thin film transistor, and a TFT array having the thin film transistor. It is to provide a method of manufacturing a substrate.
도 1은 본 발명의 실시예1인 TFT어레이기판의 화소부분을 도시한 단면도,1 is a cross-sectional view showing a pixel portion of a TFT array substrate according to the first embodiment of the present invention;
도 2는 i-a-Si막두께와 시리즈저항의 관계를 도시한 도면,2 is a diagram showing a relationship between an i-a-Si film thickness and a series resistance;
도 3은 i-a-Si막두께와 이동도 및 임계값전압의 관계를 도시한 도면,3 is a diagram showing a relationship between an i-a-Si film thickness, mobility, and a threshold voltage;
도 4는 선형영역에 있어서의 이동도와 임계값전압의 n-a-Si막두께 의존성을 도시한 도면,4 is a diagram showing the n-a-Si film thickness dependence of mobility and threshold voltage in a linear region;
도 5는 종래의 TFT어레이기판의 화소부분을 도시한 단면도.5 is a sectional view showing a pixel portion of a conventional TFT array substrate.
※부호의 설명※ Explanation of sign
1…유리기판, 2…게이트전극선, 3…게이트절연막, 4…i-a-Si(논도프 비정질 실리콘)층, 5…n-a-Si(인도프 비정질 실리콘)층, 6…소스전극선, 7…드레인전극, 8…화소전극, 9…보호막.One… Glass substrate; Gate electrode line, 3... Gate insulating film, 4... i-a-Si (non-doped amorphous silicon) layer, 5... n-a-Si (indof amorphous silicon) layer, 6... Source electrode line 7. Drain electrode, 8.. Pixel electrode; Shield.
본 발명에 관한 박막 트랜지스터는 투명절연성기판상에 형성된 게이트전극, 게이트전극상에 게이트절연막을 거쳐서 마련된 채널부로 이루어지는 i-a-Si층, 이 i-a-Si층상의 소스/드레인 접촉부에 마련된 n-a-Si층으로 이루어지는 반도체층 및 반도체층과 함께 반도체소자를 형성하는 소스 및 드레인전극을 구비하고, 소스/드레인 접촉부의 i-a-Si층의 막두께를 80㎚이상 120㎚이하로 한 것이다.The thin film transistor according to the present invention is an ia-Si layer comprising a gate electrode formed on a transparent insulating substrate, a channel portion provided on the gate electrode via a gate insulating film, and a na-Si layer provided on a source / drain contact portion on the ia-Si layer. The semiconductor layer and the semiconductor layer together with the source and drain electrodes which form a semiconductor element are provided, and the film thickness of the ia-Si layer of a source / drain contact part is 80 nm or more and 120 nm or less.
또, n-a-Si층의 막두께를 20㎚이상 50㎚이하로 한 것이다.The film thickness of the n-a-Si layer is set to 20 nm or more and 50 nm or less.
또, 채널부의 i-a-Si층의 막두께를 30㎚이상 80㎚이하로 한 것이다.In addition, the film thickness of the i-a-Si layer of a channel part is made into 30 nm or more and 80 nm or less.
또, 게이트전극과 소스전극 및 드레인전극의 중첩길이를 2㎛이상 5㎛이하로 한 것이다.In addition, the overlapping length of the gate electrode, the source electrode and the drain electrode is set to 2 µm or more and 5 µm or less.
또, 본 발명에 관한 액정표시장치는 상기중의 하나의 박막 트랜지스터를 포함하는 스위칭소자 및 이 스위칭소자를 거쳐서 각각 제어되는 표시소자를 갖는 TFT어레이기판, 이 TFT어레이기판과의 사이에 액정을 끼워 유지하는 대향전극기판 및 스위칭소자의 구동회로를 구비한 것이다.In addition, a liquid crystal display device according to the present invention includes a TFT array substrate having a switching element including any one of the above thin film transistors, and a display element controlled through the switching element, and a liquid crystal sandwiched between the TFT array substrate. And a driving circuit for holding the counter electrode substrate and the switching element.
또, 본 발명에 관한 TFT어레이기판의 제조방법은 투명절연기판상에 Cr등의 금속박막을 성막하고 패턴형성에 의해 게이트전극선을 형성하는 공정, 이 게이트전극선상에 게이트절연막을 거쳐서 채널로 되는 막두께80㎚이상 120㎚이하의 i-a-Si층 및 소스/드레인 접촉층으로 되는 막두께20㎚이상 50㎚이하의 n-a-Si층을 연속해서성막하고 섬형상으로 패터닝하는 공정, 투명도전막을 스퍼터링 등의 방법에 의해 성막하고 패턴형성에 의해 화소전극을 형성하는 공정, Aℓ, Cr 등의 금속박막을 스퍼터링법 등에 의해 성막하고 패턴형성에 의해 소스전극선 및 드레인전극을 형성하는 공정, 채널부의 상기 i-a-Si층의 잔여 막량(殘膜量)이 30㎚이상 80㎚이하로 되도록 상기 n-a-Si층의 오버에칭량을 제어하면서 채널상의 불필요한 상기 n-a-Si층을 드라이에칭 등으로 제거하는 공정 및 보호막을 형성하는 공정을 포함해서 제조하도록 한 것이다.Further, the method for manufacturing a TFT array substrate according to the present invention is a step of forming a metal thin film such as Cr on a transparent insulating substrate and forming a gate electrode line by pattern formation, and forming a channel through the gate insulating film on the gate electrode line. A process of continuously forming a film thickness of 20 nm or more and a nm-Si layer of less than or equal to 120 nm and an ia-Si layer having a thickness of 80 nm or more and 120 nm or less and patterning it into an island shape, sputtering a transparent conductive film, etc. Forming a pixel electrode by pattern formation; forming a metal thin film such as A1, Cr, etc. by sputtering; forming a source electrode line and a drain electrode by pattern formation; By removing the unnecessary na-Si layer on the channel by dry etching or the like while controlling the over-etching amount of the na-Si layer so that the remaining film amount of the Si layer is 30 nm or more and 80 nm or less. It is made to include the process of forming a process and a protective film.
[발명의 실시예][Examples of the Invention]
실시예1Example 1
이하, 본 발명의 실시예1인 박막 트랜지스터(TFT) 및 그것을 구비한 TFT어레이기판의 제조방법을 도면에 따라서 설명한다. 도 1은 본 발명의 실시예1인 TFT어레이기판의 화소부분의 구조를 도시한 단면도이다. 도면에 있어서, (1)은 투명절연성기판으로서 예를 들면 유리기판, (2)는 게이트전극선, (3)은 게이트절연막, (4)는 채널로 되는 i-a-Si(논드프 비정질 실리콘)층, (5)는 i-a-Si층(4)상의 소스/드레인 접촉부에 마련된 n-a-Si(인도프 비정질 실리콘)층, (6)은 소스전극선, (7)은 드레인전극, (8)은 투명도전막으로 이루어지는 화소전극, (9)는 보호막, L은 게이트전극(2)와 소스전극(6) 및 드레인전극(7)의 중첩길이를 각각 나타낸다.Hereinafter, a thin film transistor (TFT) according to Embodiment 1 of the present invention and a method of manufacturing a TFT array substrate having the same will be described with reference to the drawings. 1 is a cross-sectional view showing the structure of a pixel portion of a TFT array substrate according to the first embodiment of the present invention. In the drawing, reference numeral 1 denotes a transparent insulating substrate, for example, a glass substrate, (2) a gate electrode line, (3) a gate insulating film, (4) a channel, and an ia-Si (non-doped amorphous silicon) layer, (5) is a na-Si (in-doped amorphous silicon) layer provided on the source / drain contact portion on the ia-Si layer (4), (6) is a source electrode line, (7) is a drain electrode, and (8) is a transparent conductive film Pixel electrode 9 formed is a protective film, and L represents the overlap length of the gate electrode 2, the source electrode 6 and the drain electrode 7, respectively.
본 실시예에 있어서의 박막 트랜지스터는 채널부로 되는 i-a-Si층(4) 및 소스/드레인 접촉부에 마련된 n-a-Si층(5)로 이루어지는 반도체층과 소스전극(6) 및 드레인전극(7)에 의해 반도체소자가 형성되어 있다. 또, 이 박막 트랜지스터를 포함하는 스위칭소자 및 이 스위칭소자를 거쳐서 각각 제어되는 표시소자, 여기서는 화소전극(8)을 갖는 TFT어레이기판, 컬러필터, 블랙 매트릭스 및 대향전극 등을 갖고 TFT어레이기판과의 사이에 액정을 끼워 유지하는 대향전극기판 및 스위칭소자의 구동회로 등에 의해 액정표시장치가 구성된다.The thin film transistor according to the present embodiment includes a semiconductor layer made up of an ia-Si layer 4 serving as a channel portion and a na-Si layer 5 provided in the source / drain contact portion, the source electrode 6 and the drain electrode 7. Thus, a semiconductor element is formed. In addition, a switching element including the thin film transistor and a display element controlled through the switching element, in this case, a TFT array substrate having a pixel electrode 8, a color filter, a black matrix, an opposing electrode, and the like, and a TFT array substrate. A liquid crystal display device is constituted by a counter electrode substrate holding a liquid crystal in between and a driving circuit of a switching element.
이하, 본 실시예에 의한 박막 트랜지스터를 구비한 역스태거형 TFT어레이기판의 제조방법을 설명한다.Hereinafter, the manufacturing method of the reverse staggered TFT array substrate provided with the thin film transistor by this Example is demonstrated.
우선, 유리기판(1)상에 Cr 등의 단층구조 또는 Cr/Aℓ등의 다층구조의 금속박막을 성막하고, 패턴형성에 의해 게이트전극선(2)를 형성한다. 다음에, 게이트절연막(3)을 형성한 후, 채널로 되는 i-a-Si층(4)를 80∼120㎚의 두께로 형성한다. 또, 연속해서 소스/드레인 접촉부를 형성하는 n-a-Si층(5)를 30㎚의 막두께로 형성한다. 또한, 본 실시예에서는 n-a-Si층(5)의 막두께를 30㎚로 하였지만, 20이상 50㎚이하의 범위이면 좋다. 이들의 반도체층(a-Si)의 막두께는 채널부의 i-a-Si층을 프로세스의 변동에 관계없이 항상 충분한 막두께를 확보하고, 또한 소스/드레인 접촉부에 있어서의 i-a-Si층(4)에 기인하는 기생저항(이하, 시리즈저항이라 한다)을 저감하는 것이 가능하게 되도록 최적화된 것이다.First, a metal thin film having a single layer structure such as Cr or a multi-layer structure such as Cr / Al is formed on the glass substrate 1, and the gate electrode line 2 is formed by pattern formation. Next, after the gate insulating film 3 is formed, an i-a-Si layer 4 serving as a channel is formed to a thickness of 80 to 120 nm. In addition, an n-a-Si layer 5 that continuously forms a source / drain contact portion is formed at a film thickness of 30 nm. In addition, in the present Example, the film thickness of the n-a-Si layer 5 was set to 30 nm, but what is necessary is just to be 20 or more and 50 nm or less. The film thickness of these semiconductor layers (a-Si) ensures that the ia-Si layer of the channel portion always has a sufficient film thickness regardless of the process variation, and that the ia-Si layer 4 at the source / drain contact portion is provided. The parasitic resistance (hereinafter referred to as series resistance) resulting from the optimization is optimized.
그 후, i-a-Si층(4) 및 n-a-Si층(5)를 섬형상으로 패터닝하고, 투명도전막을 스퍼터링 등의 방법에 의해 성막하고, 패턴형성에 의해 화소전극(8)을 형성한다. 또, Cr, Aℓ/Cr 또는 Cr/Aℓ/Cr 등의 금속박막을 스퍼터링법 등에 의해 성막하고, 패턴형성에 의해 소스전극선(6) 및 드레인전극(7)을 형성한다. 이 때. 게이트전극(2)와 소스전극(6) 및 드레인전극(7)의 중첩길이L을 2㎛이상 5㎛이하로 설계하는 것에 의해, 시리즈저항의 증가에 의한 특성의 열화없이 TFT의 기생용량을 저감할 수 있다. 또, 소스전극(6) 및 드레인전극(7)을 마스크로 해서 채널상의 불필요한 n-a-Si층(5)를 드라이에칭 등에 의해 제거(BCE : 백 채널 에칭)한다. 이 때, i-a-Si층(4)의 잔여 막량이 30㎚이상 80㎚이하로 되도록 n-a-Si층(5)의 오버에칭량을 제어하면서 에칭을 실행한다. 마지막으로, 보호막(9)를 SiN 등으로 형성해서 TFT어레이기판을 제작한다.Thereafter, the i-a-Si layer 4 and the n-a-Si layer 5 are patterned in an island shape, and a transparent conductive film is formed by a method such as sputtering to form a pixel electrode 8 by pattern formation. Further, a metal thin film such as Cr, Al / Cr or Cr / Al / Cr is formed by sputtering or the like, and the source electrode line 6 and the drain electrode 7 are formed by pattern formation. At this time. By designing the overlap length L between the gate electrode 2, the source electrode 6, and the drain electrode 7 to be 2 µm or more and 5 µm or less, the parasitic capacitance of the TFT is reduced without deterioration of characteristics due to the increase in series resistance. can do. The unnecessary n-a-Si layer 5 on the channel is removed by dry etching or the like (BCE: back channel etching) using the source electrode 6 and the drain electrode 7 as a mask. At this time, etching is performed while controlling the over-etching amount of the n-a-Si layer 5 so that the remaining film amount of the i-a-Si layer 4 may be 30 nm or more and 80 nm or less. Finally, the protective film 9 is made of SiN or the like to produce a TFT array substrate.
도 2는 i-a-Si막두께와 시리즈저항의 관계를 도시한 도면, 도 3은 i-a-Si막두께와 이동도 및 임계값전압의 관계를 도시한 도면이다. 도면에 있어서, 횡축은 i-a-Si막두께(㎚)이고, 종축의 R시리즈(M옴)는 시리즈저항, μfe(㎠/VS)는 이동도, Vth(V)는 임계값전압을 각각 나타낸다. 이들 실험결과에 의해 i-a-Si막두께가 커지면 시리즈저항은 증대하고 TFT특성이 열화하는 것을 알 수 있고, 본 발명에 의한 i-a-Si막두께의 박막화의 효과를 나타내고 있다. 또, 본 발명에 의한 TFT어레이기판에 의하면, 선형영역(저Vd영역)에 있어서, 종래의 백채널 에칭형 TFT보다 30%이상 큰 이동도가 얻어지므로, 라이트시간이 단축되고 라이트부족에 기인하는 표시불량이나 편차(불균일)를 저감할 수 있다.2 is a diagram showing the relationship between the i-a-Si film thickness and the series resistance, and FIG. 3 is a diagram showing the relationship between the i-a-Si film thickness, mobility, and threshold voltage. In the figure, the horizontal axis represents i-a-Si film thickness (nm), the R series (M ohm) of the vertical axis represents series resistance, μfe (cm 2 / VS) represents mobility, and Vth (V) represents threshold voltage, respectively. These experimental results show that as the i-a-Si film thickness increases, the series resistance increases and TFT characteristics deteriorate, and the thin film of the i-a-Si film thickness according to the present invention is exhibited. Further, according to the TFT array substrate according to the present invention, since the mobility in the linear region (low Vd region) is 30% or more larger than that of the conventional back channel etching type TFT, the write time is shortened and due to the lack of light. It is possible to reduce display defects and variations (nonuniformities).
또, 도 4는 선형영역(Vd=1V)에 있어서의 이동도와 임계값전압의 n-a-Si막두께 의존성을 도시한 실험결과로서, 본 발명에 있어서의 n-a-Si층(5)의 박막화의 가능성을 시사하고 있다. n-a-Si층(5)를 박막화하는 것에 의해 임계값전압이 작아지는 이점이 있긴 하지만, 이동도도 작아지기 때문에 그 양쪽을 고려해서 막두께를 설정할 필요가 있다. 본 실시예에서는 n-a-Si층(5)를 에칭할 때에 오버에칭에 의해서 i-a-Si층(4)를 손상시키는 것에 의한 TFT 특성의 저하를 저감하기 위해서 n-a-Si층(5)를 종래의 50㎚에서 30㎚까지 박막화하고, 오버에칭량을 저감하도록 한 것이다.Fig. 4 is an experimental result showing the dependence of the na-Si film thickness on the mobility and threshold voltage in the linear region (Vd = 1 V), and the possibility of thinning the na-Si layer 5 in the present invention. Suggests. Although the threshold voltage is reduced by thinning the n-a-Si layer 5, the mobility is also reduced, and therefore it is necessary to set the film thickness in consideration of both. In this embodiment, in order to reduce the deterioration of TFT characteristics by damaging the ia-Si layer 4 by over etching when etching the na-Si layer 5, the na-Si layer 5 is replaced with the conventional 50. The film thickness is reduced from nm to 30 nm, and the amount of overetching is reduced.
이상과 같이, 본 실시예에서는 소스/드레인 접촉부에 있어서의 i-a-Si층(4)의 막두께를 종래의 200㎚에서 80㎚이상 120㎚이하로 박막화하고, 또 n-a-Si층(5)를 종래의 50㎚에서 30㎚까지 박막화했으므로, 시리즈저항이 작고 선형영역에서의 이동도가 높아 기생용량이 작은 박막 트랜지스터가 얻어졌다. 또, i-a-Si층(4)에 의한 저항의 저감에 의해 박막 트랜지스터의 소형화가 가능하게 되므로 화소의 고개구율화가 가능하게 된다. 또, 이 박막 트랜지스터를 구비하는 것에 의해 큰 면적이고 고선명도인 액정표시장치의 실현이 가능하게 된다.As described above, in the present embodiment, the film thickness of the ia-Si layer 4 in the source / drain contact portion is thinned from the conventional 200 nm to 80 nm or more and 120 nm or less, and the na-Si layer 5 is further reduced. Since the conventional thin film has been thinned from 50 nm to 30 nm, a thin film transistor having a small series resistance and high mobility in a linear region with low parasitic capacitance has been obtained. In addition, since the thin film transistor can be miniaturized by reducing the resistance by the i-a-Si layer 4, the high aperture ratio of the pixel can be achieved. In addition, by providing the thin film transistor, it is possible to realize a liquid crystal display device having a large area and high definition.
이상과 같이, 본 발명에 의하면 i-a-Si층의 막두께를 80㎚이상 120㎚이하로 박막화했으므로 소스/드레인 접촉부분에 있어서의 i-a-Si층에 기인하는 기생저항을 저감할 수 있고, 온특성이 우수한 박막 트랜지스터가 얻어지고, 또 이 박막 트랜지스터를 구비하는 것에 의해 큰 면적이고 고선명도인 액정표시장치의 실현이 가능하게 된다.As described above, according to the present invention, since the film thickness of the ia-Si layer is thinned to 80 nm or more and 120 nm or less, the parasitic resistance caused by the ia-Si layer in the source / drain contact portion can be reduced, and the thermal characteristics This excellent thin film transistor is obtained, and the provision of this thin film transistor enables the realization of a large area and high definition liquid crystal display device.
Claims (6)
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| JP9243180A JPH1187721A (en) | 1997-09-08 | 1997-09-08 | Thin-film transistor and liquid crystal display device comprising the same, and manufacture of tft array substrate |
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| KR100980020B1 (en) | 2003-08-28 | 2010-09-03 | 삼성전자주식회사 | Thin film transistor array panel and manufacturing method thereof |
| US8080449B2 (en) | 2009-04-07 | 2011-12-20 | Hitachi Displays, Ltd. | Method for manufacturing thin-film transistors |
| GB2543101B (en) * | 2015-10-09 | 2022-09-14 | Flexenable Ltd | Lamination technique for producing electronic devices |
| KR102596354B1 (en) * | 2018-11-05 | 2023-10-31 | 삼성디스플레이 주식회사 | Liquid crystal display and the method therrof |
| CN112993041B (en) * | 2021-02-03 | 2023-03-24 | 重庆先进光电显示技术研究院 | Liquid crystal display panel, thin film transistor and manufacturing method thereof |
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