KR19990029193A - Power-on reset circuit that can reliably generate power-on reset signal - Google Patents

Abstract

Voltages of the interconnected first and second inverter circuits 10, 12, the capacitor 14 connected to the input node NDA of the first inverter circuit 10, and the output node NDB of the first inverter circuit 10. In the power-on reset circuit including the buffer circuits 20 to 25 for generating the power-on reset signal / POR, the source voltage of the N-channel MOS transistor 124 in the second inverter circuit 12 is grounded. In order to rise above the voltage GND, a diode-connected transistor 18 is inserted between the source of the transistor 124 and the ground node 2. Therefore, this power-on reset circuit can surely generate the power-on reset signal / POR even when the power supply voltage VCC falls.

Description

Power-on reset circuit that can reliably generate power-on reset signal

The present invention relates to a power on reset circuit, and more particularly, to a power on reset circuit for generating a power on reset signal for a predetermined period after power is turned on.

Most semiconductor integrated circuit devices, such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and microprocessors, are powered on only for a predetermined period of time after the power is turned on, in order to initialize an internal circuit in an unstable state before power is turned on. A power-on reset circuit for generating a reset signal is employed. This power-on reset signal is activated only for a predetermined period until the power supply voltage reaches a predetermined level, and is deactivated when the power supply voltage reaches a predetermined level. The internal circuit is reset in response to this activated power on reset signal.

On the other hand, recently, semiconductor integrated circuit devices employing two kinds of power supply voltages have also been provided. In addition, a semiconductor integrated circuit device may be tested by increasing or decreasing a power supply voltage. Here, the higher power supply voltage is defined as a high power supply voltage, and the lower power supply voltage is defined as a low power supply voltage. For example, some DRAMs use a high power supply voltage of 5.0 V in the normal operation mode and a low power supply voltage of 1.3 V in the standby operation mode.

In the case of employing a conventional power-on reset circuit in such a semiconductor integrated circuit device, there is a fear that the internal circuit may not be reset when the power supply voltage returns from the low power supply voltage to the high power supply voltage. That is, the conventional power-on reset circuit cannot generate a power-on reset signal unless it rises again after the power supply voltage becomes lower than 0.76V. For example, in a DRAM employing 1.3 V as the low power supply voltage in the standby operation mode, there is a problem that the internal circuit is not reset unless the power-on reset signal is generated after the termination of the standby operation mode.

An object of the present invention is to provide a power-on reset circuit which can surely generate a power-on reset signal when the power supply voltage once rises and then rises again.

1 is a circuit diagram showing an overall configuration of a power on reset circuit according to a first embodiment of the present invention;

FIG. 2 is a waveform diagram illustrating the operation of the power-on reset circuit according to the first embodiment shown in FIG. 1;

3 is a circuit diagram showing the configuration of main parts of a power-on reset circuit according to a second embodiment of the present invention;

4 is a circuit diagram showing the configuration of main parts of the power-on reset circuit according to the third embodiment of the present invention;

Explanation of symbols for the main parts of the drawings

One ; Power node 2; Ground node

10, 12, 20-25, 34; CM0S inverter circuits 14 and 16; Capacitor

18, 104, 124, 126, 181 to 183, 411 to 413; N-channel MOS transistor

102, 122; P-channel MOS transistors 401 to 403; fuse

421 to 423; Inverter circuits 431 to 434; resistance

According to one aspect of the present invention, a power-on reset circuit for generating a power-on reset signal for a predetermined period after power is turned on includes a first CMOS inverter circuit, a second CM0S inverter circuit, a capacitor, and a voltage raising circuit. And a buffer circuit. The second CM0S inverter circuit has an input node connected to the output node of the first CMOS inverter circuit and an output node connected to the input node of the first CM0S inverter circuit. The capacitor is connected between the power supply node and the input node of the first CM0S inverter circuit. The voltage raising circuit raises the source voltage of the N-channel MOS transistor in the second CMOS inverter circuit by a predetermined voltage rather than the ground voltage. The buffer circuit generates a power-on reset signal in response to the voltage at the output node of the first CM0S inverter circuit.

Advantageously, said voltage ramping circuit comprises a transistor diode connected between a source and a ground node of said N-channel MOS transistor.

Preferably, the voltage raising circuit includes a plurality of transistors and a switching element. A plurality of transistors are connected in series between the source and ground node of the N-channel MOS transistor. Each of the transistors is diode connected. The switching element is connected in parallel to at least one of the plurality of transistors.

Preferably, the voltage raising circuit further includes a control circuit for controlling the switching element to be on / off in accordance with a power supply voltage.

According to one aspect of the present invention, a power-on reset circuit for generating a power-on reset signal for a predetermined period after power is turned on includes a first node, a second node, a capacitor, a first transistor, and a second. A transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a buffer circuit are provided. The capacitor is connected between the power supply node and the first node. The first transistor has a gate connected to the first node, a source connected to the power supply node, and a drain connected to the second node. The second transistor has a gate connected to the first node, a drain connected to the second node, and a source connected to the ground node. The third transistor has a gate connected to the second node, a source connected to the power supply node, and a drain connected to the first node. The fourth transistor has a gate connected to the second node. The fifth transistor has a gate that receives a predetermined voltage, a drain connected to the first node, and a source connected to the drain of the fourth transistor. The sixth transistor has a gate connected to the source of the fourth transistor, a drain connected to the source of the fourth transistor, and a source connected to the ground node. The buffer circuit generates a power on reset signal in response to the voltage of the second node.

In the power-on reset circuit according to the present invention, since the source voltage of the N-channel M0S transistor in the CMOS inverter circuit is increased by a predetermined voltage rather than the ground voltage, the level at which the power-on reset signal is activated becomes high, and thus the power supply. Even when the voltage drops from the high power supply voltage to the low power supply voltage, the power-on reset signal can be surely activated. As a result, even when the semiconductor integrated circuit device employing this power-on reset circuit enters the low power supply voltage mode, its internal circuit can be reliably reset.

In addition, since a diode-connected transistor is inserted between the source and the ground node of the N-channel M0S transistor to raise the source voltage by a predetermined voltage rather than the ground voltage, this power-on reset circuit greatly increases the layout area. Can be realized without.

In order to raise the source voltage by a predetermined voltage above the ground voltage, a plurality of transistors connected in series and diode-connected in series are inserted between the source and the ground node of the N-channel MOS transistor, and at least one of these transistors is inserted. Since the switching elements are connected in parallel, the level at which the power-on reset signal is activated can be freely adjusted.

In addition, since the switching element is controlled to be turned on / off according to the power supply voltage, the level at which the power on reset signal is activated can be automatically adjusted according to the low power supply voltage used.

The above and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same or equivalent part in drawing, and the description is not repeated.

(Example 1)

1 is a circuit diagram showing the overall configuration of a power-on reset circuit according to the first embodiment of the present invention. Referring to Fig. 1, this power-on reset circuit includes a CM0S inverter circuits 10 and 12, a capacitor 14, and an N-channel MOS transistor 18.

The CMOS inverter circuit 10 includes a P channel MOS transistor 102, an N channel MOS transistor 104, and a P channel MOS transistor 106. P-channel MOS transistor 102 has a gate connected to node NDA, a source connected to power supply node 1, and a drain connected to node NDB via P-channel MOS transistor 106. N-channel MOS transistor 104 has a gate connected to node NDA, a drain connected to node NDB, and a source connected to ground node 2. The P channel MOS transistor 106 is connected between the P channel MOS transistor 102 and the node NDB.

The CMOS inverter circuit 12 includes a P-channel MOS transistor 122, an N-channel MOS transistor 124, and an N-channel MOS transistor 126. P-channel MOS transistor 122 has a gate connected to node NDB, a source connected to power supply node 1, and a drain connected to node NDA. N-channel MOS transistor 124 has a gate connected to node NDB, a drain connected to node NDA via N-channel MOS transistor 126, and a source connected to ground node via N-channel MOS transistor 18. The N-channel MOS transistor 126 has a gate that receives a predetermined voltage, a drain connected to the node NDA, and a source connected to the drain of the N-channel MOS transistor 124.

Capacitor 14 is connected between power supply node 1 and node NDA. The N-channel MOS transistor 18 is for raising the source voltage of the N-channel MOS transistor 124 by the threshold voltage Vth above the ground voltage GND, and is connected between the source of the N-channel MOS transistor and the ground node 2, In addition, a diode is connected.

This power-on reset circuit further includes a buffer circuit composed of six CM0S inverter circuits 20 to 25. The buffer circuits 20 to 25 generate a power-on reset signal / POR in response to the voltage of the output node NDB of the CMOS inverter circuit 10. Each of the CMOS inverter circuits 20 to 25 includes a P channel MOS transistor 202 and an N channel MOS transistor 204.

This power-on reset circuit further includes a capacitor 16, a P-channel MOS transistor 26, an N-channel MOS transistor 28, a P-channel MOS transistor 30 and 32, and a CMOS inverter circuit 34. And a P-channel MOS transistor 36 and an N-channel MOS transistor 38.

Capacitor 16 is connected between node NDB and ground node 2. P-channel MOS transistor 26 has a gate connected to ground node 2, a source connected to power supply node 1, and a drain connected to the gate of N-channel MOS transistor 126. Since the P-channel MOS transistor 26 functions as a resistor, a predetermined voltage is supplied to the gate of the N-channel MOS transistor 126. N-channel MOS transistor 28 is connected between node NDA and ground node 2. Each of the P channel MOS transistors 30 and 32 is connected between the gate of the P channel MOS transistor 106 and the ground node 2. The gate of the P-channel MOS transistor 30 is connected to the drain of the transistor 30 itself, and the gate of the P-channel MOS transistor 32 is connected to the source of the transistor 32 itself. Therefore, the P channel MOS transistors 30 and 32 supply a predetermined voltage to the gate of the P channel MOS transistor 106.

The CMOS inverter circuit 34 includes a P channel MOS transistor 342, an N channel MOS transistor 344, and a P channel MOS transistor 346. The P-channel MOS transistor 36 is connected between the output node of the CMOS inverter circuit 34 and the gate of the N-channel MOS transistor 28, and is also diode connected. The N-channel MOS transistor 38 has a gate connected to the output node of the CMOS inverter circuit 23, and is connected between the gate of the N-channel MOS transistor 28 and the ground node 2.

This power-on reset circuit has a level type function that generates a power-on reset signal / POR for a predetermined period when the power supply voltage VCC gradually rises after the power supply, and the power supply voltage VCC increases rapidly after the power supply. Has a timer type function that generates a power-on reset signal / POR for a predetermined period of time. Therefore, this power-on reset circuit can surely generate a power-on reset signal for a predetermined period even when the power supply voltage VCC gradually rises or rises sharply.

Here, in order to realize a timer type function, the capacitor 16, the N-channel MOS transistor 28, the CMOS inverter circuit 34, the P-channel MOS transistor 36, and the N-channel MOS transistor 38 are provided. Since the features of the present invention reside in circuits other than those described above for realizing the timer type function, the operation thereof will be described below with reference to circuits for realizing the level type function.

FIG. 2 is a waveform diagram illustrating the operation of the power-on reset circuit shown in FIG. 1. Referring to FIG. 2, when the power is turned on at time t = 0, the power supply voltage VCC gradually rises toward the high power voltage VCCH (for example, 5.0 V). Therefore, the voltages of the nodes NDA and NDB also increase in accordance with the power supply voltage VCC. Until the time t = 1 at which the voltage of the node NDB reaches a predetermined level, the activated L (low) level power-on reset signal / POR is a buffer circuit (inverter circuits 20 to 25). Is caused by

Subsequently, when the voltage of the node NDB reaches the predetermined level at time t = 1, the power-on reset signal / POR is deactivated to the H (high) level. Since the voltage at this node NDB reaches the high power voltage VCCH, the N-channel MOS transistor 124 is turned on. At this time, since the N-channel MOS transistor 126 that receives the power supply voltage VCC from the gate via the P-channel MOS transistor 26 is always in the on state, the voltage of the node NDA drops to a predetermined level. This level is determined by the threshold voltage of the diode-connected N-channel MOS transistor 18.

In the steady state after the power supply voltage VCC reaches the high power supply voltage VCCH (between time t = 1 and time t = 2), the voltage of the node NDA drops to the predetermined level, so that the P-channel MOS transistor ( 102 is turned on so that the power supply voltage VCC is supplied to the node NDB via the P channel MOS transistors 102 and 106. Since the voltage at the node NDB has reached a high power voltage, the N-channel MOS transistor 124 is turned on, and the charge of the node NDA is discharged to the ground node 2 via the N-channel MOS transistors 126, 124, and 18. do.

Subsequently, at time t = 2, when the power supply voltage VCC starts to fall from the high power supply voltage VCCH to the low power supply voltage VCCL, the voltage of the node NDA is subjected to the coupling effect of the capacitor 14 to obtain a predetermined negative ( Descend to the level of i). The voltage at node NDB drops to the low power supply voltage VCCL in accordance with the power supply voltage VCC.

At this time, for example, when the N-channel MOS transistor 18 is not provided, since the source voltage of the N-channel MOS transistor 124 is the ground voltage, the voltage of the node NDB is the threshold voltage of the N-channel MOS transistor 124 (for example, For example, the N-channel MOS transistor 124 does not turn on unless it is lower than 0.76 V). Therefore, the node NDB maintains the H level, and the power-on reset signal / POR is not activated to the L level.

However, since the N-channel MOS transistor 10 is provided in this power-on reset circuit, the source voltage of the N-channel MOS transistor 124 is higher than the threshold voltage of the N-channel MOS transistor 18 rather than the ground voltage GND. For example, since it rises by about 1.0 V, when the voltage of the node NDB falls below a predetermined voltage (here, 1.7 V ≒ 0.76 V + 1.0 V), the N-channel MOS transistor 124 is turned off. In this case, the voltage of the node NDB falls to the low power supply voltage VCCL of 1.3 V, which is lower than 1.7 V, so that the voltage is at the L level, whereby the power-on reset signal / POR is activated at the L level.

As described above, since the voltage of the node NDB drops to 1.3 V which is lower than 1.7 V, the N-channel MOS transistor 124 is turned off, and the node NDA is charged by the P-channel MOS transistor 122. Therefore, the voltage at the node NDA rises to a voltage lower by the threshold voltage of the P-channel MOS transistor 122 than the low power supply voltage VCCL. When the voltage of the node NDA is higher than the threshold voltage of the N-channel MOS transistor 104, the N-channel MOS transistor 104 is turned on, so that the voltage of the node NDB drops to the ground voltage GND, thereby reducing the node NDB. Is set. When the voltage of the node NDB becomes the ground voltage, the P-channel MOS transistor 122 is completely turned on, and the power supply voltage VCC (here, the low power supply voltage VCCL) is supplied to the node NDA as it is.

Subsequently, at time t = 3, when the power supply voltage VCC starts to rise from the low power supply voltage VCCL to the high power voltage VCCH, and reaches a predetermined level at time t = 4, the power-on reset signal / POR is reset again. Inactivated to H level.

In the above, the case where the power supply voltage VCC rises relatively slowly has been described in detail. Hereinafter, the case where the power supply voltage VCC rises rapidly will be briefly described.

In this power-on reset circuit, even if the power supply voltage VCC rises sharply, the output of the CMOS inverter circuit 23 is prevented from being deactivated immediately after the power-on reset signal / POR circuit is turned on. Delayed by the P-channel MOS transistor 36 and delivered to the gate of the N-channel MOS transistor 28. Therefore, even when the power supply voltage VCC rises sharply, the N-channel MOS transistor 28 is turned off for a predetermined period after the power is turned on, so that the node NDA is not immediately discharged. Therefore, even when the power supply voltage VCC rises sharply, the L level power-on reset signal / POR deactivated for a predetermined period after the power supply is generated is generated.

As described above, according to the first embodiment, a diode-connected N-channel MOS transistor 18 is inserted between the N-channel MOS transistor 124 and the ground node 2, so that the source voltage of the N-channel MOS transistor 124 is inserted. Since the ground voltage GND is raised by the threshold voltage of the N-channel MOS transistor 18, the power-on reset signal / POR is surely activated even when the power supply voltage VCC falls from the high power supply voltage VCCH to the low power supply voltage VCCL. Can be. As a result, when this power-on reset circuit is employed in a semiconductor integrated circuit device such as a DRAM, the internal circuit can be reliably reset even when the semiconductor integrated circuit device enters a low power supply voltage mode.

(Example 2)

In the first embodiment, since one N-channel MOS transistor 18 is provided, the level at which the power-on reset signal / POR is activated (1.7 V in the first embodiment) is fixed. You may make it adjustable according to the specification of the semiconductor integrated circuit device which employs a set circuit.

Fig. 3 is a circuit diagram showing the configuration of main parts of the power-on reset circuit according to the second embodiment for the purpose of making the level adjustable. Referring to Fig. 3, in the second embodiment, instead of the N-channel MOS transistor 18 in the first embodiment, three N-channel MOS transistors 181 to 183 of the N-channel MOS transistor 124 are used. It is connected in series between the source and the ground node 2. Each of the N-channel MOS transistors 181 to 183 is diode connected. Further, fuses 401 to 403 are connected in parallel to the N-channel MOS transistors 181 to 183 respectively as switching elements.

When all the fuses 401 to 403 are not blown, the source voltage of the N-channel MOS transistor 124 becomes the ground voltage GND. When one of the fuses 401 to 403 is blown, the source voltage of the N-channel MOS transistor 124 is raised by the threshold voltage of the N-channel MOS transistor corresponding to the blown fuse rather than the ground voltage GND. When two of the fuses 401 to 403 are blown, the source voltage of the N-channel MOS transistor 124 is raised by the threshold voltages of the two N-channel MOS transistors from the ground voltage GND. When the fuses 401 to 403 are blown, the source voltage of the N channel MOS transistor 124 is raised from the ground voltage GND by the threshold voltages of the three N channel MOS transistors 181 to 183.

Therefore, by appropriately cutting the fuses 401 to 403 according to the specification of the semiconductor integrated circuit device employing this power on reset circuit, it is possible to freely adjust the level at which the power on reset signal / POR is generated. do.

Here, three N-channel MOS transistors 181 to 183 are inserted, but this number is not particularly limited. Note that it is not necessary to connect the fuses 401 to 403 in parallel with all the N channel MOS transistors 181 to 183, and the fuses may be connected in parallel with at least one N channel MOS transistor.

(Example 3)

In the second embodiment, the level at which the power-on reset signal / POR is artificially generated in accordance with the power supply voltage can be adjusted. However, the level may be automatically adjusted in accordance with the power supply voltage VCC.

Fig. 4 is a circuit diagram showing the configuration of the main part of the power-on reset circuit according to the third embodiment for the purpose of automatically adjusting the level at which the power-on reset signal / POR is activated in accordance with the power supply voltage VCC. Referring to Fig. 4, in the third embodiment, N-channel MOS transistors 411 to 413 are connected as switching elements instead of the fuses 401 to 403 in the second embodiment. The resistors 431 to 434 are connected in series between the power supply node 1 and the ground node 2, and the connection nodes ND1 to ND3 of the resistors 431 to 434 and the N channel MOS transistors 411 to 413 are connected in series. Inverter circuits 421 to 423 are connected between the gates, respectively.

When a relatively low low power supply voltage VCCL is used, the number of the N-channel MOS transistors 411 to 413 turned on becomes large, and therefore the level at which the power-on reset signal / POR is activated is low. . On the other hand, when a relatively high low power supply voltage VCCL is used, the number of the N-channel MOS transistors 411 to 413 to be turned on becomes small, and therefore the level at which the power-on reset signal / POR is activated becomes high.

As described above, according to the third embodiment, since the N-channel MOS transistor is controlled to be turned on / off in accordance with the power supply voltage VCC, the level at which the power-on reset signal / POR is activated can be automatically adjusted.

In the power-on reset circuit according to the present invention, since the source voltage of the N-channel M0S transistor in the CMOS inverter circuit is increased by a predetermined voltage rather than the ground voltage, the level at which the power-on reset signal is activated becomes high, and thus the power supply. Even when the voltage drops from the high power supply voltage to the low power supply voltage, the power-on reset signal can be surely activated. As a result, even when the semiconductor integrated circuit device employing this power-on reset circuit enters the low power supply voltage mode, its internal circuit can be reliably reset.

In addition, since a diode-connected transistor is inserted between the source and the ground node of the N-channel M0S transistor to raise the source voltage by a predetermined voltage rather than the ground voltage, this power-on reset circuit greatly increases the layout area. Can be realized without.

In order to raise the source voltage by a predetermined voltage above the ground voltage, a plurality of transistors connected in series and diode-connected in series are inserted between the source and the ground node of the N-channel MOS transistor, and at least one of these transistors is inserted. Since the switching elements are connected in parallel, the level at which the power-on reset signal is activated can be freely adjusted.

In addition, since the switching element is controlled to be turned on / off according to the power supply voltage, the level at which the power on reset signal is activated can be automatically adjusted according to the low power supply voltage used.

As mentioned above, although the invention made by this inventor was demonstrated concretely according to the said Example, this invention is not limited to the said Example and can be variously changed in the range which does not deviate from the summary.

Claims (3)

In a power-on reset circuit for generating a power-on reset signal (/ POR) for a predetermined period after the power is turned on, The first CM0S inverter circuit 10, An output node NDA connected to an output node NDB of the first CM0S inverter circuit 10 and an output node NDA connected to an input node NDA of the first CM0S inverter circuit 10. 2 CMOS inverter circuit 12, A capacitor 14 connected between the power supply node 1 and the input node NDA of the first CM0S inverter circuit 10, Voltage raising means (18; 181-183,401-403; 411-413) for raising the source voltage of the N-channel MOS transistor 124 in the second CMOS inverter circuit 12 by a predetermined voltage than the ground voltage GND; And a buffer circuit (20-25) for generating the power on reset signal (/ POR) in response to the voltage of the output node (NDB) of the first CM0S inverter circuit (10). The method of claim 1, And said voltage raising means comprises a transistor (18) diode-connected between a source of said N-channel MOS transistor (124) and a ground node (2). In a power-on reset circuit for generating a power-on reset signal (/ POR) for a predetermined period after the power is turned on, The first node (NDA), The second node (NDB), A capacitor 14 connected between the power node 1 and the first node NDA, A first transistor 102 having a gate connected to the first node NDA, a source connected to the power supply node 1, and a drain connected to the second node NDB; A second transistor 104 having a gate connected to the first node NDA, a drain connected to the second node NDB, and a source connected to the ground node 2; A third transistor 122 having a gate connected to the second node NDB, a source connected to the power node 1, and a drain connected to the first node NDA; A fourth transistor 124 having a gate connected to the second node NDB, A fifth transistor 126 having a gate receiving a predetermined voltage, a drain connected to the first node NDA, and a source connected to the drain of the fourth transistor 124; A sixth transistor 18 having a gate connected to the source of the fourth transistor 124, a drain connected to the source of the fourth transistor 124, and a source connected to the ground node 2; And a buffer circuit (20-25) for generating the power on reset signal (/ POR) in response to the voltage of the second node (NDB).