KR19990027918A - Contact manufacturing method of semiconductor device - Google Patents
Contact manufacturing method of semiconductor device Download PDFInfo
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- KR19990027918A KR19990027918A KR1019970050449A KR19970050449A KR19990027918A KR 19990027918 A KR19990027918 A KR 19990027918A KR 1019970050449 A KR1019970050449 A KR 1019970050449A KR 19970050449 A KR19970050449 A KR 19970050449A KR 19990027918 A KR19990027918 A KR 19990027918A
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- insulating film
- contact
- polysilicon
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Abstract
본 발명은 반도체소자의 콘택 제조방법에 관한 것으로, 종래에는 3차사진식각공정에서 오정렬이 발생하면, 게이트의 상부에 증착된 질화막, 비피에스지막 및 절연막이 식각되어 게이트와 폴리실리콘이 단락되는 문제점이 있었다. 이와같은 문제점을 감안한 본 발명은 측벽을 가진 게이트를 소정거리 이격되도록 형성한 기판의 상부전면에 순차적으로 제1절연막, 제1평탄화막과 제1질화막을 순차적으로 증착하는 단계와; 사진식각공정을 통해 상기 제1질화막, 제1평탄화막과 제1절연막의 일부를 순차적으로 식각한 후, 제1폴리실리콘을 매립하여 게이트의 사이에 제1콘택을 형성하는 단계와; 상기 제1콘택 및 제1질화막의 상부에 제2절연막, 제2질화막, 제2평탄화막, 제3절연막과 제4절연막을 순차적으로 증착하는 단계와; 사진식각공정을 통해 상기 제4절연막의 일부를 식각하여 제3절연막의 일부를 노출시킨후, 상기 제4절연막의 측면에 폴리실리콘측벽을 형성하는 단계와; 사진식각공정을 통해 노출된 제3절연막, 제2평탄화막, 제2질화막과 제2절연막을 식각하여 제2콘택홀을 형성한 후, 제2폴리실리콘을 증착하여 제2콘택을 형성하는 단계로 이루어지는 반도체소자의 콘택 제조방법을 제공하여 제1질화막을 통해 이후의 식각공정에서 그 제1평탄화막이 식각되는 것을 억제함으로써, 오정렬에 의한 게이트와 콘택의 단락을 방지하여 금속배선의 절연신뢰성을 향상시킬 수 있는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a semiconductor device. In the past, when a misalignment occurs in a third photolithography process, a nitride film, a BP film, and an insulating film deposited on an upper portion of the gate are etched to short-circuit the gate and polysilicon. There was this. In view of the above problems, the present invention includes the steps of sequentially depositing a first insulating film, a first planarization film and a first nitride film on an upper front surface of a substrate on which a gate having sidewalls is spaced a predetermined distance apart; Sequentially etching a portion of the first nitride film, the first planarization film, and the first insulating film through a photolithography process, and then filling the first polysilicon to form a first contact between the gates; Sequentially depositing a second insulating film, a second nitride film, a second planarization film, a third insulating film, and a fourth insulating film on the first contact and the first nitride film; Etching a portion of the fourth insulating layer through a photolithography process to expose a portion of the third insulating layer, and then forming a polysilicon sidewall on the side of the fourth insulating layer; Forming a second contact hole by etching the third insulating film, the second planarization film, the second nitride film and the second insulating film exposed through the photolithography process, and then depositing the second polysilicon to form the second contact. By providing a method for manufacturing a contact of a semiconductor device formed by the first nitride film to prevent the etching of the first flattening film in the subsequent etching process, to prevent the short circuit of the gate and the contact due to misalignment to improve the insulation reliability of the metal wiring It can be effective.
Description
본 발명은 반도체소자의 콘택 제조방법에 관한 것으로, 특히 디램(DRAM)셀 커패시터의 하부전극을 금속배선과 접속시키는 콘택의 절연신뢰성을 향상시키기에 적당하도록 한 반도체소자의 콘택 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact of a semiconductor device, and more particularly, to a method for manufacturing a contact for a semiconductor device suitable for improving insulation reliability of a contact connecting a lower electrode of a DRAM cell capacitor with a metal wiring.
일반적으로, 반도체소자의 콘택(contact)은 다층 금속배선을 전기적으로 절연시키는 층간절연막의 일부를 식각하여 홀을 형성하고, 그 홀의 내부에 도전물질을 매립하여 다층 금속배선을 선택적으로 접속시키기 위해 제조된다. 이와같은 종래 반도체소자의 콘택 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.In general, a contact of a semiconductor device is manufactured by etching a portion of an interlayer insulating film electrically insulating the multilayer metal wiring to form a hole, and filling a conductive material in the hole to selectively connect the multilayer metal wiring. do. If described in detail with reference to the accompanying drawings, such a conventional method for manufacturing a semiconductor device as follows.
도1a 내지 도1e는 종래 반도체소자의 콘택 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 기판(1)의 상부에 측벽(3)을 가진 게이트(2)를 소정거리 이격되도록 형성한후, 기판(1)의 상부전면에 순차적으로 절연막(4)과 비피에스지막(BPSG:5)을 증착하는 단계(도1a)와; 1차사진식각공정을 이용하여 게이트(2) 사이의 비피에스지막(5)과 절연막(4)을 순차적으로 식각하여 콘택홀을 형성한 후, 그 콘택홀의 내부에 폴리실리콘(6)을 매립하는 단계(도1b)와; 상기 비피에스지막(5)과 폴리실리콘(6)의 상부에 순차적으로 절연막(7), 질화막(8), 비피에스지막(9), 절연막(10)과 절연막(11)을 증착하는 단계(도1c)와; 2차사진식각공정을 통해 절연막(11)의 일부를 식각하여 절연막(10)을 노출시킨후, 그 절연막(11)의 측면에 폴리실리콘측벽(12)을 형성하는 단계(도1d)와; 3차사진식각공정을 이용하여 폴리실리콘(6)과 비피에지막(5)의 일부가 노출되도록 절연막(10), 비피에스지막(9), 질화막(8), 절연막(7)을 순차적으로 식각한 후, 상부전면에 폴리실리콘(13)을 증착하는 단계(도1e)로 구성된다. 이하, 종래 반도체소자의 콘택 제조방법을 좀더 상세히 설명한다.1A through 1E are cross-sectional views showing a conventional method for manufacturing a contact of a semiconductor device. As shown in FIG. 1A to 1E, a gate 2 having sidewalls 3 is formed on the substrate 1 so as to be spaced a predetermined distance apart. Depositing an insulating film 4 and a non-PSG film 5 on the upper surface of the substrate 1 in sequence (FIG. 1A); After forming a contact hole by sequentially etching the BP film 5 and the insulating film 4 between the gates 2 using a primary photolithography process, the polysilicon 6 is embedded in the contact hole. Step (FIG. 1B); Depositing an insulating film 7, a nitride film 8, a BP film 9, an insulating film 10, and an insulating film 11 on top of the BP film 5 and the polysilicon 6 (FIG. 1c); Etching a part of the insulating film 11 through the secondary photolithography process to expose the insulating film 10, and then forming a polysilicon sidewall 12 on the side of the insulating film 11 (FIG. 1D); Etching the insulating film 10, the BP film 9, the nitride film 8, and the insulating film 7 sequentially so that a part of the polysilicon 6 and the BP layer 5 are exposed using a third photolithography process. After that, the polysilicon 13 is deposited on the upper front surface (FIG. 1E). Hereinafter, a method for manufacturing a contact of a conventional semiconductor device will be described in more detail.
먼저, 도1a에 도시한 바와같이 기판(1)의 상부에 측벽(3)을 가진 게이트(2)를 소정거리 이격되도록 형성한 후, 기판(1)의 상부전면에 순차적으로 절연막(4)과 비피에스지막(5)을 증착한다. 이때, 절연막(1)은 이후의 공정에서 커패시터의 상부전극과 게이트(2)의 단락을 방지하기 위해 증착하고, 비피에스지막(5)은 다층구조의 형성에 적당하도록 웨이퍼의 상부를 평탄화하기 위해 증착한다.First, as shown in FIG. 1A, a gate 2 having sidewalls 3 is formed on the substrate 1 so as to be spaced apart by a predetermined distance, and then the insulating film 4 and the upper surface of the substrate 1 are sequentially formed. The BPS film 5 is deposited. At this time, the insulating film 1 is deposited to prevent a short circuit between the upper electrode of the capacitor and the gate 2 in a subsequent process, and the BPS layer 5 is used to planarize the top of the wafer so as to be suitable for forming a multilayer structure. Deposit.
그리고, 도1b에 도시한 바와같이 1차사진식각공정을 이용하여 게이트(2) 사이의 비피에스지막(5)과 절연막(4)을 순차적으로 식각하여 콘택홀을 형성한 후, 그 콘택홀의 내부에 폴리실리콘(6)을 매립한다. 이때, 폴리실리콘(6)은 콘택홀의 내부에 증착된 후, 식각되어 형성되므로, 비피에스지막(5)과 단차를 갖게되고, 이 콘택은 기판(1)에 형성된 소스 또는 드레인과 이후에 형성되는 금속배선을 접속시킨다.As shown in FIG. 1B, the BP film 5 and the insulating film 4 between the gates 2 are sequentially etched using a first photolithography process to form a contact hole, and then the inside of the contact hole. Polysilicon 6 is embedded in the. In this case, since the polysilicon 6 is deposited inside the contact hole and then etched, the polysilicon 6 has a step with the BPS layer 5, and the contact is formed after the source or drain formed on the substrate 1. Connect the metal wiring.
그리고, 도1c에 도시한 바와같이 비피에스지막(5)과 폴리실리콘(6)의 상부에 순차적으로 절연막(7), 질화막(8), 비피에스지막(9), 절연막(10)과 절연막(11)을 증착한다. 이때, 질화막(8)은 이후의 식각공정에서 게이트(2) 상부의 비피에스지막(5)과 절연막(4)이 식각되는 것을 억제하고, 비피에스지막(9)은 상기 폴리실리콘(6)과 비피에스지막(5)의 단차를 평탄화한다.As shown in FIG. 1C, the insulating film 7, the nitride film 8, the BP film 9, the insulating film 10, and the insulating film are sequentially formed on the BPS film 5 and the polysilicon 6. 11) Deposit. In this case, the nitride film 8 inhibits the etching of the BPS film 5 and the insulating film 4 on the gate 2 in the subsequent etching process, and the BPS film 9 is formed of the polysilicon 6 and the like. The level difference of the BPS film 5 is planarized.
그리고, 도1d에 도시한 바와같이 2차사진식각공정을 통해 절연막(11)의 일부를 식각하여 절연막(10)을 노출시킨후, 그 절연막(11)의 측면에 폴리실리콘측벽(12)을 형성한다. 이때, 폴리실리콘측벽(12)을 형성하는 이유는 콘택의 폭을 최소화하고, 절연막(11)의 모서리를 완만하게 하여 이후, 그 부분에 형성되는 폴리실리콘(13)의 스텝커버리지(step coverage)특성을 향상시키기 위해서이다.Then, as shown in FIG. 1D, a part of the insulating film 11 is etched through the secondary photolithography process to expose the insulating film 10, and then a polysilicon side wall 12 is formed on the side surface of the insulating film 11. do. At this time, the reason for forming the polysilicon side wall 12 is to minimize the width of the contact, to smooth the edge of the insulating film 11, and then the step coverage (step coverage) characteristics of the polysilicon 13 formed in the portion To improve it.
그리고, 도1e에 도시한 바와같이 3차사진식각공정을 이용하여 폴리실리콘(6)과 비피에지막(5)의 일부가 노출되도록 절연막(10), 비피에스지막(9), 질화막(8), 절연막(7)을 순차적으로 식각한 후, 상부전면에 폴리실리콘(13)을 증착한다.As shown in FIG. 1E, the insulating film 10, the non-PSI film 9, and the nitride film 8 are exposed so that a part of the polysilicon 6 and the non-PEG layer 5 are exposed by using a tertiary photolithography process. After sequentially etching the insulating film 7, the polysilicon 13 is deposited on the upper surface.
그러나, 상기한 바와같이 제조되는 종래 반도체소자의 콘택 제조방법은 3차사진식각공정에서 오정렬(misalign)이 발생하면, 게이트의 상부에 증착된 질화막, 비피에스지막 및 절연막이 식각되어 게이트와 폴리실리콘이 단락되는 문제점이 있었다.However, in the conventional method for manufacturing a contact of a semiconductor device manufactured as described above, when misalignment occurs in the third photolithography process, the nitride film, the BPS film, and the insulating film deposited on the gate are etched to form the gate and the polysilicon. There was a problem with this shorting.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 오정렬이 발생해도 게이트와 콘택의 절연신뢰성을 향상시킬 수 있는 반도체소자의 콘택 제조방법을 제공하는데 있다.The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a contact of a semiconductor device which can improve the insulation reliability of the gate and the contact even if misalignment occurs.
도1은 종래 반도체소자의 콘택 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a conventional method for manufacturing a contact of a semiconductor device.
도2는 본 발명의 일 실시예를 보인 수순단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
1:기판 2:게이트1: Substrate 2: Gate
3:측벽 4,7,10,11:절연막3: side wall 4, 7, 10, 11: insulation film
5,9:비피에스지막 6,13:폴리실리콘5,9: PS film 6,13: polysilicon
8,20:질화막 12:폴리실리콘측벽8,20: nitride film 12: polysilicon side wall
상기한 바와같은 본 발명의 목적은 측벽을 가진 게이트를 소정거리 이격되도록 형성한 기판의 상부전면에 순차적으로 제1절연막, 제1평탄화막과 제1질화막을 순차적으로 증착하는 단계와; 사진식각공정을 통해 상기 제1질화막, 제1평탄화막과 제1절연막의 일부를 순차적으로 식각한 후, 제1폴리실리콘을 매립하여 게이트의 사이에 제1콘택을 형성하는 단계와; 상기 제1콘택 및 제1질화막의 상부에 제2절연막, 제2질화막, 제2평탄화막, 제3절연막과 제4절연막을 순차적으로 증착하는 단계와; 사진식각공정을 통해 상기 제4절연막의 일부를 식각하여 제3절연막의 일부를 노출시킨후, 상기 제4절연막의 측면에 폴리실리콘측벽을 형성하는 단계와; 사진식각공정을 통해 노출된 제3절연막, 제2평탄화막, 제2질화막과 제2절연막을 식각하여 제2콘택홀을 형성한 후, 제2폴리실리콘을 증착하여 제2콘택을 형성하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 콘택 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above is the step of sequentially depositing the first insulating film, the first planarization film and the first nitride film on the upper surface of the substrate formed by forming a gate having a sidewall spaced apart a predetermined distance; Sequentially etching a portion of the first nitride film, the first planarization film, and the first insulating film through a photolithography process, and then filling the first polysilicon to form a first contact between the gates; Sequentially depositing a second insulating film, a second nitride film, a second planarization film, a third insulating film, and a fourth insulating film on the first contact and the first nitride film; Etching a portion of the fourth insulating layer through a photolithography process to expose a portion of the third insulating layer, and then forming a polysilicon sidewall on the side of the fourth insulating layer; Forming a second contact hole by etching the third insulating film, the second planarization film, the second nitride film and the second insulating film exposed through the photolithography process, and then depositing the second polysilicon to form the second contact. This is achieved by the above, and will be described in detail with reference to the accompanying drawings.
도2a 내지 도2e는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 기판(1)의 상부에 측벽(3)을 가진 게이트(2)를 소정거리 이격되도록 형성한후, 기판(1)의 상부전면에 순차적으로 절연막(4), 비피에스지막(5)과 질화막(20)을 증착하는 단계(도2a)와; 사진식각공정을 통해 게이트(2) 사이의 질화막(20), 비피에스지막(5)과 절연막(4)을 순차적으로 식각하여 콘택홀을 형성한 후, 그 콘택홀의 내부에 폴리실리콘(6)을 매립하여 제1콘택을 형성하는 단계(도2b)와; 질화막(20) 및 폴리실리콘(6)의 상부에 순차적으로 절연막(7), 질화막(8), 비피에스지막(9), 절연막(10), 절연막(11)을 증착하는 단계(도2c)와; 사진식각공정을 통해 절연막(11)의 일부를 식각하여 절연막(10)을 노출시킨후, 그 절연막(11)의 측면에 폴리실리콘측벽(12)을 형성하는 단계(도2d)와; 사진식각공정을 통해 폴리실리콘(6)과 질화막(20)의 일부가 노출되도록 절연막(10), 비피에스지막(9), 질화막(8), 절연막(7)을 순차적으로 식각한 후, 상부전면에 폴리실리콘(13)을 증착하는 단계(도2e)로 구성된다. 이하, 본 발명의 일 실시예를 좀더 상세히 설명한다.2A to 2E are cross-sectional views showing an embodiment of the present invention. As shown therein, a gate 2 having sidewalls 3 is formed on the substrate 1 so as to be spaced apart by a predetermined distance. Depositing an insulating film 4, a BPS film 5 and a nitride film 20 sequentially on the upper front surface of (1) (FIG. 2A); Through the photolithography process, the nitride film 20, the BPS film 5, and the insulating film 4 between the gates 2 are sequentially etched to form a contact hole, and then the polysilicon 6 is formed inside the contact hole. Embedding to form a first contact (FIG. 2B); Sequentially depositing an insulating film 7, a nitride film 8, a BP film 9, an insulating film 10, and an insulating film 11 on the nitride film 20 and the polysilicon 6 (FIG. 2C); ; Etching a part of the insulating film 11 through a photolithography process to expose the insulating film 10, and then forming a polysilicon side wall 12 on the side of the insulating film 11 (FIG. 2D); After etching the insulating film 10, BPS film 9, nitride film 8, insulating film 7 in order to expose a portion of the polysilicon 6 and the nitride film 20 through a photolithography process, the upper front surface And depositing polysilicon 13 on (FIG. 2E). Hereinafter, an embodiment of the present invention will be described in more detail.
먼저, 도2a에 도시한 바와같이 기판(1)의 상부에 측벽(3)을 가진 게이트(2)를 소정거리 이격되도록 형성한후, 기판(1)의 상부전면에 순차적으로 절연막(4), 비피에스지막(5)과 질화막(20)을 증착한다. 이때, 종래와 동일하게 절연막(1)은 커패시터의 상부전극과 게이트(2)의 단락을 방지하기 위해 증착하고, 비피에스지막(5)은 웨이퍼의 상부를 평탄화하기 위해 증착한다.First, as shown in FIG. 2A, a gate 2 having sidewalls 3 is formed on the substrate 1 so as to be spaced apart by a predetermined distance, and then the insulating film 4, The BPS film 5 and the nitride film 20 are deposited. At this time, as in the prior art, the insulating film 1 is deposited to prevent a short circuit between the upper electrode of the capacitor and the gate 2, and the BPS film 5 is deposited to planarize the top of the wafer.
그리고, 도2b에 도시한 바와같이 사진식각공정을 통해 게이트(2) 사이의 질화막(20), 비피에스지막(5)과 절연막(4)을 순차적으로 식각하여 콘택홀을 형성한 후, 그 콘택홀의 내부에 폴리실리콘(6)을 매립하여 제1콘택을 형성한다. 이때, 폴리실리콘(6)은 종래와 동일하게 비피에스지막(5)과 단차를 갖게된다.As shown in FIG. 2B, the nitride film 20, the BPS film 5, and the insulating film 4 between the gates 2 are sequentially etched through a photolithography process to form a contact hole, and then the contact. Polysilicon 6 is embedded in the hole to form a first contact. At this time, the polysilicon 6 has a step with the BPS film 5 as in the prior art.
그리고, 도2c에 도시한 바와같이 질화막(20) 및 폴리실리콘(6)의 상부에 순차적으로 절연막(7), 질화막(8), 비피에스지막(9), 절연막(10), 절연막(11)을 증착한다. 이때, 종래와 동일하게 질화막(8)은 게이트(2) 상부의 비피에스지막(5)과 절연막(4)이 식각되는 것을 억제하고, 비피에스지막(9)은 상기 폴리실리콘(6)과 비피에스지막(5)의 단차를 평탄화한다.As shown in FIG. 2C, the insulating film 7, the nitride film 8, the BP film 9, the insulating film 10, and the insulating film 11 are sequentially disposed on the nitride film 20 and the polysilicon 6. Deposit. At this time, as in the prior art, the nitride film 8 suppresses etching of the BP film 5 and the insulating film 4 on the gate 2, and the BP film 9 is not formed of the polysilicon 6. The step of the PS film 5 is planarized.
그리고, 도2d에 도시한 바와같이 사진식각공정을 통해 절연막(11)의 일부를 식각하여 절연막(10)을 노출시킨후, 그 절연막(11)의 측면에 폴리실리콘측벽(12)을 형성한다. 이때, 폴리실리콘측벽(12)을 형성하는 이유는 종래와 동일하게 콘택의 폭을 최소화하고, 폴리실리콘(13)의 스텝커버리지특성을 향상시키기 위해서이다.As shown in FIG. 2D, a part of the insulating film 11 is etched through the photolithography process to expose the insulating film 10, and then a polysilicon side wall 12 is formed on the side surface of the insulating film 11. At this time, the reason for forming the polysilicon side wall 12 is to minimize the width of the contact and improve the step coverage characteristics of the polysilicon 13 as in the prior art.
그리고, 도2e에 도시한 바와같이 사진식각공정을 통해 폴리실리콘(6)과 질화막(20)의 일부가 노출되도록 절연막(10), 비피에스지막(9), 질화막(8), 절연막(7)을 순차적으로 식각한 후, 상부전면에 폴리실리콘(13)을 증착한다. 이때, 상기 비피에스지막(5)과 절연막(4)의 상부에 질화막(20)이 증착되어 그 비피에스지막(5)과 절연막(4)의 식각을 억제하여 오정렬에 의한 게이트(2)와 제1콘택의 단락을 방지한다.As shown in FIG. 2E, the insulating film 10, the BP film 9, the nitride film 8, and the insulating film 7 are exposed so that a portion of the polysilicon 6 and the nitride film 20 are exposed through a photolithography process. After sequentially etching, polysilicon 13 is deposited on the upper surface. At this time, the nitride film 20 is deposited on the BPS film 5 and the insulating film 4 to suppress the etching of the BPS film 5 and the insulating film 4, thereby preventing the gate 2 and the second from being misaligned. 1 Prevent short circuit of contact.
상기한 바와같이 제조되는 본 발명에 의한 반도체소자의 콘택 제조방법은 제1평탄화막의 상부에 제1질화막을 증착하여 이후의 식각공정에서 그 제1평탄화막이 식각되는 것을 억제함으로써, 오정렬에 의한 게이트와 콘택의 단락을 방지하여 금속배선의 절연신뢰성을 향상시킬 수 있는 효과가 있다.In the method for manufacturing a contact of a semiconductor device according to the present invention manufactured as described above, by depositing a first nitride film on top of the first planarization film and suppressing the etching of the first planarization film in a subsequent etching process, By preventing the short circuit of the contact has an effect that can improve the insulation reliability of the metal wiring.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970050449A KR100437623B1 (en) | 1997-09-30 | 1997-09-30 | Method of manufacturing contact of semiconductor device without short between gate and contact |
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| KR1019970050449A KR100437623B1 (en) | 1997-09-30 | 1997-09-30 | Method of manufacturing contact of semiconductor device without short between gate and contact |
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| KR19990027918A true KR19990027918A (en) | 1999-04-15 |
| KR100437623B1 KR100437623B1 (en) | 2004-07-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100706800B1 (en) * | 2006-01-02 | 2007-04-12 | 삼성전자주식회사 | Method of fabricating metal wiring of semiconductor device |
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| FR2664095B1 (en) * | 1990-06-28 | 1993-12-17 | Commissariat A Energie Atomique | METHOD FOR MANUFACTURING AN ELECTRICAL CONTACT ON AN ACTIVE ELEMENT OF A MIS INTEGRATED CIRCUIT. |
| US5558873A (en) * | 1994-06-21 | 1996-09-24 | Kimberly-Clark Corporation | Soft tissue containing glycerin and quaternary ammonium compounds |
| KR960004086A (en) * | 1994-07-30 | 1996-02-23 | 김태구 | Flickering control device for vehicle direction indicator |
| KR0166027B1 (en) * | 1994-12-28 | 1999-02-01 | 김주용 | Manufacturing method of semiconductor device |
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| KR100706800B1 (en) * | 2006-01-02 | 2007-04-12 | 삼성전자주식회사 | Method of fabricating metal wiring of semiconductor device |
| US7871829B2 (en) | 2006-01-02 | 2011-01-18 | Samsung Electronics Co., Ltd. | Metal wiring of semiconductor device and method of fabricating the same |
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