KR19990026608A - Metal diffusion barrier film formation method of semiconductor device - Google Patents
Metal diffusion barrier film formation method of semiconductor device Download PDFInfo
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- KR19990026608A KR19990026608A KR1019970048813A KR19970048813A KR19990026608A KR 19990026608 A KR19990026608 A KR 19990026608A KR 1019970048813 A KR1019970048813 A KR 1019970048813A KR 19970048813 A KR19970048813 A KR 19970048813A KR 19990026608 A KR19990026608 A KR 19990026608A
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- polycrystalline silicon
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 52
- 239000002184 metal Substances 0.000 title claims abstract description 52
- 238000009792 diffusion process Methods 0.000 title claims abstract description 34
- 230000004888 barrier function Effects 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 title claims abstract description 20
- 239000004065 semiconductor Substances 0.000 title abstract description 32
- 230000015572 biosynthetic process Effects 0.000 title description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 58
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 32
- 239000010408 film Substances 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 239000010409 thin film Substances 0.000 claims abstract description 24
- 238000000151 deposition Methods 0.000 claims abstract description 21
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 16
- 239000010937 tungsten Substances 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 230000008021 deposition Effects 0.000 claims abstract description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 7
- 230000009466 transformation Effects 0.000 abstract description 2
- 238000007796 conventional method Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 7
- 239000000463 material Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
본 발명은 반도체 소자의 금속 확산 방지막 형성방법에 관한 것으로, 종래 반도체 소자의 금속 확산 방지막 형성방법은 TiN을 게이트의 상부에 증착하여 금속 확산 방지막으로 사용함으로써, 금속 확산 방지막의 재료인 TiN은 700℃정도에서 상변태온도를 가지므로, 금속박막의 증착 후 700℃이상의 열공정을 거치면서 금속박막이 게이트를 구성하는 다결정실리콘으로 확산되어, 소자의 특성을 열화시키는 문제점이 있었다. 이와 같은 문제점을 감안한 본 발명은 기판의 상부에 게이트 산화막을 증착하는 게이트 산화막 증착단계와; 상기 게이트 산화막의 상부에 다결정실리콘을 증착하고, 그 다결정실리콘에 질소를 주입하여 특정 위치에 질소 도핑층을 갖는 다결정실리콘을 형성하는 확산 방지막 형성단계와; 상기 질소가 도핑된 다결정실리콘의 상부에 텅스텐을 증착하여 금속박막을 형성하는 금속박막 형성단계로 이루어져 일함수가 다결정실리콘과 같은 질소를 다결정실리콘에 증착한 질소 도핑 다결정실리콘을 반도체 소자의 게이트로 사용하여 반도체 소자의 문턱전압을 일정하게 유지시킴과 아울러 고온공정에서도 텅스텐이 확산을 방지하여 반도체 소자의 특성을 향상시키는 효과가 있다.The present invention relates to a method for forming a metal diffusion barrier of a semiconductor device. In the conventional method of forming a metal diffusion barrier of a semiconductor device, TiN is deposited on top of a gate and used as a metal diffusion barrier. Since it has a phase transformation temperature in the degree, the metal thin film is diffused into the polycrystalline silicon constituting the gate through the thermal process of 700 ℃ or more after the deposition of the metal thin film, there is a problem that deteriorates the characteristics of the device. In view of the above problems, the present invention includes a gate oxide film deposition step of depositing a gate oxide film on the substrate; Forming a polysilicon layer on the gate oxide layer and injecting nitrogen into the polysilicon layer to form polysilicon having a nitrogen doping layer at a specific position; A metal thin film forming step of forming a metal thin film by depositing tungsten on top of the nitrogen-doped polycrystalline silicon to form a metal thin film work function using a nitrogen-doped polycrystalline silicon in which nitrogen, such as polycrystalline silicon is deposited on the polycrystalline silicon as a gate of the semiconductor device Therefore, the threshold voltage of the semiconductor device is kept constant, and tungsten is prevented from being diffused even at a high temperature process, thereby improving the characteristics of the semiconductor device.
Description
본 발명은 반도체 소자의 금속 확산 방지막 제조방법에 관한 것으로, 특히 반도체 소자의 게이트의 상부에 질소원자가 도핑된 다결정실리콘을 증착하고, 이 질소원자가 도핑된 다결정실리콘을 금속 확산 방지막으로 사용함으로써, 반도체 소자의 특성을 향상시키는데 적당하도록 한 반도체 소자의 금속 확산 방지막 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a metal diffusion barrier film of a semiconductor device, and more particularly, by depositing polycrystalline silicon doped with nitrogen atoms on an upper portion of a gate of a semiconductor device, and using the nitrogen crystal doped polycrystalline silicon as a metal diffusion barrier. The present invention relates to a method for manufacturing a metal diffusion barrier of a semiconductor device, which is suitable for improving the characteristics of the semiconductor device.
일반적으로, 반도체 소자의 게이트의 상부에는 외부의 전원이 인가되는 금속배선이 접속되며, 이와 같이 게이트의 상부에 금속을 증착하는 경우, 증착되는 금속이 게이트에 확산되어 게이트의 두께를 변화시켜 반도체 소자의 문턱전압을 변화시키는 요인이 된다. 이를 방지하기 위해 게이트의 상부에 증착되는 금속이 게이트에 확산되는 것을 방지하기 위해 게이트의 상부에 확산 방지층을 먼저 증착한 후, 금속을 증착하게 된다.In general, a metal wiring to which an external power source is applied is connected to an upper portion of a gate of the semiconductor element. In the case of depositing a metal on the upper portion of the gate, the deposited metal is diffused to the gate to change the thickness of the gate element. It is a factor that changes the threshold voltage of. To prevent this, the diffusion barrier layer is first deposited on the gate to prevent the metal deposited on the gate from diffusing to the gate, and then the metal is deposited.
상기와 같은 기능의 확산 방지막의 재료로 종래에는 TiN을 사용하였으나, 상기 TiN은 700℃이상의 온도에서는 상이 변하게 되어 확산 방지막의 재료로서의 작용이 불가능하여 다른 대체 물질이 요구되고 있으며, 이와 같은 종래 반도체 소자의 금속 확산 방지막 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Conventionally, TiN was used as a material of the diffusion barrier film having the above function, but the TiN phase changed at a temperature of 700 ° C. or higher, so that it could not function as a material of the diffusion barrier film, and thus, another alternative material was required. If described in detail with reference to the accompanying drawings a method of manufacturing a metal diffusion barrier film of.
도1은 종래 확산 방지막이 형성된 반도체 소자의 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 게이트 산화막(2)과 다결정실리콘(3)을 증착하고, 사진 식각공정으로 상기 다결정실리콘(3), 게이트 산화막(2)을 부분적으로 식각하여, 게이트를 형성하는 단계와; 상기 게이트의 상부에 TiN을 증착하여 확산 방지막(4)을 형성하는 단계와; 상기 확산 방지막(4)의 상부에 금속박막을 증착하는 단계로 제조된다.1 is a cross-sectional view of a semiconductor device in which a diffusion barrier film is formed. As shown in FIG. 1, a gate oxide film 2 and a polysilicon 3 are deposited on an upper portion of a substrate 1, and the polysilicon 3 is formed by a photolithography process. ), Partially etching the gate oxide film 2 to form a gate; Depositing TiN on the gate to form a diffusion barrier (4); It is prepared by depositing a metal thin film on the diffusion barrier (4).
이하, 상기와 같은 종래 반도체 소자의 확산 방지막 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing the diffusion barrier of the conventional semiconductor device as described above will be described in more detail.
먼저, 반도체 기판(1)의 상부에 소자가 형성될 영역과 각 소자의 절연영역을 정의하고, 상기 기판(1)의 상부에 게이트 산화막(2)과 다결정실리콘(3)을 증착한다. 이때, 다결정실리콘(3)은 도핑되지 않은 것을 사용하였다.First, a region in which an element is to be formed and an insulating region of each element are defined on the semiconductor substrate 1, and a gate oxide film 2 and a polysilicon 3 are deposited on the substrate 1. At this time, the polysilicon 3 was used that is not doped.
그 다음, 상기 다결정실리콘(3)의 상부에 포토레지스트를 도포하고, 노광하여 게이트 패턴을 형성하고, 그 패턴이 형성된 포토레지스트를 식각 마스크로 사용하는 식각공정으로 상기 다결정실리콘(3)과 게이트 산화막(2)을 식각하여 게이트를 형성한다. 그리고, 그 게이트의 좌우측 기판의 하부에 불순물을 이온주입하여 소스 및 드레인을 형성하여 모스 트랜지스터의 구조를 완성하게 되나 설명의 편의상 도면에 나타내지 않았다.Next, a photoresist is applied on the polysilicon 3 and exposed to form a gate pattern, and the polysilicon 3 and the gate oxide film are etched using an etch mask using the photoresist on which the pattern is formed. (2) is etched to form a gate. The source and the drain are formed by ion implantation of impurities into the lower left and right substrates of the gate to complete the structure of the MOS transistor, but are not shown in the drawings for convenience of description.
그 다음, 상기 다결정실리콘(3)의 상부에 TiN을 소정 두께 증착하여 금속의 확산 방지막(4)을 형성한다.Next, TiN is deposited on the polysilicon 3 to a predetermined thickness to form a metal diffusion barrier 4.
그 다음, 상기 확산방지막(4)의 상부에 텅스텐을 증착하여 금속박막(5)을 형성하게 된다. 이때 금속박막(5)의 성분인 텅스텐을 증착하고, 700℃이상의 열공정으로 상기 금속박막(5)을 활성화하는 공정에서 상기 확산 방지막(4)은 그 상태가 변하게 되어 상기 금속박막(5)의 성분인 텅스텐이 게이트를 구성하는 다결정실리콘(3)의 상부로 확산되어 반도체 소자의 특성을 열화시키게 된다.Next, tungsten is deposited on the diffusion barrier 4 to form the metal thin film 5. At this time, in the process of depositing tungsten which is a component of the metal thin film 5 and activating the metal thin film 5 by a thermal process of 700 ° C. or more, the diffusion preventing film 4 is changed in state. Tungsten, a component, is diffused to the upper part of the polysilicon 3 constituting the gate to deteriorate the characteristics of the semiconductor device.
상기한 바와 같이 종래 반도체 소자의 금속 확산 방지막 형성방법은 TiN을 게이트의 상부에 증착하여 금속 확산 방지막으로 사용함으로써, 금속 확산 방지막의 재료인 TiN은 700℃정도에서 상변태온도를 가지므로, 금속박막의 증착 후 700℃이상의 열공정을 거치면서 금속박막이 게이트를 구성하는 다결정실리콘으로 확산되어, 소자의 특성을 열화시키는 문제점이 있었다.As described above, in the method of forming a metal diffusion barrier of a semiconductor device, TiN is deposited on top of a gate and used as a metal diffusion barrier. Thus, TiN, which is a material of the metal diffusion barrier, has a phase transformation temperature at about 700 ° C. After the deposition, the metal thin film is diffused into the polycrystalline silicon constituting the gate through a thermal process of 700 ° C. or more, thereby degrading the characteristics of the device.
이와 같은 문제점을 감안한 본 발명은 금속박막의 증착 후 실시하는 열공정시에도 금속이 게이트로 확산되는 것을 방지하는 반도체 소자의 금속 확산 방지막 제조방법을 제공함에 그 목적이 있다.In view of the above problems, an object of the present invention is to provide a method for manufacturing a metal diffusion prevention film of a semiconductor device which prevents metal from diffusing to a gate even in a thermal process performed after deposition of a metal thin film.
도1은 종래 금속 확산 방지막이 형성된 반도체 소자의 단면도.1 is a cross-sectional view of a semiconductor device in which a conventional metal diffusion barrier film is formed.
도2는 본 발명에 의한 금속 확산 방지막이 형성된 반도체 소자의 일실시예도.Figure 2 is an embodiment of a semiconductor device having a metal diffusion barrier according to the present invention.
도3은 본 발명에 의한 금속 확산 방지막이 형성된 반도체 소자의 일실시예도.Figure 3 is an embodiment of a semiconductor device having a metal diffusion barrier according to the present invention.
도4는 본 발명에 의한 금속 확산 방지막이 형성된 반도체 소자의 일실시예도.Figure 4 is an embodiment of a semiconductor device having a metal diffusion barrier according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1:기판 2:게이트 산화막1: Substrate 2: Gate oxide film
5:금속박막 6:질소가 도핑된 다결정실리콘5: Metal thin film 6: Ni-doped polycrystalline silicon
상기와 같은 목적은 기판의 상부에 게이트 산화막을 증착하는 게이트 산화막 증착단계와; 상기 게이트 산화막의 상부에 다결정실리콘을 증착하고, 그 다결정실리콘에 질소를 주입하여 특정 위치에 질소 도핑층을 갖는 다결정실리콘을 형성하는 확산 방지막 형성단계와; 상기 질소가 도핑된 다결정실리콘의 상부에 텅스텐을 증착하여 금속박막을 형성하는 금속박막 형성단계로 구성하여 일함수가 다결정실리콘과 같은 질소를 다결정실리콘에 증착한 질소 도핑 다결정실리콘을 반도체 소자의 게이트로 사용하여 반도체 소자의 문턱전압을 일정하게 유지시킴으로써 달성되는 것으로, 이와 같은 본 발명을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.The above object is a gate oxide film deposition step of depositing a gate oxide film on top of the substrate; Forming a polysilicon layer on the gate oxide layer and injecting nitrogen into the polysilicon layer to form polysilicon having a nitrogen doping layer at a specific position; A metal thin film forming step of forming a metal thin film by depositing tungsten on top of the nitrogen-doped polycrystalline silicon to form a metal thin film, the function of the nitrogen-doped polycrystalline silicon in which nitrogen, such as polycrystalline silicon is deposited on the polycrystalline silicon as a gate of the semiconductor device This is achieved by maintaining a constant voltage of the semiconductor device by using the present invention, which will be described in detail with reference to the accompanying drawings.
도2, 도3 및 도4는 각각 본 발명 반도체 소자의 금속 확산 방지막 제조방법의 일실시예에 따른 반도체 소자의 단면도로서, 이에 도시한 바와 같이 기판(1)의 상부에 게이트 산화막(2)이 증착되고, 그 게이트 산화막(3)의 상부에는 질소가 도핑된 다결정실리콘(6)이 증착되며, 상기 다결정실리콘(6)의 상부에는 금속박막(5)이 증착된 구조를 갖는다.2, 3 and 4 are cross-sectional views of a semiconductor device according to an embodiment of the method for manufacturing a metal diffusion barrier film of the semiconductor device of the present invention, respectively. As shown therein, a gate oxide film 2 is formed on the substrate 1. The polycrystalline silicon 6 doped with nitrogen is deposited on the gate oxide film 3, and the metal thin film 5 is deposited on the polycrystalline silicon 6.
이때 도2는 게이트 산화막(2)의 상부에 질소가 전체에 도핑된 다결정실리콘(6)을 게이트전극과 금속 확산 방지막으로 사용하며, 도3과 도4는 각각 상부일부와 중간에 질소가 도핑된 질소도핑층을 갖는 다결정실리콘(6)을 갖는 구조이다.2 uses polycrystalline silicon 6 doped entirely with nitrogen on the gate oxide film 2 as a gate electrode and a metal diffusion preventing film, and FIGS. 3 and 4 are respectively doped with nitrogen in an upper portion and in the middle thereof. It is the structure which has the polysilicon 6 which has a nitrogen doping layer.
이와 같은 구조의 반도체 소자는 기판(1)의 상부에 게이트 산화막(2)을 증착하는 단계와; 상기 게이트 산화막(2)의 상부에 다결정실리콘을 증착하고, 그 다결정실리콘에 질소를 주입하여 특정 위치에 질소 도핑층을 갖는 다결정실리콘(6)을 형성하는 단계와; 상기 질소가 도핑된 다결정실리콘(6)의 상부에 텅스텐을 증착하여 금속박막(5)을 형성하는 단계로 이루어진다.A semiconductor device having such a structure includes the steps of depositing a gate oxide film 2 on the substrate 1; Depositing polycrystalline silicon on the gate oxide film (2), and injecting nitrogen into the polycrystalline silicon to form polycrystalline silicon (6) having a nitrogen doping layer at a specific position; And depositing tungsten on the nitrogen-doped polysilicon 6 to form the metal thin film 5.
이하, 상기와 같은 본 발명 반도체 소자의 금속 확산 방지막 제조방법을 좀 더 상세히 설명한다.Hereinafter, a method of manufacturing the metal diffusion barrier of the semiconductor device of the present invention as described above will be described in more detail.
먼저, 기판(1)에 반도체 소자가 제조될 영역과 각각의 소자를 분리하는 영역을 정의하고, 그 기판(1)의 상부에 게이트 산화막(2)을 형성한다.First, a region in which a semiconductor element is to be manufactured and a region separating each element are defined in the substrate 1, and a gate oxide film 2 is formed on the substrate 1.
그 다음, 상기 게이트 산화막(2)의 상부에 다결정실리콘을 증착하고, 그 다결정실리콘에 질소를 주입한다. 이때 질소주입에너지를 조절하여 원하는 위치에 질소를 주입하고, 어닐링을 통해 활성화 시켜, 질소가 도핑된 다결정실리콘(6)을 형성한다.Next, polycrystalline silicon is deposited on the gate oxide film 2, and nitrogen is injected into the polycrystalline silicon. At this time, the nitrogen injection energy is adjusted to inject nitrogen at a desired position, and activated through annealing to form polycrystalline silicon 6 doped with nitrogen.
그 다음, 상기 질소가 도핑된 다결정실리콘(6)의 상부에 텅스텐을 증착하여 금속박막(5)을 형성한다.Next, tungsten is deposited on the nitrogen-doped polycrystalline silicon 6 to form a metal thin film 5.
그 다음, 상기 금속박막(5)의 형성 후, 열공정을 통해 상기 금속박막(5)을 활성화하며, 이때, 도2의 상기 질소가 다결정실리콘의 전면에 도핑되어 형성한 다결정실리콘(6)의 질소는 상기 금속박막(5)의 재료인 텅스텐과 결합하여 텅스텐과 다결정실리콘(6)과 결합하는 것을 막아 금속박막(5)이 확산되는 것을 방지한다. 즉, 텅스텐과 질소의 결합은 열역학적으로 안정된 화합물이므로 이후에 텅스텐과 다결정실리콘이 반응하는 것을 방지하게 된다.Then, after the formation of the metal thin film 5, the metal thin film 5 is activated through a thermal process, in which the nitrogen of Figure 2 of the polycrystalline silicon (6) formed by doping the entire surface of the polysilicon Nitrogen is bonded to tungsten, which is the material of the metal thin film 5, to prevent the tungsten and polycrystalline silicon 6 from being bonded, thereby preventing the metal thin film 5 from being diffused. That is, the combination of tungsten and nitrogen is a thermodynamically stable compound to prevent the reaction of tungsten and polysilicon later.
그리고, 상기 도3에 도시한 질소가 상부에만 도핑된 다결정실리콘(6)은 저항이 다결정실리콘 보다 높은 질소 도핑층을 상부에 형성하여 전체적인 저항을 작게 할 수 있으며, 도4에 도시한 질소가 중간에 도핑된 다결정실리콘(6)은 질소 도핑층의 상부에 위치하는 다결정실리콘에 텅스텐이 확산되나, 질소 도핑층의 하부로는 텅스텐의 확산을 방지하여 금속, 실리사이드, 질소 도핑층, 다결정실리콘의 구조를 특별한 구조를 형성하여 필요에 따라 사용할 수 있다.In addition, the polysilicon 6 doped only with the nitrogen shown in FIG. 3 may form a nitrogen doping layer having a higher resistance than the polysilicon to reduce the overall resistance, and the nitrogen shown in FIG. The doped polysilicon 6 has tungsten diffused into the polycrystalline silicon positioned on the upper portion of the nitrogen doped layer, but the lower portion of the nitrogen doped layer prevents the diffusion of tungsten so that the structure of the metal, silicide, nitrogen doped layer, and polycrystalline silicon Can be used as needed to form a special structure.
상기한 바와 같이 본 발명 반도체 소자의 금속 확산 방지막 형성방법은 일함수가 다결정실리콘과 같은 질소를 다결정실리콘에 증착한 질소 도핑 다결정실리콘을 반도체 소자의 게이트로 사용하여 반도체 소자의 문턱전압을 일정하게 유지시킴과 아울러 고온공정에서도 텅스텐이 확산을 방지하여 반도체 소자의 특성을 향상시키는 효과가 있다.As described above, in the method of forming a metal diffusion barrier film of the semiconductor device of the present invention, the threshold voltage of the semiconductor device is kept constant by using a nitrogen-doped polysilicon obtained by depositing nitrogen such as polycrystalline silicon on the polycrystalline silicon as a gate of the semiconductor device. In addition, tungsten is prevented from diffusing in high temperature processes, thereby improving the characteristics of the semiconductor device.
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| KR100378062B1 (en) * | 1999-09-01 | 2003-03-29 | 전영권 | Method of forming material film |
| US9349821B2 (en) | 2010-07-02 | 2016-05-24 | Samsung Electronics Co., Ltd. | Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure |
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| KR100378062B1 (en) * | 1999-09-01 | 2003-03-29 | 전영권 | Method of forming material film |
| US9349821B2 (en) | 2010-07-02 | 2016-05-24 | Samsung Electronics Co., Ltd. | Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure |
| US10685959B2 (en) | 2010-07-02 | 2020-06-16 | Samsung Electronics Co., Ltd. | Electrode structure, method of fabricating the same, and semiconductor device including the electrode structure |
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