KR19990026127A - Digital-to-analog conversion circuit for high integration - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-analog conversion circuit, and more particularly, to a digital-analog conversion circuit for minimizing an area. An analog conversion circuit, comprising: a first decoder for decoding switch bits of a first group of the N-bit digital signals to generate switch driving signals; A second decoder for decoding the bits of the second group except for the first group of bits of the N-bit digital signal to generate a selection signal and non-selection signals; A voltage generator generating first voltages in response to a switch driving signal from the first decoder; A voltage divider for dividing the first voltages in equal proportions in response to the select signal and the unselected signals from the second decoder: the divided voltages in response to the select signal and the unselected signals of the second decoder; It characterized in that it comprises a selection unit for selecting one of the output. Such a circuit can reduce the area of the digital-analog conversion circuit.

Description

Digital-analog converting circuit for reducing number of devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital analog converters and, more particularly, to digital to analog converter circuits for high integration.

Digital-to-analog conversion circuits are demanding higher levels of resolution that characterize the converter as the system becomes more efficient.

1 is a circuit diagram showing the configuration of a digital-analog conversion circuit according to the prior art.

Referring to FIG. 1, the digital-to-analog converter includes a decoder 10, a voltage distribution circuit 20, and a selection circuit 30. The decoder 10 receives an N-bit digital signal from the outside and decodes it to output 2 ^N selection signals and non-selection signals, and the selection signal is a signal for selecting one of the distribution voltages of the voltage distribution circuit. to be. The voltage divider circuit 20 includes a plurality of resistors R1 to Rn connected in series between the first and second input terminals to which the upper reference voltage VREFT and the lower reference voltage VREFB are applied. The reference voltages are divided according to the resistance ratio. The selection circuit 30 selects one of several distribution voltages in response to the selection signal and the non-selection signals, which are connected to the switches {sw0 to sw (n-1)} connected to the connection points of the respective resistors. Is determined due to. The op amp connected to the output terminal of the selection circuit amplifies the level of the selected divided voltage and outputs an analog signal corresponding to the N-bit digital input signal. The digital-analog circuit having the above configuration reacts sensitively by the precision of passive elements such as resistors and switches in terms of resolution, and the resolution is an indicator of the characteristics of the transducer. Is improved.

However, the digital-to-analog converter described above has a problem in that the resistance increases exponentially as the resolution is increased and the number of bits of the input digital signal is increased. In addition, the resistance column of the voltage divider circuit is determined by the number of bits of the input digital signal to be 2 ^{N. In} the case of 4 bits, only 2 or ⁴ resistors can operate, but in the case of a 20 bit input digital signal, ^As many as ²⁰ resistors are needed. In addition, as the number of resistors increases exponentially, the number of switches corresponding to their respective connection points increases, and the area of the decoder generating signals for driving these switches also increases. As described above, as the number and area of the resistors, the switches, and the decoders increase, the noise component due to the switching increases, resulting in a deterioration of the characteristics of the digital-analog conversion circuit.

It is an object of the present invention to reduce the number of resistors and switches in a digital-to-analog conversion circuit to minimize the area and to increase the resolution.

1 is a circuit diagram showing the configuration of a digital-analog conversion circuit according to the prior art:

2 is a circuit diagram showing a configuration of a digital-analog conversion circuit according to an embodiment of the present invention:

3 is a circuit diagram showing in detail a digital-analog conversion circuit configuration according to an embodiment of the present invention:

4A is an operation timing diagram of switches in response to a drive signal of a first decoder:

4B is an operation timing diagram of switches in response to a selection signal of a second decoder:

5 shows an output of an analog signal corresponding to digital signals:

* Explanation of symbols for main parts of the drawings

100: first decoder 200: second decoder

300: voltage generator 400: voltage divider

500: selection

(Configuration)

According to one aspect for achieving the above object, in the digital-to-analog conversion circuit for receiving a digital signal of N bits (where N is a positive integer) applied from the outside and converting it to an analog signal, the A first decoder for decoding the first group of bits of the N-bit digital signal to generate switch driving signals; A second decoder for decoding the bits of the second group except for the first group of bits of the N-bit digital signal to generate a selection signal and non-selection signals; A voltage generator generating first voltages in response to a switch driving signal from the first decoder; A voltage divider for dividing the first voltages in equal proportions in response to the select signal and the unselected signals from the second decoder: the divided voltages in response to the select signal and the unselected signals of the second decoder; A selector configured to select and output one of the first and second voltage generators, the voltage generator comprising: a first input terminal configured to receive a first upper reference voltage from an external source; A second input terminal for receiving a first lower reference voltage from the outside; A first array of resistors connected in series between the first input terminal and the second input terminal; A first switch group that electrically isolates and connects the resistors in response to switch drive signals from the first decoder to separate the first resistor string and the second resistor string; And a second switch group configured to transfer a pair of first voltages to the voltage divider when the resistors are divided into a first resistor string and a second resistor string in response to the selection signals and the non-selection signal. Characterized in that.

In a preferred embodiment of the circuit, the voltage divider includes: a first node through which a second upper reference voltage is transmitted from the voltage generator; A second node through which a second lower reference voltage is transmitted from the voltage generator; And a second array of resistors connected in series between the first node and the second node.

In a preferred embodiment of this circuit, the selector comprises: a third node to which the selected divided voltage is to be delivered; And a second switch group connected between the connection point of the resistors and the third node.

In a preferred embodiment of the circuit, the first voltages are characterized in that the first upper reference voltage and the second lower reference voltage are lowered by the resistance ratio of the first resistance string and the second resistance string.

In a preferred embodiment of this circuit, the first switch group comprises: connection switches connected between the resistors; Upper and lower switches connected between both ends of the first array of resistors and the first and second power terminals, respectively.

In a preferred embodiment of this circuit, the second switch group comprises 2 ^X switch pairs connected to each end of the first switch group.

In a preferred embodiment of this circuit, the selector comprises: a third node to which the selected divided voltage is transmitted; And (2 ^Y ) switches connected between the interconnection point of the resistors and the third node.

In a preferred embodiment of this circuit, in the first group corresponding to the upper X bits of the N bits of the digital signal and the second group corresponding to the lower Y bits, the sum of the X bits and the Y bits is N. It is characterized by being a bit.

In a preferred embodiment of this circuit, the X bits of the first group are the upper N / 2 bits of the N bits divided by N / 2, and the Y bits of the second group are the remaining lower N / 2 bits. It is characterized by.

In a preferred embodiment of this circuit, the first group has fewer bits than the upper N / 2 bits, and the second group has more bits than the lower N / 2 bits.

In a preferred embodiment of this circuit, the first group has more bits than the upper N / 2 bits, and the second group has fewer bits than the lower N / 2 bits.

In a preferred embodiment of this circuit, the first array of resistors comprises (2 ^X -1) resistors having the same resistance value.

In a preferred embodiment of this circuit, the second array of resistors comprises (2 ^Y ) resistors having the same resistance value.

(Example)

2 is a block diagram showing the configuration of a digital-analog conversion circuit according to an embodiment of the present invention.

The digital-analog conversion circuit includes a first decoder 100, a second decoder 200, a voltage generator circuit 300, a voltage divider circuit 400, and a select circuit 500. The first decoder 100 decodes the X-bit signal from the most significant bit of the N-bit digital signal to generate switch driving signals, and the second decoder 100 decodes the Y-bit signal from the least significant bit to select and deselect the signal. Generate selection signals. In addition, the voltage generation circuit 300 receives a first upper reference voltage VREFT1 and a first lower reference voltage VREFB1 from the outside and transfers the voltages generated in response to the driving signals to the voltage distribution circuit 400. Is authorized. The voltages VREFT2 and VREFB2 delivered from the voltage generation circuit 300 are distributed at a predetermined rate through the voltage distribution circuit 400, and the divided voltages are output through the selection circuit 500.

3 is a circuit diagram showing in detail the configuration of a digital-analog conversion circuit for a 4-bit digital signal.

The first decoder 100 and the second decoder 200 receive an N-bit digital signal by dividing an upper X bit and a lower Y bit to perform an operation, and the sum of the upper X bit and the lower Y bit is N. Bit. The first decoder 100 receives the first group of bits to generate (2 ^{X + 1} ) driving signals, and the driving signals are divided into a first driving signal group and a second driving signal group. The second decoder 200 receives the second group of bits and generates 2 ^Y select signals and non-select signals. The driving signals are for turning off the switches swi, swti, swbi, and the selection signals are signals for selecting one of the distribution voltages of the voltage distribution circuit 400.

The voltage generation circuit 300 includes resistors RM1 arranged in series between the first input terminal 1 to which the upper reference voltage VREFT is applied and the second input terminal 2 to which the lower reference voltage VREFB is applied. A first switch group sw0, sw1, sw2 connected between the resistors R and at both ends of the first and second input terminals 1 and 2 and the resistor array; , sw3). The second switch pairs swti and swbi connected to both ends of each switch of the first switch group sw0, sw1, sw2 and sw3 have the other ends common to the first node N1 and the second node N2. Is connected. That is, the upper switches swt0, swt1, swt2 and swt3 connected to the upper end of each switch swi in the first switch group among the second switch pairs wt and swb are commonly connected to the first node N1. The lower switches swb0, swb1, swb2, and swbB3 connected to the lower ends of the switches swi are commonly connected to the other ends of the second node N2.

Subsequently, the voltage distribution circuit 400 includes resistors RL1 to RL4 connected in series between the first node N1 and the second node N2, and the selection circuit 500 includes the resistors. Switches swl1, swl2, swl3, swl4 corresponding to the interconnection points of RL1 to RL4. An op amp is provided at the output terminal of the selection circuit 500. Since the op amp is well known to those skilled in the art, the following description is omitted.

Hereinafter, a detailed example of converting a 4-bit digital signal into an analog signal in the digital-analog conversion circuit having the above-described configuration will be described with reference to FIGS. 3 to 4A and 4B.

4A is an operation timing diagram of the first switch group.

4B is an operation timing diagram of the second switch group.

Referring to FIG. 3, the first decoder 100 and the second decoder 200 divide a 4-bit input digital signal into two bits and apply them to the first decoder 100 and the second decoder 200. The sum of the upper X bits applied to the first decoder 100 and the lower Y bits applied to the second decoder 200 even if the input signals applied to the first decoder 100 and the second decoder 200 are not necessarily 2 bits. The N-bit digital signal needs only to be used. In this case, the 4-bit digital input signal is divided into half bits for input. For example, when you want to convert the digital signal into an analog signal 0110, a first decoder 100 accepts the 01 of the upper two bits and outputs ²³ of the switch drive signal after decoding it. Half of the drive signals are applied to first switches swi that electrically insulate or connect the resistors RMi, and the other half of the second switch pairs that are connected to the first switches swi. (swti, swbi). The number of resistors varies depending on the number of bits input to the first decoder 100. In the case of 2 bits as described above, 2 ^2-1 are required.

Referring to FIG. 4A, in response to the driving signals for 01, only the sw1 of the first switches swi is turned off and the remaining sw0, sw2, sw3 are turned on in response to the driving signals for 01. Therefore, the resistor array is provided with the first resistance strings RM3 and RM4 and the lower reference voltage VREFB connected in series to the first input terminal 1 to which the upper reference voltage VREFT is applied. The second resistor string RM1 is connected to the second input terminal 2 in series. The second switch pairs swti and swbi respectively connected to both ends of the first switches swi are sw1 in response to the remaining driving signals except for the driving signals applied to the first switches swi. The remaining switch pairs swt0, swbO / swt2, swb2 / swt3 and swb3 are turned off except for swt1 and swb1 connected to both ends. As the second switch pairs swt1 and swb1 are turned on, the upper reference voltage VREFT is lowered by the resistance ratio of the first resistor string to be transferred to the first node N1 through swt1, and the lower reference voltage VREFB is set to the first voltage. The voltage drops by the resistance ratio of the two resistance strings, and is transferred to the second node N2 through swb1.

When the upper bit is 00, 01, 10, 11, the first switches sw0, sw1, sw2, sw3 are sequentially turned off. When 00, sw0, 01, sw1, 10, sw2 and 11 sw3 is turned off sequentially. For example, when sw0 is turned off, all resistors RM1 to RM3 are connected between the first input terminal 1 and the switches. The swt0 and swb0 pairs connected to both ends of sw0 are turned on, and the upper reference voltage VREFT drops to the first node N1 by a resistance ratio, and the lower reference voltage VREFB is transferred to the second node N2. do. In the case of 01, the operation is the same as in the case of 10, and in case of 11, when sw3 is turned off, the resistors are all connected between the second input terminal 2 and the switch. At the same time, only swt3 and swb3 connected to both ends of sw3 among the first switch pairs swti and swbi are turned on, so that the upper reference voltage VREFT is transmitted to the first node N1, and the reference voltage is transmitted to the second node N2. The voltage at which VREFB drops by the ratio of resistors is delivered. The voltage generator 300 generates four different levels of voltages according to the signal applied to the first decoder 100. The division voltage selection of the selection circuit 500 also varies according to the selection signal and the non-selection signals according to the lower bits. For example, swl1, swl2, swl3, and swl4 are sequentially turned on in response to the selection signals for the lower bits 00, 01, 10, and 11 to divide one of the voltages distributed to the resistors RL1 to RL4. Select and print.

Subsequently, the voltage distribution circuit 300 distributes the voltages transmitted to the first node N1 and the second node N2 to each resistor. In this case, the resistors (RMi) was when the first contrast to the number according to the number of bits input to the decoder 100, the second bit as shown as an example in the above is required for the dog ^22. The second decoder 200 decodes it to accept the lower bit 10 other than the upper bits 01 to ²² and outputs the selection signal and non-selection signal for selecting the divided voltage of the resistors (RLi). As shown in FIG. 4B, only swl3 is turned on in response to the selection signal and the non-selection signals, so that the corresponding distribution voltage is transferred to the third node N3 to which the switches swl1 to swl4 are commonly connected. The selected divided voltage is amplified by the op amp and output as an analog signal DAout.

Here, the range of the voltage delivered to the voltage distribution circuit 400 varies according to the operation of the switches for the driving signals generated from the first decoder 100. That is, the voltages transferred to the voltage divider circuit 400 are output after the voltage for the lower bit is selected within the divided voltage range determined by the upper bit.

5 is a diagram illustrating output of analog signals corresponding to digital signals.

When the 4-bit digital signals are sequentially applied from 0000 to 1111, analog signals are output in a step structure to them. 2 ² 2 ² -1 of the resistors and the voltage division circuit 400, a divide a digital signal of four bits into a first group of upper and lower two bits of the second group of voltage generating circuit 300, as in the Resistors are the number of resistors required for the digital-to-analog conversion circuit of the present invention. It can be seen that the number is reduced by almost half compared with the conventional need 2 2 ⁴ conventional. However, the above is a case where N bits are divided and input by N / 2 bits, and a 5-bit input digital signal is divided into an upper two bits to the first decoder 100 and a lower three bits to the second decoder 200. Figure 2 reduces the number of conventional resistance than ^five. This shows that when N bits are even bits, the resistance can be reduced to the maximum by dividing by N / 2 bits. In the case of odd bits, the number of resistors can be obtained by simply dividing and applying the N bits of the digital signal even if they are not only half bits. Can be reduced.

As described above, when the number of resistors is reduced, the number of switches connected to the connection point can be reduced, and the circuit configuration of the decoder for generating signals for driving them is simplified. According to the present invention, two resistance trains are configured according to the bit group, so that resistances do not increase exponentially even when the resolution is high.

According to the present invention, the input digital signal is divided into upper and lower bits and applied to reduce the number of resistors and the number of switches connected thereto. In addition, the circuit configuration of the decoder for driving the switches is simplified, thereby reducing the total area.

Claims (13)

In a digital-to-analog conversion circuit for receiving a digital signal of N bits (where N is a positive integer) applied from the outside and converting it to an analog signal, A first decoder for decoding the first group of bits of the N-bit digital signal to generate switch driving signals; A second decoder for decoding the bits of the second group except for the first group of bits of the N-bit digital signal to generate a selection signal and non-selection signals; Voltage generating means for generating first voltages in response to a switch drive signal from the first decoder; Voltage dividing means for distributing the first voltages in equal proportions in response to the select signal and the non-select signals from the second decoder; Selection means for selecting and outputting one of the divided voltages in response to the selection signal and the non-selection signals of the second decoder, The voltage generating means A first input terminal for receiving a first upper reference voltage from the outside; A second input terminal for receiving a first lower reference voltage from the outside; A first array of resistors connected in series between the first input terminal and the second input terminal; A first switch group that electrically isolates and connects the resistors in response to switch drive signals from the first decoder to separate the first resistor string and the second resistor string; And a second switch group that, when the resistors are separated in response to the selection signals and the non-selection signal, the reference voltages drop by the ratio of the resistors to transfer the first voltages to the voltage divider. Digital-to-analog conversion circuit, characterized in that. The method of claim 1, The voltage distribution means A first node to which a first higher reference voltage of the first voltages drops or a voltage equivalent thereto is transferred; A second node to which the first lower reference voltage of the first voltages is lowered or the equivalent voltage is transmitted; And a second array of resistors connected in series between the first node and the second node. The method of claim 1, Wherein the first voltages are voltages at which the first upper reference voltage and the first lower reference voltage are dropped by the resistance ratio of the first resistance string and the second resistance string or are voltages of the same level. The method of claim 1, The first switch group Connection switches connected between the resistors; And upper and lower switches connected between both ends of the first array of resistors and the first and second input terminals, respectively. The method of claim 1, The first group is upper bits obtained by dividing the N-bit digital signal from the most significant bit by X bits, the second group is the lower bits obtained by dividing the N bits from the least significant bits to Y bits, and the sum of the X and Y bits is N. Digital-to-analog conversion circuit, characterized in that the bit. The method of claim 5, The X bits of the first group are upper (N / 2) bits of the N bits divided into (N / 2), and the Y bits of the second group are the remaining lower (N / 2) bits. Digital-to-analog conversion circuit. The method according to claim 1 or 5, And wherein the first group has fewer bits than the upper (N / 20 bits) and the second group has more bits than the lower (N / 2) bits. The method according to claim 1 or 5 And wherein the first group has more bits than the upper (N / 2) bits and the second group has fewer bits than the lower (N / 2) bits. The method according to claim 1 or 5, And the first array of resistors comprises (2 ^× -1) resistors having the same resistance value. The method of claim 4, wherein And the second array of resistors comprises (2 ^Y ) resistors having the same resistance value. The method according to claim 1 or 5, And said second switch group comprises 2 ^X switch pairs connected to each end of said first switch group. The method according to claim 1 or 2 or 5, The selection means comprising: a third node to which a selected divided voltage is transmitted in response to the selection signal; And (2 ^Y ) switches connected between the interconnection point of the resistors and the third node. In a digital-analog conversion circuit for converting an N bit digital signal into an analog signal and outputting the same, An upper bit decoder for decoding upper X bits (where X is a positive integer) of the N bits of digital signals and outputting selected signals, unselected signals, and their complementary signals; A lower bit decoder which decodes the lower Y bits (where Y is a positive integer) of the N bits of digital signals and outputs selection signals and non-selection signals; Voltage generation means for receiving reference voltages from an external source and generating an upper reference voltage of a first level and a lower reference voltage of a second level in response to the selection signal and its non-suntec signals; Voltage distribution means for equally distributing an upper reference voltage of the first level and a lower reference voltage difference of a second level; And selecting means for selecting one of said divided voltages.